:option:::insn-bit-size:16
|
:option:::insn-bit-size:16
|
:option:::hi-bit-nr:15
|
:option:::hi-bit-nr:15
|
|
|
|
|
:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
|
:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
|
:option:::format-names:XI,XII,XIII
|
:option:::format-names:XI,XII,XIII
|
:option:::format-names:XIV,XV
|
:option:::format-names:XIV,XV
|
:option:::format-names:Z
|
:option:::format-names:Z
|
|
|
|
|
:model:::v850:v850:
|
:model:::v850:v850:
|
|
|
:option:::multi-sim:true
|
:option:::multi-sim:true
|
:model:::v850e:v850e:
|
:model:::v850e:v850e:
|
:option:::multi-sim:true
|
:option:::multi-sim:true
|
:model:::v850e1:v850e1:
|
:model:::v850e1:v850e1:
|
|
|
// Cache macros
|
// Cache macros
|
|
|
:cache:::unsigned:reg1:RRRRR:(RRRRR)
|
:cache:::unsigned:reg1:RRRRR:(RRRRR)
|
:cache:::unsigned:reg2:rrrrr:(rrrrr)
|
:cache:::unsigned:reg2:rrrrr:(rrrrr)
|
:cache:::unsigned:reg3:wwwww:(wwwww)
|
:cache:::unsigned:reg3:wwwww:(wwwww)
|
|
|
:cache:::unsigned:disp4:dddd:(dddd)
|
:cache:::unsigned:disp4:dddd:(dddd)
|
:cache:::unsigned:disp5:dddd:(dddd << 1)
|
:cache:::unsigned:disp5:dddd:(dddd << 1)
|
:cache:::unsigned:disp7:ddddddd:ddddddd
|
:cache:::unsigned:disp7:ddddddd:ddddddd
|
:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
|
:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
|
:cache:::unsigned:disp8:dddddd:(dddddd << 2)
|
:cache:::unsigned:disp8:dddddd:(dddddd << 2)
|
:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
|
:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
|
:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
|
:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
|
:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
|
:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
|
:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
|
:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
|
|
|
:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
|
:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
|
:cache:::unsigned:imm6:iiiiii:iiiiii
|
:cache:::unsigned:imm6:iiiiii:iiiiii
|
:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
|
:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
|
:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
|
:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
|
:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
|
:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
|
:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
|
:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
|
:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
|
:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
|
:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
|
:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
|
|
|
:cache:::unsigned:vector:iiiii:iiiii
|
:cache:::unsigned:vector:iiiii:iiiii
|
|
|
:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
|
:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
|
:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
|
:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
|
|
|
:cache:::unsigned:bit3:bbb:bbb
|
:cache:::unsigned:bit3:bbb:bbb
|
|
|
|
|
// What do we do with an illegal instruction?
|
// What do we do with an illegal instruction?
|
:internal::::illegal:
|
:internal::::illegal:
|
{
|
{
|
sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
|
sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
|
(unsigned long) cia);
|
(unsigned long) cia);
|
sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
|
sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
|
}
|
}
|
|
|
|
|
|
|
// Add
|
// Add
|
|
|
rrrrr,001110,RRRRR:I:::add
|
rrrrr,001110,RRRRR:I:::add
|
"add r, r"
|
"add r, r"
|
{
|
{
|
COMPAT_1 (OP_1C0 ());
|
COMPAT_1 (OP_1C0 ());
|
}
|
}
|
|
|
rrrrr,010010,iiiii:II:::add
|
rrrrr,010010,iiiii:II:::add
|
"add ,r"
|
"add ,r"
|
{
|
{
|
COMPAT_1 (OP_240 ());
|
COMPAT_1 (OP_240 ());
|
}
|
}
|
|
|
|
|
|
|
// ADDI
|
// ADDI
|
rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
|
rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
|
"addi , r, r"
|
"addi , r, r"
|
{
|
{
|
COMPAT_2 (OP_600 ());
|
COMPAT_2 (OP_600 ());
|
}
|
}
|
|
|
|
|
|
|
// AND
|
// AND
|
rrrrr,001010,RRRRR:I:::and
|
rrrrr,001010,RRRRR:I:::and
|
"and r, r"
|
"and r, r"
|
{
|
{
|
COMPAT_1 (OP_140 ());
|
COMPAT_1 (OP_140 ());
|
}
|
}
|
|
|
|
|
|
|
// ANDI
|
// ANDI
|
rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
|
rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
|
"andi , r, r"
|
"andi , r, r"
|
{
|
{
|
COMPAT_2 (OP_6C0 ());
|
COMPAT_2 (OP_6C0 ());
|
}
|
}
|
|
|
|
|
|
|
// Map condition code to a string
|
// Map condition code to a string
|
:%s::::cccc:int cccc
|
:%s::::cccc:int cccc
|
{
|
{
|
switch (cccc)
|
switch (cccc)
|
{
|
{
|
case 0xf: return "gt";
|
case 0xf: return "gt";
|
case 0xe: return "ge";
|
case 0xe: return "ge";
|
case 0x6: return "lt";
|
case 0x6: return "lt";
|
|
|
case 0x7: return "le";
|
case 0x7: return "le";
|
|
|
case 0xb: return "h";
|
case 0xb: return "h";
|
case 0x9: return "nl";
|
case 0x9: return "nl";
|
case 0x1: return "l";
|
case 0x1: return "l";
|
|
|
case 0x3: return "nh";
|
case 0x3: return "nh";
|
|
|
case 0x2: return "e";
|
case 0x2: return "e";
|
|
|
case 0xa: return "ne";
|
case 0xa: return "ne";
|
|
|
case 0x0: return "v";
|
case 0x0: return "v";
|
case 0x8: return "nv";
|
case 0x8: return "nv";
|
case 0x4: return "n";
|
case 0x4: return "n";
|
case 0xc: return "p";
|
case 0xc: return "p";
|
/* case 0x1: return "c"; */
|
/* case 0x1: return "c"; */
|
/* case 0x9: return "nc"; */
|
/* case 0x9: return "nc"; */
|
/* case 0x2: return "z"; */
|
/* case 0x2: return "z"; */
|
/* case 0xa: return "nz"; */
|
/* case 0xa: return "nz"; */
|
case 0x5: return "r"; /* always */
|
case 0x5: return "r"; /* always */
|
case 0xd: return "sa";
|
case 0xd: return "sa";
|
}
|
}
|
return "(null)";
|
return "(null)";
|
}
|
}
|
|
|
|
|
// Bcond
|
// Bcond
|
ddddd,1011,ddd,cccc:III:::Bcond
|
ddddd,1011,ddd,cccc:III:::Bcond
|
"b%s "
|
"b%s "
|
{
|
{
|
int cond;
|
int cond;
|
if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
|
if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
|
// Special case - treat "br *" like illegal instruction
|
// Special case - treat "br *" like illegal instruction
|
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
|
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
|
} else {
|
} else {
|
cond = condition_met (cccc);
|
cond = condition_met (cccc);
|
if (cond)
|
if (cond)
|
nia = cia + disp9;
|
nia = cia + disp9;
|
TRACE_BRANCH1 (cond);
|
TRACE_BRANCH1 (cond);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
// BSH
|
// BSH
|
rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
|
rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"bsh r, r"
|
"bsh r, r"
|
{
|
{
|
unsigned32 value;
|
unsigned32 value;
|
TRACE_ALU_INPUT1 (GR[reg2]);
|
TRACE_ALU_INPUT1 (GR[reg2]);
|
|
|
value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
|
value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
|
| MOVED32 (GR[reg2], 31, 24, 23, 16)
|
| MOVED32 (GR[reg2], 31, 24, 23, 16)
|
| MOVED32 (GR[reg2], 7, 0, 15, 8)
|
| MOVED32 (GR[reg2], 7, 0, 15, 8)
|
| MOVED32 (GR[reg2], 15, 8, 7, 0));
|
| MOVED32 (GR[reg2], 15, 8, 7, 0));
|
|
|
GR[reg3] = value;
|
GR[reg3] = value;
|
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
if ((value & 0xffff) == 0) PSW |= PSW_Z;
|
if ((value & 0xffff) == 0) PSW |= PSW_Z;
|
if (value & 0x80000000) PSW |= PSW_S;
|
if (value & 0x80000000) PSW |= PSW_S;
|
if (((value & 0xff) == 0) || ((value & 0xff00) == 0)) PSW |= PSW_CY;
|
if (((value & 0xff) == 0) || ((value & 0xff00) == 0)) PSW |= PSW_CY;
|
|
|
TRACE_ALU_RESULT (GR[reg3]);
|
TRACE_ALU_RESULT (GR[reg3]);
|
}
|
}
|
|
|
// BSW
|
// BSW
|
rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
|
rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"bsw r, r"
|
"bsw r, r"
|
{
|
{
|
#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
|
#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
|
unsigned32 value;
|
unsigned32 value;
|
TRACE_ALU_INPUT1 (GR[reg2]);
|
TRACE_ALU_INPUT1 (GR[reg2]);
|
|
|
value = GR[reg2];
|
value = GR[reg2];
|
value >>= 24;
|
value >>= 24;
|
value |= (GR[reg2] << 24);
|
value |= (GR[reg2] << 24);
|
value |= ((GR[reg2] << 8) & 0x00ff0000);
|
value |= ((GR[reg2] << 8) & 0x00ff0000);
|
value |= ((GR[reg2] >> 8) & 0x0000ff00);
|
value |= ((GR[reg2] >> 8) & 0x0000ff00);
|
GR[reg3] = value;
|
GR[reg3] = value;
|
|
|
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
|
if (value == 0) PSW |= PSW_Z;
|
if (value == 0) PSW |= PSW_Z;
|
if (value & 0x80000000) PSW |= PSW_S;
|
if (value & 0x80000000) PSW |= PSW_S;
|
if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
|
if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
|
|
|
TRACE_ALU_RESULT (GR[reg3]);
|
TRACE_ALU_RESULT (GR[reg3]);
|
}
|
}
|
|
|
// CALLT
|
// CALLT
|
0000001000,iiiiii:II:::callt
|
0000001000,iiiiii:II:::callt
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"callt "
|
"callt "
|
{
|
{
|
unsigned32 adr;
|
unsigned32 adr;
|
unsigned32 off;
|
unsigned32 off;
|
CTPC = cia + 2;
|
CTPC = cia + 2;
|
CTPSW = PSW;
|
CTPSW = PSW;
|
adr = (CTBP & ~1) + (imm6 << 1);
|
adr = (CTBP & ~1) + (imm6 << 1);
|
off = load_mem (adr, 2) & ~1; /* Force alignment */
|
off = load_mem (adr, 2) & ~1; /* Force alignment */
|
nia = (CTBP & ~1) + off;
|
nia = (CTBP & ~1) + off;
|
TRACE_BRANCH3 (adr, CTBP, off);
|
TRACE_BRANCH3 (adr, CTBP, off);
|
}
|
}
|
|
|
|
|
// CLR1
|
// CLR1
|
10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
|
10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
|
"clr1 , [r]"
|
"clr1 , [r]"
|
{
|
{
|
COMPAT_2 (OP_87C0 ());
|
COMPAT_2 (OP_87C0 ());
|
}
|
}
|
|
|
rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
|
rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"clr1 r, [r]"
|
"clr1 r, [r]"
|
{
|
{
|
COMPAT_2 (OP_E407E0 ());
|
COMPAT_2 (OP_E407E0 ());
|
}
|
}
|
|
|
|
|
// CTRET
|
// CTRET
|
0000011111100000 + 0000000101000100:X:::ctret
|
0000011111100000 + 0000000101000100:X:::ctret
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"ctret"
|
"ctret"
|
{
|
{
|
nia = (CTPC & ~1);
|
nia = (CTPC & ~1);
|
PSW = (CTPSW & (CPU)->psw_mask);
|
PSW = (CTPSW & (CPU)->psw_mask);
|
TRACE_BRANCH1 (PSW);
|
TRACE_BRANCH1 (PSW);
|
}
|
}
|
|
|
// CMOV
|
// CMOV
|
rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
|
rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"cmov %s, r, r, r"
|
"cmov %s, r, r, r"
|
{
|
{
|
int cond = condition_met (cccc);
|
int cond = condition_met (cccc);
|
TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
|
TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
|
GR[reg3] = cond ? GR[reg1] : GR[reg2];
|
GR[reg3] = cond ? GR[reg1] : GR[reg2];
|
TRACE_ALU_RESULT (GR[reg3]);
|
TRACE_ALU_RESULT (GR[reg3]);
|
}
|
}
|
|
|
rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
|
rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"cmov %s, , r, r"
|
"cmov %s, , r, r"
|
{
|
{
|
int cond = condition_met (cccc);
|
int cond = condition_met (cccc);
|
TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
|
TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
|
GR[reg3] = cond ? imm5 : GR[reg2];
|
GR[reg3] = cond ? imm5 : GR[reg2];
|
TRACE_ALU_RESULT (GR[reg3]);
|
TRACE_ALU_RESULT (GR[reg3]);
|
}
|
}
|
|
|
// CMP
|
// CMP
|
rrrrr,001111,RRRRR:I:::cmp
|
rrrrr,001111,RRRRR:I:::cmp
|
"cmp r, r"
|
"cmp r, r"
|
{
|
{
|
COMPAT_1 (OP_1E0 ());
|
COMPAT_1 (OP_1E0 ());
|
}
|
}
|
|
|
rrrrr,010011,iiiii:II:::cmp
|
rrrrr,010011,iiiii:II:::cmp
|
"cmp , r"
|
"cmp , r"
|
{
|
{
|
COMPAT_1 (OP_260 ());
|
COMPAT_1 (OP_260 ());
|
}
|
}
|
|
|
|
|
|
|
// DI
|
// DI
|
0000011111100000 + 0000000101100000:X:::di
|
0000011111100000 + 0000000101100000:X:::di
|
"di"
|
"di"
|
{
|
{
|
COMPAT_2 (OP_16007E0 ());
|
COMPAT_2 (OP_16007E0 ());
|
}
|
}
|
|
|
|
|
|
|
// DISPOSE
|
// DISPOSE
|
// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
|
// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
|
// "dispose , "
|
// "dispose , "
|
0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
|
0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"dispose , ":RRRRR == 0
|
"dispose , ":RRRRR == 0
|
"dispose , , [reg1]"
|
"dispose , , [reg1]"
|
{
|
{
|
int i;
|
int i;
|
SAVE_2;
|
SAVE_2;
|
|
|
trace_input ("dispose", OP_PUSHPOP1, 0);
|
trace_input ("dispose", OP_PUSHPOP1, 0);
|
|
|
SP += (OP[3] & 0x3e) << 1;
|
SP += (OP[3] & 0x3e) << 1;
|
|
|
/* Load the registers with lower number registers being retrieved
|
/* Load the registers with lower number registers being retrieved
|
from higher addresses. */
|
from higher addresses. */
|
for (i = 12; i--;)
|
for (i = 12; i--;)
|
if ((OP[3] & (1 << type1_regs[ i ])))
|
if ((OP[3] & (1 << type1_regs[ i ])))
|
{
|
{
|
State.regs[ 20 + i ] = load_mem (SP, 4);
|
State.regs[ 20 + i ] = load_mem (SP, 4);
|
SP += 4;
|
SP += 4;
|
}
|
}
|
|
|
if ((OP[3] & 0x1f0000) != 0)
|
if ((OP[3] & 0x1f0000) != 0)
|
{
|
{
|
nia = State.regs[ (OP[3] >> 16) & 0x1f];
|
nia = State.regs[ (OP[3] >> 16) & 0x1f];
|
}
|
}
|
|
|
trace_output (OP_PUSHPOP1);
|
trace_output (OP_PUSHPOP1);
|
}
|
}
|
|
|
|
|
// DIV
|
// DIV
|
rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
|
rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"div r, r, r"
|
"div r, r, r"
|
{
|
{
|
COMPAT_2 (OP_2C007E0 ());
|
COMPAT_2 (OP_2C007E0 ());
|
}
|
}
|
|
|
|
|
// DIVH
|
// DIVH
|
rrrrr!0,000010,RRRRR!0:I:::divh
|
rrrrr!0,000010,RRRRR!0:I:::divh
|
"divh r, r"
|
"divh r, r"
|
{
|
{
|
unsigned32 ov, s, z;
|
unsigned32 ov, s, z;
|
signed long int op0, op1, result;
|
signed long int op0, op1, result;
|
|
|
trace_input ("divh", OP_REG_REG, 0);
|
trace_input ("divh", OP_REG_REG, 0);
|
|
|
PC = cia;
|
PC = cia;
|
OP[0] = instruction_0 & 0x1f;
|
OP[0] = instruction_0 & 0x1f;
|
OP[1] = (instruction_0 >> 11) & 0x1f;
|
OP[1] = (instruction_0 >> 11) & 0x1f;
|
|
|
/* Compute the result. */
|
/* Compute the result. */
|
op0 = EXTEND16 (State.regs[OP[0]]);
|
op0 = EXTEND16 (State.regs[OP[0]]);
|
op1 = State.regs[OP[1]];
|
op1 = State.regs[OP[1]];
|
|
|
if (op0 == -1 && op1 == 0x80000000)
|
if (op0 == -1 && op1 == 0x80000000)
|
{
|
{
|
PSW &= ~PSW_Z;
|
PSW &= ~PSW_Z;
|
PSW |= PSW_OV | PSW_S;
|
PSW |= PSW_OV | PSW_S;
|
State.regs[OP[1]] = 0x80000000;
|
State.regs[OP[1]] = 0x80000000;
|
}
|
}
|
else if (op0 == 0)
|
else if (op0 == 0)
|
{
|
{
|
PSW |= PSW_OV;
|
PSW |= PSW_OV;
|
}
|
}
|
else
|
else
|
{
|
{
|
result = (signed32) op1 / op0;
|
result = (signed32) op1 / op0;
|
ov = 0;
|
ov = 0;
|
|
|
/* Compute the condition codes. */
|
/* Compute the condition codes. */
|
z = (result == 0);
|
z = (result == 0);
|
s = (result & 0x80000000);
|
s = (result & 0x80000000);
|
|
|
/* Store the result and condition codes. */
|
/* Store the result and condition codes. */
|
State.regs[OP[1]] = result;
|
State.regs[OP[1]] = result;
|
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
|
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
|
PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
|
PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
|
}
|
}
|
|
|
trace_output (OP_REG_REG);
|
trace_output (OP_REG_REG);
|
|
|
PC += 2;
|
PC += 2;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
|
|
rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
|
rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"divh r, r, r"
|
"divh r, r, r"
|
{
|
{
|
COMPAT_2 (OP_28007E0 ());
|
COMPAT_2 (OP_28007E0 ());
|
}
|
}
|
|
|
|
|
// DIVHU
|
// DIVHU
|
rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
|
rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"divhu r, r, r"
|
"divhu r, r, r"
|
{
|
{
|
COMPAT_2 (OP_28207E0 ());
|
COMPAT_2 (OP_28207E0 ());
|
}
|
}
|
|
|
|
|
// DIVU
|
// DIVU
|
rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
|
rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"divu r, r, r"
|
"divu r, r, r"
|
{
|
{
|
COMPAT_2 (OP_2C207E0 ());
|
COMPAT_2 (OP_2C207E0 ());
|
}
|
}
|
|
|
|
|
// EI
|
// EI
|
1000011111100000 + 0000000101100000:X:::ei
|
1000011111100000 + 0000000101100000:X:::ei
|
"ei"
|
"ei"
|
{
|
{
|
COMPAT_2 (OP_16087E0 ());
|
COMPAT_2 (OP_16087E0 ());
|
}
|
}
|
|
|
|
|
|
|
// HALT
|
// HALT
|
0000011111100000 + 0000000100100000:X:::halt
|
0000011111100000 + 0000000100100000:X:::halt
|
"halt"
|
"halt"
|
{
|
{
|
COMPAT_2 (OP_12007E0 ());
|
COMPAT_2 (OP_12007E0 ());
|
}
|
}
|
|
|
|
|
|
|
// HSW
|
// HSW
|
rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
|
rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"hsw r, r"
|
"hsw r, r"
|
{
|
{
|
unsigned32 value;
|
unsigned32 value;
|
TRACE_ALU_INPUT1 (GR[reg2]);
|
TRACE_ALU_INPUT1 (GR[reg2]);
|
|
|
value = GR[reg2];
|
value = GR[reg2];
|
value >>= 16;
|
value >>= 16;
|
value |= (GR[reg2] << 16);
|
value |= (GR[reg2] << 16);
|
|
|
GR[reg3] = value;
|
GR[reg3] = value;
|
|
|
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
|
if (value == 0) PSW |= PSW_Z;
|
if (value == 0) PSW |= PSW_Z;
|
if (value & 0x80000000) PSW |= PSW_S;
|
if (value & 0x80000000) PSW |= PSW_S;
|
if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
|
if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
|
|
|
TRACE_ALU_RESULT (GR[reg3]);
|
TRACE_ALU_RESULT (GR[reg3]);
|
}
|
}
|
|
|
|
|
|
|
// JARL
|
// JARL
|
rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
|
rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
|
"jarl , r"
|
"jarl , r"
|
{
|
{
|
GR[reg2] = nia;
|
GR[reg2] = nia;
|
nia = cia + disp22;
|
nia = cia + disp22;
|
TRACE_BRANCH1 (GR[reg2]);
|
TRACE_BRANCH1 (GR[reg2]);
|
}
|
}
|
|
|
|
|
|
|
// JMP
|
// JMP
|
00000000011,RRRRR:I:::jmp
|
00000000011,RRRRR:I:::jmp
|
"jmp [r]"
|
"jmp [r]"
|
{
|
{
|
nia = GR[reg1] & ~1;
|
nia = GR[reg1] & ~1;
|
TRACE_BRANCH0 ();
|
TRACE_BRANCH0 ();
|
}
|
}
|
|
|
|
|
|
|
// JR
|
// JR
|
0000011110,dddddd + ddddddddddddddd,0:V:::jr
|
0000011110,dddddd + ddddddddddddddd,0:V:::jr
|
"jr "
|
"jr "
|
{
|
{
|
nia = cia + disp22;
|
nia = cia + disp22;
|
TRACE_BRANCH0 ();
|
TRACE_BRANCH0 ();
|
}
|
}
|
|
|
|
|
|
|
// LD
|
// LD
|
rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
|
rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
|
"ld.b [r], r"
|
"ld.b [r], r"
|
{
|
{
|
COMPAT_2 (OP_700 ());
|
COMPAT_2 (OP_700 ());
|
}
|
}
|
|
|
rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
|
rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
|
"ld.h [r], r"
|
"ld.h [r], r"
|
{
|
{
|
COMPAT_2 (OP_720 ());
|
COMPAT_2 (OP_720 ());
|
}
|
}
|
|
|
rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
|
rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
|
"ld.w [r], r"
|
"ld.w [r], r"
|
{
|
{
|
COMPAT_2 (OP_10720 ());
|
COMPAT_2 (OP_10720 ());
|
}
|
}
|
|
|
rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
|
rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"ld.bu [r], r"
|
"ld.bu [r], r"
|
{
|
{
|
COMPAT_2 (OP_10780 ());
|
COMPAT_2 (OP_10780 ());
|
}
|
}
|
|
|
rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
|
rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"ld.hu [r], r"
|
"ld.hu [r], r"
|
{
|
{
|
COMPAT_2 (OP_107E0 ());
|
COMPAT_2 (OP_107E0 ());
|
}
|
}
|
|
|
|
|
// LDSR
|
// LDSR
|
regID,111111,RRRRR + 0000000000100000:IX:::ldsr
|
regID,111111,RRRRR + 0000000000100000:IX:::ldsr
|
"ldsr r, s"
|
"ldsr r, s"
|
{
|
{
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
|
|
if (&PSW == &SR[regID])
|
if (&PSW == &SR[regID])
|
PSW = (GR[reg1] & (CPU)->psw_mask);
|
PSW = (GR[reg1] & (CPU)->psw_mask);
|
else
|
else
|
SR[regID] = GR[reg1];
|
SR[regID] = GR[reg1];
|
|
|
TRACE_ALU_RESULT (SR[regID]);
|
TRACE_ALU_RESULT (SR[regID]);
|
}
|
}
|
|
|
|
|
|
|
// MOV
|
// MOV
|
rrrrr!0,000000,RRRRR:I:::mov
|
rrrrr!0,000000,RRRRR:I:::mov
|
"mov r, r"
|
"mov r, r"
|
{
|
{
|
TRACE_ALU_INPUT0 ();
|
TRACE_ALU_INPUT0 ();
|
GR[reg2] = GR[reg1];
|
GR[reg2] = GR[reg1];
|
TRACE_ALU_RESULT (GR[reg2]);
|
TRACE_ALU_RESULT (GR[reg2]);
|
}
|
}
|
|
|
|
|
rrrrr!0,010000,iiiii:II:::mov
|
rrrrr!0,010000,iiiii:II:::mov
|
"mov , r"
|
"mov , r"
|
{
|
{
|
COMPAT_1 (OP_200 ());
|
COMPAT_1 (OP_200 ());
|
}
|
}
|
|
|
00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
|
00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"mov , r"
|
"mov , r"
|
{
|
{
|
SAVE_2;
|
SAVE_2;
|
trace_input ("mov", OP_IMM_REG, 4);
|
trace_input ("mov", OP_IMM_REG, 4);
|
State.regs[ OP[0] ] = load_mem (PC + 2, 4);
|
State.regs[ OP[0] ] = load_mem (PC + 2, 4);
|
trace_output (OP_IMM_REG);
|
trace_output (OP_IMM_REG);
|
}
|
}
|
|
|
|
|
|
|
// MOVEA
|
// MOVEA
|
rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
|
rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
|
"movea , r, r"
|
"movea , r, r"
|
{
|
{
|
TRACE_ALU_INPUT2 (GR[reg1], simm16);
|
TRACE_ALU_INPUT2 (GR[reg1], simm16);
|
GR[reg2] = GR[reg1] + simm16;
|
GR[reg2] = GR[reg1] + simm16;
|
TRACE_ALU_RESULT (GR[reg2]);
|
TRACE_ALU_RESULT (GR[reg2]);
|
}
|
}
|
|
|
|
|
|
|
// MOVHI
|
// MOVHI
|
rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
|
rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
|
"movhi , r, r"
|
"movhi , r, r"
|
{
|
{
|
COMPAT_2 (OP_640 ());
|
COMPAT_2 (OP_640 ());
|
}
|
}
|
|
|
|
|
|
|
// MUL
|
// MUL
|
rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
|
rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"mul r, r, r"
|
"mul r, r, r"
|
{
|
{
|
COMPAT_2 (OP_22007E0 ());
|
COMPAT_2 (OP_22007E0 ());
|
}
|
}
|
|
|
rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
|
rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"mul , r, r"
|
"mul , r, r"
|
{
|
{
|
COMPAT_2 (OP_24007E0 ());
|
COMPAT_2 (OP_24007E0 ());
|
}
|
}
|
|
|
|
|
// MULH
|
// MULH
|
rrrrr!0,000111,RRRRR:I:::mulh
|
rrrrr!0,000111,RRRRR:I:::mulh
|
"mulh r, r"
|
"mulh r, r"
|
{
|
{
|
COMPAT_1 (OP_E0 ());
|
COMPAT_1 (OP_E0 ());
|
}
|
}
|
|
|
rrrrr!0,010111,iiiii:II:::mulh
|
rrrrr!0,010111,iiiii:II:::mulh
|
"mulh , r"
|
"mulh , r"
|
{
|
{
|
COMPAT_1 (OP_2E0 ());
|
COMPAT_1 (OP_2E0 ());
|
}
|
}
|
|
|
|
|
|
|
// MULHI
|
// MULHI
|
rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
|
rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
|
"mulhi , r, r"
|
"mulhi , r, r"
|
{
|
{
|
COMPAT_2 (OP_6E0 ());
|
COMPAT_2 (OP_6E0 ());
|
}
|
}
|
|
|
|
|
|
|
// MULU
|
// MULU
|
rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
|
rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"mulu r, r, r"
|
"mulu r, r, r"
|
{
|
{
|
COMPAT_2 (OP_22207E0 ());
|
COMPAT_2 (OP_22207E0 ());
|
}
|
}
|
|
|
rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
|
rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"mulu , r, r"
|
"mulu , r, r"
|
{
|
{
|
COMPAT_2 (OP_24207E0 ());
|
COMPAT_2 (OP_24207E0 ());
|
}
|
}
|
|
|
|
|
|
|
// NOP
|
// NOP
|
0000000000000000:I:::nop
|
0000000000000000:I:::nop
|
"nop"
|
"nop"
|
{
|
{
|
/* do nothing, trace nothing */
|
/* do nothing, trace nothing */
|
}
|
}
|
|
|
|
|
|
|
// NOT
|
// NOT
|
rrrrr,000001,RRRRR:I:::not
|
rrrrr,000001,RRRRR:I:::not
|
"not r, r"
|
"not r, r"
|
{
|
{
|
COMPAT_1 (OP_20 ());
|
COMPAT_1 (OP_20 ());
|
}
|
}
|
|
|
|
|
|
|
// NOT1
|
// NOT1
|
01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
|
01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
|
"not1 , [r]"
|
"not1 , [r]"
|
{
|
{
|
COMPAT_2 (OP_47C0 ());
|
COMPAT_2 (OP_47C0 ());
|
}
|
}
|
|
|
rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
|
rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"not1 r, r"
|
"not1 r, r"
|
{
|
{
|
COMPAT_2 (OP_E207E0 ());
|
COMPAT_2 (OP_E207E0 ());
|
}
|
}
|
|
|
|
|
|
|
// OR
|
// OR
|
rrrrr,001000,RRRRR:I:::or
|
rrrrr,001000,RRRRR:I:::or
|
"or r, r"
|
"or r, r"
|
{
|
{
|
COMPAT_1 (OP_100 ());
|
COMPAT_1 (OP_100 ());
|
}
|
}
|
|
|
|
|
|
|
// ORI
|
// ORI
|
rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
|
rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
|
"ori , r, r"
|
"ori , r, r"
|
{
|
{
|
COMPAT_2 (OP_680 ());
|
COMPAT_2 (OP_680 ());
|
}
|
}
|
|
|
|
|
|
|
// PREPARE
|
// PREPARE
|
0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
|
0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"prepare , "
|
"prepare , "
|
{
|
{
|
int i;
|
int i;
|
SAVE_2;
|
SAVE_2;
|
|
|
trace_input ("prepare", OP_PUSHPOP1, 0);
|
trace_input ("prepare", OP_PUSHPOP1, 0);
|
|
|
/* Store the registers with lower number registers being placed at
|
/* Store the registers with lower number registers being placed at
|
higher addresses. */
|
higher addresses. */
|
for (i = 0; i < 12; i++)
|
for (i = 0; i < 12; i++)
|
if ((OP[3] & (1 << type1_regs[ i ])))
|
if ((OP[3] & (1 << type1_regs[ i ])))
|
{
|
{
|
SP -= 4;
|
SP -= 4;
|
store_mem (SP, 4, State.regs[ 20 + i ]);
|
store_mem (SP, 4, State.regs[ 20 + i ]);
|
}
|
}
|
|
|
SP -= (OP[3] & 0x3e) << 1;
|
SP -= (OP[3] & 0x3e) << 1;
|
|
|
trace_output (OP_PUSHPOP1);
|
trace_output (OP_PUSHPOP1);
|
}
|
}
|
|
|
|
|
0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
|
0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"prepare , , sp"
|
"prepare , , sp"
|
{
|
{
|
COMPAT_2 (OP_30780 ());
|
COMPAT_2 (OP_30780 ());
|
}
|
}
|
|
|
0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
|
0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"prepare , , "
|
"prepare , , "
|
{
|
{
|
COMPAT_2 (OP_B0780 ());
|
COMPAT_2 (OP_B0780 ());
|
}
|
}
|
|
|
0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
|
0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"prepare , , "
|
"prepare , , "
|
{
|
{
|
COMPAT_2 (OP_130780 ());
|
COMPAT_2 (OP_130780 ());
|
}
|
}
|
|
|
0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
|
0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"prepare , , "
|
"prepare , , "
|
{
|
{
|
COMPAT_2 (OP_1B0780 ());
|
COMPAT_2 (OP_1B0780 ());
|
}
|
}
|
|
|
|
|
|
|
// RETI
|
// RETI
|
0000011111100000 + 0000000101000000:X:::reti
|
0000011111100000 + 0000000101000000:X:::reti
|
"reti"
|
"reti"
|
{
|
{
|
if ((PSW & PSW_EP))
|
if ((PSW & PSW_EP))
|
{
|
{
|
nia = (EIPC & ~1);
|
nia = (EIPC & ~1);
|
PSW = EIPSW;
|
PSW = EIPSW;
|
}
|
}
|
else if ((PSW & PSW_NP))
|
else if ((PSW & PSW_NP))
|
{
|
{
|
nia = (FEPC & ~1);
|
nia = (FEPC & ~1);
|
PSW = FEPSW;
|
PSW = FEPSW;
|
}
|
}
|
else
|
else
|
{
|
{
|
nia = (EIPC & ~1);
|
nia = (EIPC & ~1);
|
PSW = EIPSW;
|
PSW = EIPSW;
|
}
|
}
|
TRACE_BRANCH1 (PSW);
|
TRACE_BRANCH1 (PSW);
|
}
|
}
|
|
|
|
|
|
|
// SAR
|
// SAR
|
rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
|
rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
|
"sar r, r"
|
"sar r, r"
|
{
|
{
|
COMPAT_2 (OP_A007E0 ());
|
COMPAT_2 (OP_A007E0 ());
|
}
|
}
|
|
|
rrrrr,010101,iiiii:II:::sar
|
rrrrr,010101,iiiii:II:::sar
|
"sar , r"
|
"sar , r"
|
{
|
{
|
COMPAT_1 (OP_2A0 ());
|
COMPAT_1 (OP_2A0 ());
|
}
|
}
|
|
|
|
|
|
|
// SASF
|
// SASF
|
rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
|
rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"sasf %s, r"
|
"sasf %s, r"
|
{
|
{
|
COMPAT_2 (OP_20007E0 ());
|
COMPAT_2 (OP_20007E0 ());
|
}
|
}
|
|
|
|
|
|
|
|
|
// SATADD
|
// SATADD
|
rrrrr!0,000110,RRRRR:I:::satadd
|
rrrrr!0,000110,RRRRR:I:::satadd
|
"satadd r, r"
|
"satadd r, r"
|
{
|
{
|
COMPAT_1 (OP_C0 ());
|
COMPAT_1 (OP_C0 ());
|
}
|
}
|
|
|
rrrrr!0,010001,iiiii:II:::satadd
|
rrrrr!0,010001,iiiii:II:::satadd
|
"satadd , r"
|
"satadd , r"
|
{
|
{
|
COMPAT_1 (OP_220 ());
|
COMPAT_1 (OP_220 ());
|
}
|
}
|
|
|
|
|
|
|
// SATSUB
|
// SATSUB
|
rrrrr!0,000101,RRRRR:I:::satsub
|
rrrrr!0,000101,RRRRR:I:::satsub
|
"satsub r, r"
|
"satsub r, r"
|
{
|
{
|
COMPAT_1 (OP_A0 ());
|
COMPAT_1 (OP_A0 ());
|
}
|
}
|
|
|
|
|
|
|
// SATSUBI
|
// SATSUBI
|
rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
|
rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
|
"satsubi , r, r"
|
"satsubi , r, r"
|
{
|
{
|
COMPAT_2 (OP_660 ());
|
COMPAT_2 (OP_660 ());
|
}
|
}
|
|
|
|
|
|
|
// SATSUBR
|
// SATSUBR
|
rrrrr!0,000100,RRRRR:I:::satsubr
|
rrrrr!0,000100,RRRRR:I:::satsubr
|
"satsubr r, r"
|
"satsubr r, r"
|
{
|
{
|
COMPAT_1 (OP_80 ());
|
COMPAT_1 (OP_80 ());
|
}
|
}
|
|
|
|
|
|
|
// SETF
|
// SETF
|
rrrrr,1111110,cccc + 0000000000000000:IX:::setf
|
rrrrr,1111110,cccc + 0000000000000000:IX:::setf
|
"setf %s, r"
|
"setf %s, r"
|
{
|
{
|
COMPAT_2 (OP_7E0 ());
|
COMPAT_2 (OP_7E0 ());
|
}
|
}
|
|
|
|
|
|
|
// SET1
|
// SET1
|
00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
|
00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
|
"set1 , [r]"
|
"set1 , [r]"
|
{
|
{
|
COMPAT_2 (OP_7C0 ());
|
COMPAT_2 (OP_7C0 ());
|
}
|
}
|
|
|
rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
|
rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"set1 r, [r]"
|
"set1 r, [r]"
|
{
|
{
|
COMPAT_2 (OP_E007E0 ());
|
COMPAT_2 (OP_E007E0 ());
|
}
|
}
|
|
|
|
|
|
|
// SHL
|
// SHL
|
rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
|
rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
|
"shl r, r"
|
"shl r, r"
|
{
|
{
|
COMPAT_2 (OP_C007E0 ());
|
COMPAT_2 (OP_C007E0 ());
|
}
|
}
|
|
|
rrrrr,010110,iiiii:II:::shl
|
rrrrr,010110,iiiii:II:::shl
|
"shl , r"
|
"shl , r"
|
{
|
{
|
COMPAT_1 (OP_2C0 ());
|
COMPAT_1 (OP_2C0 ());
|
}
|
}
|
|
|
|
|
|
|
// SHR
|
// SHR
|
rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
|
rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
|
"shr r, r"
|
"shr r, r"
|
{
|
{
|
COMPAT_2 (OP_8007E0 ());
|
COMPAT_2 (OP_8007E0 ());
|
}
|
}
|
|
|
rrrrr,010100,iiiii:II:::shr
|
rrrrr,010100,iiiii:II:::shr
|
"shr , r"
|
"shr , r"
|
{
|
{
|
COMPAT_1 (OP_280 ());
|
COMPAT_1 (OP_280 ());
|
}
|
}
|
|
|
|
|
|
|
// SLD
|
// SLD
|
rrrrr,0110,ddddddd:IV:::sld.b
|
rrrrr,0110,ddddddd:IV:::sld.b
|
"sld.bu [ep], r":(PSW & PSW_US)
|
"sld.bu [ep], r":(PSW & PSW_US)
|
"sld.b [ep], r"
|
"sld.b [ep], r"
|
{
|
{
|
unsigned32 addr = EP + disp7;
|
unsigned32 addr = EP + disp7;
|
unsigned32 result = load_mem (addr, 1);
|
unsigned32 result = load_mem (addr, 1);
|
if (PSW & PSW_US)
|
if (PSW & PSW_US)
|
{
|
{
|
GR[reg2] = result;
|
GR[reg2] = result;
|
TRACE_LD_NAME ("sld.bu", addr, result);
|
TRACE_LD_NAME ("sld.bu", addr, result);
|
}
|
}
|
else
|
else
|
{
|
{
|
result = EXTEND8 (result);
|
result = EXTEND8 (result);
|
GR[reg2] = result;
|
GR[reg2] = result;
|
TRACE_LD (addr, result);
|
TRACE_LD (addr, result);
|
}
|
}
|
}
|
}
|
|
|
rrrrr,1000,ddddddd:IV:::sld.h
|
rrrrr,1000,ddddddd:IV:::sld.h
|
"sld.hu [ep], r":(PSW & PSW_US)
|
"sld.hu [ep], r":(PSW & PSW_US)
|
"sld.h [ep], r"
|
"sld.h [ep], r"
|
{
|
{
|
unsigned32 addr = EP + disp8;
|
unsigned32 addr = EP + disp8;
|
unsigned32 result = load_mem (addr, 2);
|
unsigned32 result = load_mem (addr, 2);
|
if (PSW & PSW_US)
|
if (PSW & PSW_US)
|
{
|
{
|
GR[reg2] = result;
|
GR[reg2] = result;
|
TRACE_LD_NAME ("sld.hu", addr, result);
|
TRACE_LD_NAME ("sld.hu", addr, result);
|
}
|
}
|
else
|
else
|
{
|
{
|
result = EXTEND16 (result);
|
result = EXTEND16 (result);
|
GR[reg2] = result;
|
GR[reg2] = result;
|
TRACE_LD (addr, result);
|
TRACE_LD (addr, result);
|
}
|
}
|
}
|
}
|
|
|
rrrrr,1010,dddddd,0:IV:::sld.w
|
rrrrr,1010,dddddd,0:IV:::sld.w
|
"sld.w [ep], r"
|
"sld.w [ep], r"
|
{
|
{
|
unsigned32 addr = EP + disp8;
|
unsigned32 addr = EP + disp8;
|
unsigned32 result = load_mem (addr, 4);
|
unsigned32 result = load_mem (addr, 4);
|
GR[reg2] = result;
|
GR[reg2] = result;
|
TRACE_LD (addr, result);
|
TRACE_LD (addr, result);
|
}
|
}
|
|
|
rrrrr!0,0000110,dddd:IV:::sld.bu
|
rrrrr!0,0000110,dddd:IV:::sld.bu
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"sld.b [ep], r":(PSW & PSW_US)
|
"sld.b [ep], r":(PSW & PSW_US)
|
"sld.bu [ep], r"
|
"sld.bu [ep], r"
|
{
|
{
|
unsigned32 addr = EP + disp4;
|
unsigned32 addr = EP + disp4;
|
unsigned32 result = load_mem (addr, 1);
|
unsigned32 result = load_mem (addr, 1);
|
if (PSW & PSW_US)
|
if (PSW & PSW_US)
|
{
|
{
|
result = EXTEND8 (result);
|
result = EXTEND8 (result);
|
GR[reg2] = result;
|
GR[reg2] = result;
|
TRACE_LD_NAME ("sld.b", addr, result);
|
TRACE_LD_NAME ("sld.b", addr, result);
|
}
|
}
|
else
|
else
|
{
|
{
|
GR[reg2] = result;
|
GR[reg2] = result;
|
TRACE_LD (addr, result);
|
TRACE_LD (addr, result);
|
}
|
}
|
}
|
}
|
|
|
rrrrr!0,0000111,dddd:IV:::sld.hu
|
rrrrr!0,0000111,dddd:IV:::sld.hu
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"sld.h [ep], r":(PSW & PSW_US)
|
"sld.h [ep], r":(PSW & PSW_US)
|
"sld.hu [ep], r"
|
"sld.hu [ep], r"
|
{
|
{
|
unsigned32 addr = EP + disp5;
|
unsigned32 addr = EP + disp5;
|
unsigned32 result = load_mem (addr, 2);
|
unsigned32 result = load_mem (addr, 2);
|
if (PSW & PSW_US)
|
if (PSW & PSW_US)
|
{
|
{
|
result = EXTEND16 (result);
|
result = EXTEND16 (result);
|
GR[reg2] = result;
|
GR[reg2] = result;
|
TRACE_LD_NAME ("sld.h", addr, result);
|
TRACE_LD_NAME ("sld.h", addr, result);
|
}
|
}
|
else
|
else
|
{
|
{
|
GR[reg2] = result;
|
GR[reg2] = result;
|
TRACE_LD (addr, result);
|
TRACE_LD (addr, result);
|
}
|
}
|
}
|
}
|
|
|
// SST
|
// SST
|
rrrrr,0111,ddddddd:IV:::sst.b
|
rrrrr,0111,ddddddd:IV:::sst.b
|
"sst.b r, [ep]"
|
"sst.b r, [ep]"
|
{
|
{
|
COMPAT_1 (OP_380 ());
|
COMPAT_1 (OP_380 ());
|
}
|
}
|
|
|
rrrrr,1001,ddddddd:IV:::sst.h
|
rrrrr,1001,ddddddd:IV:::sst.h
|
"sst.h r, [ep]"
|
"sst.h r, [ep]"
|
{
|
{
|
COMPAT_1 (OP_480 ());
|
COMPAT_1 (OP_480 ());
|
}
|
}
|
|
|
rrrrr,1010,dddddd,1:IV:::sst.w
|
rrrrr,1010,dddddd,1:IV:::sst.w
|
"sst.w r, [ep]"
|
"sst.w r, [ep]"
|
{
|
{
|
COMPAT_1 (OP_501 ());
|
COMPAT_1 (OP_501 ());
|
}
|
}
|
|
|
// ST
|
// ST
|
rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
|
rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
|
"st.b r, [r]"
|
"st.b r, [r]"
|
{
|
{
|
COMPAT_2 (OP_740 ());
|
COMPAT_2 (OP_740 ());
|
}
|
}
|
|
|
rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
|
rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
|
"st.h r, [r]"
|
"st.h r, [r]"
|
{
|
{
|
COMPAT_2 (OP_760 ());
|
COMPAT_2 (OP_760 ());
|
}
|
}
|
|
|
rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
|
rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
|
"st.w r, [r]"
|
"st.w r, [r]"
|
{
|
{
|
COMPAT_2 (OP_10760 ());
|
COMPAT_2 (OP_10760 ());
|
}
|
}
|
|
|
// STSR
|
// STSR
|
rrrrr,111111,regID + 0000000001000000:IX:::stsr
|
rrrrr,111111,regID + 0000000001000000:IX:::stsr
|
"stsr s, r"
|
"stsr s, r"
|
{
|
{
|
TRACE_ALU_INPUT1 (SR[regID]);
|
TRACE_ALU_INPUT1 (SR[regID]);
|
GR[reg2] = SR[regID];
|
GR[reg2] = SR[regID];
|
TRACE_ALU_RESULT (GR[reg2]);
|
TRACE_ALU_RESULT (GR[reg2]);
|
}
|
}
|
|
|
// SUB
|
// SUB
|
rrrrr,001101,RRRRR:I:::sub
|
rrrrr,001101,RRRRR:I:::sub
|
"sub r, r"
|
"sub r, r"
|
{
|
{
|
COMPAT_1 (OP_1A0 ());
|
COMPAT_1 (OP_1A0 ());
|
}
|
}
|
|
|
// SUBR
|
// SUBR
|
rrrrr,001100,RRRRR:I:::subr
|
rrrrr,001100,RRRRR:I:::subr
|
"subr r, r"
|
"subr r, r"
|
{
|
{
|
COMPAT_1 (OP_180 ());
|
COMPAT_1 (OP_180 ());
|
}
|
}
|
|
|
// SWITCH
|
// SWITCH
|
00000000010,RRRRR:I:::switch
|
00000000010,RRRRR:I:::switch
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"switch r"
|
"switch r"
|
{
|
{
|
unsigned long adr;
|
unsigned long adr;
|
SAVE_1;
|
SAVE_1;
|
trace_input ("switch", OP_REG, 0);
|
trace_input ("switch", OP_REG, 0);
|
adr = (cia + 2) + (State.regs[ reg1 ] << 1);
|
adr = (cia + 2) + (State.regs[ reg1 ] << 1);
|
nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
|
nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
|
trace_output (OP_REG);
|
trace_output (OP_REG);
|
}
|
}
|
|
|
// SXB
|
// SXB
|
00000000101,RRRRR:I:::sxb
|
00000000101,RRRRR:I:::sxb
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"sxb r"
|
"sxb r"
|
{
|
{
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
GR[reg1] = EXTEND8 (GR[reg1]);
|
GR[reg1] = EXTEND8 (GR[reg1]);
|
TRACE_ALU_RESULT (GR[reg1]);
|
TRACE_ALU_RESULT (GR[reg1]);
|
}
|
}
|
|
|
// SXH
|
// SXH
|
00000000111,RRRRR:I:::sxh
|
00000000111,RRRRR:I:::sxh
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"sxh r"
|
"sxh r"
|
{
|
{
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
GR[reg1] = EXTEND16 (GR[reg1]);
|
GR[reg1] = EXTEND16 (GR[reg1]);
|
TRACE_ALU_RESULT (GR[reg1]);
|
TRACE_ALU_RESULT (GR[reg1]);
|
}
|
}
|
|
|
// TRAP
|
// TRAP
|
00000111111,iiiii + 0000000100000000:X:::trap
|
00000111111,iiiii + 0000000100000000:X:::trap
|
"trap "
|
"trap "
|
{
|
{
|
COMPAT_2 (OP_10007E0 ());
|
COMPAT_2 (OP_10007E0 ());
|
}
|
}
|
|
|
// TST
|
// TST
|
rrrrr,001011,RRRRR:I:::tst
|
rrrrr,001011,RRRRR:I:::tst
|
"tst r, r"
|
"tst r, r"
|
{
|
{
|
COMPAT_1 (OP_160 ());
|
COMPAT_1 (OP_160 ());
|
}
|
}
|
|
|
// TST1
|
// TST1
|
11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
|
11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
|
"tst1 , [r]"
|
"tst1 , [r]"
|
{
|
{
|
COMPAT_2 (OP_C7C0 ());
|
COMPAT_2 (OP_C7C0 ());
|
}
|
}
|
|
|
rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
|
rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"tst1 r, [r]"
|
"tst1 r, [r]"
|
{
|
{
|
COMPAT_2 (OP_E607E0 ());
|
COMPAT_2 (OP_E607E0 ());
|
}
|
}
|
|
|
// XOR
|
// XOR
|
rrrrr,001001,RRRRR:I:::xor
|
rrrrr,001001,RRRRR:I:::xor
|
"xor r, r"
|
"xor r, r"
|
{
|
{
|
COMPAT_1 (OP_120 ());
|
COMPAT_1 (OP_120 ());
|
}
|
}
|
|
|
// XORI
|
// XORI
|
rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
|
rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
|
"xori , r, r"
|
"xori , r, r"
|
{
|
{
|
COMPAT_2 (OP_6A0 ());
|
COMPAT_2 (OP_6A0 ());
|
}
|
}
|
|
|
// ZXB
|
// ZXB
|
00000000100,RRRRR:I:::zxb
|
00000000100,RRRRR:I:::zxb
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"zxb r"
|
"zxb r"
|
{
|
{
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
GR[reg1] = GR[reg1] & 0xff;
|
GR[reg1] = GR[reg1] & 0xff;
|
TRACE_ALU_RESULT (GR[reg1]);
|
TRACE_ALU_RESULT (GR[reg1]);
|
}
|
}
|
|
|
// ZXH
|
// ZXH
|
00000000110,RRRRR:I:::zxh
|
00000000110,RRRRR:I:::zxh
|
*v850e
|
*v850e
|
*v850e1
|
*v850e1
|
"zxh r"
|
"zxh r"
|
{
|
{
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
GR[reg1] = GR[reg1] & 0xffff;
|
GR[reg1] = GR[reg1] & 0xffff;
|
TRACE_ALU_RESULT (GR[reg1]);
|
TRACE_ALU_RESULT (GR[reg1]);
|
}
|
}
|
|
|
// Right field must be zero so that it doesn't clash with DIVH
|
// Right field must be zero so that it doesn't clash with DIVH
|
// Left field must be non-zero so that it doesn't clash with SWITCH
|
// Left field must be non-zero so that it doesn't clash with SWITCH
|
11111,000010,00000:I:::break
|
11111,000010,00000:I:::break
|
*v850
|
*v850
|
*v850e
|
*v850e
|
{
|
{
|
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
|
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
|
}
|
}
|
|
|
11111,000010,00000:I:::dbtrap
|
11111,000010,00000:I:::dbtrap
|
*v850e1
|
*v850e1
|
"dbtrap"
|
"dbtrap"
|
{
|
{
|
DBPC = cia + 2;
|
DBPC = cia + 2;
|
DBPSW = PSW;
|
DBPSW = PSW;
|
PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
|
PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
|
PC = 0x00000060;
|
PC = 0x00000060;
|
nia = 0x00000060;
|
nia = 0x00000060;
|
TRACE_BRANCH0 ();
|
TRACE_BRANCH0 ();
|
}
|
}
|
|
|
// New breakpoint: 0x7E0 0x7E0
|
// New breakpoint: 0x7E0 0x7E0
|
00000,111111,00000 + 00000,11111,100000:X:::ilgop
|
00000,111111,00000 + 00000,11111,100000:X:::ilgop
|
{
|
{
|
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
|
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
|
}
|
}
|
|
|
// Return from debug trap: 0x146007e0
|
// Return from debug trap: 0x146007e0
|
0000011111100000 + 0000000101000110:X:::dbret
|
0000011111100000 + 0000000101000110:X:::dbret
|
*v850e1
|
*v850e1
|
"dbret"
|
"dbret"
|
{
|
{
|
nia = DBPC;
|
nia = DBPC;
|
PSW = DBPSW;
|
PSW = DBPSW;
|
TRACE_BRANCH1 (PSW);
|
TRACE_BRANCH1 (PSW);
|
}
|
}
|
|
|
