/* BFD back-end for verilog hex memory dump files.
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/* BFD back-end for verilog hex memory dump files.
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Copyright 2009, 2010
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Copyright 2009, 2010
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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Written by Anthony Green <green@moxielogic.com>
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Written by Anthony Green <green@moxielogic.com>
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This file is part of BFD, the Binary File Descriptor library.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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MA 02110-1301, USA. */
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/* SUBSECTION
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/* SUBSECTION
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Verilog hex memory file handling
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Verilog hex memory file handling
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DESCRIPTION
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DESCRIPTION
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Verilog hex memory files cannot hold anything but addresses
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Verilog hex memory files cannot hold anything but addresses
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and data, so that's all that we implement.
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and data, so that's all that we implement.
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The syntax of the text file is described in the IEEE standard
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The syntax of the text file is described in the IEEE standard
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for Verilog. Briefly, the file contains two types of tokens:
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for Verilog. Briefly, the file contains two types of tokens:
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data and optional addresses. The tokens are separated by
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data and optional addresses. The tokens are separated by
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whitespace and comments. Comments may be single line or
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whitespace and comments. Comments may be single line or
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multiline, using syntax similar to C++. Addresses are
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multiline, using syntax similar to C++. Addresses are
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specified by a leading "at" character (@) and are always
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specified by a leading "at" character (@) and are always
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hexadecimal strings. Data and addresses may contain
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hexadecimal strings. Data and addresses may contain
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underscore (_) characters.
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underscore (_) characters.
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If no address is specified, the data is assumed to start at
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If no address is specified, the data is assumed to start at
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address 0. Similarly, if data exists before the first
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address 0. Similarly, if data exists before the first
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specified address, then that data is assumed to start at
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specified address, then that data is assumed to start at
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address 0.
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address 0.
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EXAMPLE
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EXAMPLE
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@1000
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@1000
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01 ae 3f 45 12
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01 ae 3f 45 12
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DESCRIPTION
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DESCRIPTION
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@1000 specifies the starting address for the memory data.
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@1000 specifies the starting address for the memory data.
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The following characters describe the 5 bytes at 0x1000. */
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The following characters describe the 5 bytes at 0x1000. */
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#include "sysdep.h"
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#include "sysdep.h"
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#include "bfd.h"
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#include "bfd.h"
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#include "libbfd.h"
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#include "libbfd.h"
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#include "libiberty.h"
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#include "libiberty.h"
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#include "safe-ctype.h"
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#include "safe-ctype.h"
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/* Macros for converting between hex and binary. */
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/* Macros for converting between hex and binary. */
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static const char digs[] = "0123456789ABCDEF";
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static const char digs[] = "0123456789ABCDEF";
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#define NIBBLE(x) hex_value(x)
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#define NIBBLE(x) hex_value(x)
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#define HEX(buffer) ((NIBBLE ((buffer)[0])<<4) + NIBBLE ((buffer)[1]))
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#define HEX(buffer) ((NIBBLE ((buffer)[0])<<4) + NIBBLE ((buffer)[1]))
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#define TOHEX(d, x) \
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#define TOHEX(d, x) \
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d[1] = digs[(x) & 0xf]; \
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d[1] = digs[(x) & 0xf]; \
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d[0] = digs[((x) >> 4) & 0xf];
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d[0] = digs[((x) >> 4) & 0xf];
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/* When writing a verilog memory dump file, we write them in the order
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/* When writing a verilog memory dump file, we write them in the order
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in which they appear in memory. This structure is used to hold them
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in which they appear in memory. This structure is used to hold them
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in memory. */
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in memory. */
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struct verilog_data_list_struct
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struct verilog_data_list_struct
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{
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{
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struct verilog_data_list_struct *next;
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struct verilog_data_list_struct *next;
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bfd_byte * data;
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bfd_byte * data;
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bfd_vma where;
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bfd_vma where;
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bfd_size_type size;
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bfd_size_type size;
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};
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};
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typedef struct verilog_data_list_struct verilog_data_list_type;
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typedef struct verilog_data_list_struct verilog_data_list_type;
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/* The verilog tdata information. */
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/* The verilog tdata information. */
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typedef struct verilog_data_struct
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typedef struct verilog_data_struct
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{
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{
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verilog_data_list_type *head;
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verilog_data_list_type *head;
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verilog_data_list_type *tail;
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verilog_data_list_type *tail;
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}
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}
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tdata_type;
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tdata_type;
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static bfd_boolean
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static bfd_boolean
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verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach)
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verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach)
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{
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{
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if (arch != bfd_arch_unknown)
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if (arch != bfd_arch_unknown)
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return bfd_default_set_arch_mach (abfd, arch, mach);
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return bfd_default_set_arch_mach (abfd, arch, mach);
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abfd->arch_info = & bfd_default_arch_struct;
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abfd->arch_info = & bfd_default_arch_struct;
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return TRUE;
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return TRUE;
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}
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}
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/* We have to save up all the outpu for a splurge before output. */
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/* We have to save up all the outpu for a splurge before output. */
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static bfd_boolean
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static bfd_boolean
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verilog_set_section_contents (bfd *abfd,
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verilog_set_section_contents (bfd *abfd,
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sec_ptr section,
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sec_ptr section,
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const void * location,
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const void * location,
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file_ptr offset,
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file_ptr offset,
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bfd_size_type bytes_to_do)
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bfd_size_type bytes_to_do)
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{
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{
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tdata_type *tdata = abfd->tdata.verilog_data;
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tdata_type *tdata = abfd->tdata.verilog_data;
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verilog_data_list_type *entry;
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verilog_data_list_type *entry;
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entry = (verilog_data_list_type *) bfd_alloc (abfd, sizeof (* entry));
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entry = (verilog_data_list_type *) bfd_alloc (abfd, sizeof (* entry));
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if (entry == NULL)
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if (entry == NULL)
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return FALSE;
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return FALSE;
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if (bytes_to_do
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if (bytes_to_do
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&& (section->flags & SEC_ALLOC)
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&& (section->flags & SEC_ALLOC)
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&& (section->flags & SEC_LOAD))
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&& (section->flags & SEC_LOAD))
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{
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{
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bfd_byte *data;
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bfd_byte *data;
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data = (bfd_byte *) bfd_alloc (abfd, bytes_to_do);
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data = (bfd_byte *) bfd_alloc (abfd, bytes_to_do);
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if (data == NULL)
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if (data == NULL)
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return FALSE;
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return FALSE;
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memcpy ((void *) data, location, (size_t) bytes_to_do);
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memcpy ((void *) data, location, (size_t) bytes_to_do);
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entry->data = data;
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entry->data = data;
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entry->where = section->lma + offset;
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entry->where = section->lma + offset;
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entry->size = bytes_to_do;
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entry->size = bytes_to_do;
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/* Sort the records by address. Optimize for the common case of
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/* Sort the records by address. Optimize for the common case of
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adding a record to the end of the list. */
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adding a record to the end of the list. */
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if (tdata->tail != NULL
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if (tdata->tail != NULL
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&& entry->where >= tdata->tail->where)
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&& entry->where >= tdata->tail->where)
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{
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{
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tdata->tail->next = entry;
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tdata->tail->next = entry;
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entry->next = NULL;
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entry->next = NULL;
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tdata->tail = entry;
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tdata->tail = entry;
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}
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}
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else
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else
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{
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{
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verilog_data_list_type **look;
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verilog_data_list_type **look;
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for (look = &tdata->head;
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for (look = &tdata->head;
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*look != NULL && (*look)->where < entry->where;
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*look != NULL && (*look)->where < entry->where;
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look = &(*look)->next)
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look = &(*look)->next)
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;
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;
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entry->next = *look;
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entry->next = *look;
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*look = entry;
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*look = entry;
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if (entry->next == NULL)
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if (entry->next == NULL)
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tdata->tail = entry;
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tdata->tail = entry;
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}
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}
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}
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}
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return TRUE;
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return TRUE;
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}
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}
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static bfd_boolean
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static bfd_boolean
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verilog_write_address (bfd *abfd, bfd_vma address)
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verilog_write_address (bfd *abfd, bfd_vma address)
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{
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{
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char buffer[12];
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char buffer[12];
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char *dst = buffer;
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char *dst = buffer;
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bfd_size_type wrlen;
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bfd_size_type wrlen;
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/* Write the address. */
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/* Write the address. */
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*dst++ = '@';
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*dst++ = '@';
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TOHEX (dst, (address >> 24));
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TOHEX (dst, (address >> 24));
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dst += 2;
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dst += 2;
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TOHEX (dst, (address >> 16));
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TOHEX (dst, (address >> 16));
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dst += 2;
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dst += 2;
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TOHEX (dst, (address >> 8));
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TOHEX (dst, (address >> 8));
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dst += 2;
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dst += 2;
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TOHEX (dst, (address));
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TOHEX (dst, (address));
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dst += 2;
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dst += 2;
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*dst++ = '\r';
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*dst++ = '\r';
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*dst++ = '\n';
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*dst++ = '\n';
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wrlen = dst - buffer;
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wrlen = dst - buffer;
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return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
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return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
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}
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}
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/* Write a record of type, of the supplied number of bytes. The
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/* Write a record of type, of the supplied number of bytes. The
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supplied bytes and length don't have a checksum. That's worked out
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supplied bytes and length don't have a checksum. That's worked out
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here. */
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here. */
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static bfd_boolean
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static bfd_boolean
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verilog_write_record (bfd *abfd,
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verilog_write_record (bfd *abfd,
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const bfd_byte *data,
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const bfd_byte *data,
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const bfd_byte *end)
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const bfd_byte *end)
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{
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{
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char buffer[48];
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char buffer[48];
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const bfd_byte *src = data;
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const bfd_byte *src = data;
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char *dst = buffer;
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char *dst = buffer;
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bfd_size_type wrlen;
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bfd_size_type wrlen;
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/* Write the data. */
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/* Write the data. */
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for (src = data; src < end; src++)
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for (src = data; src < end; src++)
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{
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{
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TOHEX (dst, *src);
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TOHEX (dst, *src);
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dst += 2;
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dst += 2;
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*dst++ = ' ';
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*dst++ = ' ';
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}
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}
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*dst++ = '\r';
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*dst++ = '\r';
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*dst++ = '\n';
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*dst++ = '\n';
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wrlen = dst - buffer;
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wrlen = dst - buffer;
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return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
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return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
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}
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}
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static bfd_boolean
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static bfd_boolean
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verilog_write_section (bfd *abfd,
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verilog_write_section (bfd *abfd,
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tdata_type *tdata ATTRIBUTE_UNUSED,
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tdata_type *tdata ATTRIBUTE_UNUSED,
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verilog_data_list_type *list)
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verilog_data_list_type *list)
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{
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{
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unsigned int octets_written = 0;
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unsigned int octets_written = 0;
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bfd_byte *location = list->data;
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bfd_byte *location = list->data;
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verilog_write_address (abfd, list->where);
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verilog_write_address (abfd, list->where);
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while (octets_written < list->size)
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while (octets_written < list->size)
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{
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{
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unsigned int octets_this_chunk = list->size - octets_written;
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unsigned int octets_this_chunk = list->size - octets_written;
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if (octets_this_chunk > 16)
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if (octets_this_chunk > 16)
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octets_this_chunk = 16;
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octets_this_chunk = 16;
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if (! verilog_write_record (abfd,
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if (! verilog_write_record (abfd,
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location,
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location,
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location + octets_this_chunk))
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location + octets_this_chunk))
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return FALSE;
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return FALSE;
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octets_written += octets_this_chunk;
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octets_written += octets_this_chunk;
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location += octets_this_chunk;
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location += octets_this_chunk;
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}
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}
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return TRUE;
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return TRUE;
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}
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}
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static bfd_boolean
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static bfd_boolean
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verilog_write_object_contents (bfd *abfd)
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verilog_write_object_contents (bfd *abfd)
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{
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{
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tdata_type *tdata = abfd->tdata.verilog_data;
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tdata_type *tdata = abfd->tdata.verilog_data;
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verilog_data_list_type *list;
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verilog_data_list_type *list;
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/* Now wander though all the sections provided and output them. */
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/* Now wander though all the sections provided and output them. */
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list = tdata->head;
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list = tdata->head;
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while (list != (verilog_data_list_type *) NULL)
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while (list != (verilog_data_list_type *) NULL)
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{
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{
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if (! verilog_write_section (abfd, tdata, list))
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if (! verilog_write_section (abfd, tdata, list))
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return FALSE;
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return FALSE;
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list = list->next;
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list = list->next;
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}
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}
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return TRUE;
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return TRUE;
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}
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}
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/* Initialize by filling in the hex conversion array. */
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/* Initialize by filling in the hex conversion array. */
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static void
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static void
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verilog_init (void)
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verilog_init (void)
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{
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{
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static bfd_boolean inited = FALSE;
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static bfd_boolean inited = FALSE;
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if (! inited)
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if (! inited)
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{
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{
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inited = TRUE;
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inited = TRUE;
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hex_init ();
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hex_init ();
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}
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}
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}
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}
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/* Set up the verilog tdata information. */
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/* Set up the verilog tdata information. */
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static bfd_boolean
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static bfd_boolean
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verilog_mkobject (bfd *abfd)
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verilog_mkobject (bfd *abfd)
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{
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{
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tdata_type *tdata;
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tdata_type *tdata;
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verilog_init ();
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verilog_init ();
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tdata = (tdata_type *) bfd_alloc (abfd, sizeof (tdata_type));
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tdata = (tdata_type *) bfd_alloc (abfd, sizeof (tdata_type));
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if (tdata == NULL)
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if (tdata == NULL)
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return FALSE;
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return FALSE;
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abfd->tdata.verilog_data = tdata;
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abfd->tdata.verilog_data = tdata;
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tdata->head = NULL;
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tdata->head = NULL;
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tdata->tail = NULL;
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tdata->tail = NULL;
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return TRUE;
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return TRUE;
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}
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}
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#define verilog_close_and_cleanup _bfd_generic_close_and_cleanup
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#define verilog_close_and_cleanup _bfd_generic_close_and_cleanup
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#define verilog_bfd_free_cached_info _bfd_generic_bfd_free_cached_info
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#define verilog_bfd_free_cached_info _bfd_generic_bfd_free_cached_info
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#define verilog_new_section_hook _bfd_generic_new_section_hook
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#define verilog_new_section_hook _bfd_generic_new_section_hook
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#define verilog_bfd_is_target_special_symbol ((bfd_boolean (*) (bfd *, asymbol *)) bfd_false)
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#define verilog_bfd_is_target_special_symbol ((bfd_boolean (*) (bfd *, asymbol *)) bfd_false)
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#define verilog_bfd_is_local_label_name bfd_generic_is_local_label_name
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#define verilog_bfd_is_local_label_name bfd_generic_is_local_label_name
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#define verilog_get_lineno _bfd_nosymbols_get_lineno
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#define verilog_get_lineno _bfd_nosymbols_get_lineno
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#define verilog_find_nearest_line _bfd_nosymbols_find_nearest_line
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#define verilog_find_nearest_line _bfd_nosymbols_find_nearest_line
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#define verilog_find_inliner_info _bfd_nosymbols_find_inliner_info
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#define verilog_find_inliner_info _bfd_nosymbols_find_inliner_info
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#define verilog_make_empty_symbol _bfd_generic_make_empty_symbol
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#define verilog_make_empty_symbol _bfd_generic_make_empty_symbol
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#define verilog_bfd_make_debug_symbol _bfd_nosymbols_bfd_make_debug_symbol
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#define verilog_bfd_make_debug_symbol _bfd_nosymbols_bfd_make_debug_symbol
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#define verilog_read_minisymbols _bfd_generic_read_minisymbols
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#define verilog_read_minisymbols _bfd_generic_read_minisymbols
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#define verilog_minisymbol_to_symbol _bfd_generic_minisymbol_to_symbol
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#define verilog_minisymbol_to_symbol _bfd_generic_minisymbol_to_symbol
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#define verilog_get_section_contents_in_window _bfd_generic_get_section_contents_in_window
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#define verilog_get_section_contents_in_window _bfd_generic_get_section_contents_in_window
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#define verilog_bfd_get_relocated_section_contents bfd_generic_get_relocated_section_contents
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#define verilog_bfd_get_relocated_section_contents bfd_generic_get_relocated_section_contents
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#define verilog_bfd_relax_section bfd_generic_relax_section
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#define verilog_bfd_relax_section bfd_generic_relax_section
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#define verilog_bfd_gc_sections bfd_generic_gc_sections
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#define verilog_bfd_gc_sections bfd_generic_gc_sections
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#define verilog_bfd_merge_sections bfd_generic_merge_sections
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#define verilog_bfd_merge_sections bfd_generic_merge_sections
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#define verilog_bfd_is_group_section bfd_generic_is_group_section
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#define verilog_bfd_is_group_section bfd_generic_is_group_section
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#define verilog_bfd_discard_group bfd_generic_discard_group
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#define verilog_bfd_discard_group bfd_generic_discard_group
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#define verilog_section_already_linked _bfd_generic_section_already_linked
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#define verilog_section_already_linked _bfd_generic_section_already_linked
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#define verilog_bfd_link_hash_table_create _bfd_generic_link_hash_table_create
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#define verilog_bfd_link_hash_table_create _bfd_generic_link_hash_table_create
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#define verilog_bfd_link_hash_table_free _bfd_generic_link_hash_table_free
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#define verilog_bfd_link_hash_table_free _bfd_generic_link_hash_table_free
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#define verilog_bfd_link_add_symbols _bfd_generic_link_add_symbols
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#define verilog_bfd_link_add_symbols _bfd_generic_link_add_symbols
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#define verilog_bfd_link_just_syms _bfd_generic_link_just_syms
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#define verilog_bfd_link_just_syms _bfd_generic_link_just_syms
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#define verilog_bfd_final_link _bfd_generic_final_link
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#define verilog_bfd_final_link _bfd_generic_final_link
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#define verilog_bfd_link_split_section _bfd_generic_link_split_section
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#define verilog_bfd_link_split_section _bfd_generic_link_split_section
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const bfd_target verilog_vec =
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const bfd_target verilog_vec =
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{
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{
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"verilog", /* Name. */
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"verilog", /* Name. */
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bfd_target_verilog_flavour,
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bfd_target_verilog_flavour,
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BFD_ENDIAN_UNKNOWN, /* Target byte order. */
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BFD_ENDIAN_UNKNOWN, /* Target byte order. */
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BFD_ENDIAN_UNKNOWN, /* Target headers byte order. */
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BFD_ENDIAN_UNKNOWN, /* Target headers byte order. */
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(HAS_RELOC | EXEC_P | /* Object flags. */
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(HAS_RELOC | EXEC_P | /* Object flags. */
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HAS_LINENO | HAS_DEBUG |
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HAS_LINENO | HAS_DEBUG |
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HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
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HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
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(SEC_CODE | SEC_DATA | SEC_ROM | SEC_HAS_CONTENTS
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(SEC_CODE | SEC_DATA | SEC_ROM | SEC_HAS_CONTENTS
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| SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags. */
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| SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags. */
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0, /* Leading underscore. */
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0, /* Leading underscore. */
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' ', /* AR_pad_char. */
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' ', /* AR_pad_char. */
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16, /* AR_max_namelen. */
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16, /* AR_max_namelen. */
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bfd_getb64, bfd_getb_signed_64, bfd_putb64,
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bfd_getb64, bfd_getb_signed_64, bfd_putb64,
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bfd_getb32, bfd_getb_signed_32, bfd_putb32,
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bfd_getb32, bfd_getb_signed_32, bfd_putb32,
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bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Data. */
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bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Data. */
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bfd_getb64, bfd_getb_signed_64, bfd_putb64,
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bfd_getb64, bfd_getb_signed_64, bfd_putb64,
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bfd_getb32, bfd_getb_signed_32, bfd_putb32,
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bfd_getb32, bfd_getb_signed_32, bfd_putb32,
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bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Hdrs. */
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bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Hdrs. */
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{
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{
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_bfd_dummy_target,
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_bfd_dummy_target,
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_bfd_dummy_target,
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_bfd_dummy_target,
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_bfd_dummy_target,
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_bfd_dummy_target,
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_bfd_dummy_target,
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_bfd_dummy_target,
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},
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},
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{
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{
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bfd_false,
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bfd_false,
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verilog_mkobject,
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verilog_mkobject,
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bfd_false,
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bfd_false,
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bfd_false,
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bfd_false,
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},
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},
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{ /* bfd_write_contents. */
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{ /* bfd_write_contents. */
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bfd_false,
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bfd_false,
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verilog_write_object_contents,
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verilog_write_object_contents,
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bfd_false,
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bfd_false,
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bfd_false,
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bfd_false,
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},
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},
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BFD_JUMP_TABLE_GENERIC (_bfd_generic),
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BFD_JUMP_TABLE_GENERIC (_bfd_generic),
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BFD_JUMP_TABLE_COPY (_bfd_generic),
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BFD_JUMP_TABLE_COPY (_bfd_generic),
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BFD_JUMP_TABLE_CORE (_bfd_nocore),
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BFD_JUMP_TABLE_CORE (_bfd_nocore),
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BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive),
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BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive),
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BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols),
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BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols),
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BFD_JUMP_TABLE_RELOCS (_bfd_norelocs),
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BFD_JUMP_TABLE_RELOCS (_bfd_norelocs),
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BFD_JUMP_TABLE_WRITE (verilog),
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BFD_JUMP_TABLE_WRITE (verilog),
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BFD_JUMP_TABLE_LINK (_bfd_nolink),
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BFD_JUMP_TABLE_LINK (_bfd_nolink),
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BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
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BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
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NULL,
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NULL,
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NULL
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NULL
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};
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};
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