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[/] [openrisc/] [tags/] [gnu-src/] [gdb-7.2/] [gdb-7.2-or32-1.0rc1/] [sim/] [lm32/] [cpu.c] - Diff between revs 330 and 341

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Rev 330 Rev 341
/* Misc. support for CPU family lm32bf.
/* Misc. support for CPU family lm32bf.
 
 
THIS FILE IS MACHINE GENERATED WITH CGEN.
THIS FILE IS MACHINE GENERATED WITH CGEN.
 
 
Copyright 1996-2010 Free Software Foundation, Inc.
Copyright 1996-2010 Free Software Foundation, Inc.
 
 
This file is part of the GNU simulators.
This file is part of the GNU simulators.
 
 
   This file is free software; you can redistribute it and/or modify
   This file is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   the Free Software Foundation; either version 3, or (at your option)
   any later version.
   any later version.
 
 
   It is distributed in the hope that it will be useful, but WITHOUT
   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.
   License for more details.
 
 
   You should have received a copy of the GNU General Public License along
   You should have received a copy of the GNU General Public License along
   with this program; if not, write to the Free Software Foundation, Inc.,
   with this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 
*/
*/
 
 
#define WANT_CPU lm32bf
#define WANT_CPU lm32bf
#define WANT_CPU_LM32BF
#define WANT_CPU_LM32BF
 
 
#include "sim-main.h"
#include "sim-main.h"
#include "cgen-ops.h"
#include "cgen-ops.h"
 
 
/* Get the value of h-pc.  */
/* Get the value of h-pc.  */
 
 
USI
USI
lm32bf_h_pc_get (SIM_CPU *current_cpu)
lm32bf_h_pc_get (SIM_CPU *current_cpu)
{
{
  return CPU (h_pc);
  return CPU (h_pc);
}
}
 
 
/* Set a value for h-pc.  */
/* Set a value for h-pc.  */
 
 
void
void
lm32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
lm32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
{
{
  CPU (h_pc) = newval;
  CPU (h_pc) = newval;
}
}
 
 
/* Get the value of h-gr.  */
/* Get the value of h-gr.  */
 
 
SI
SI
lm32bf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
lm32bf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
{
  return CPU (h_gr[regno]);
  return CPU (h_gr[regno]);
}
}
 
 
/* Set a value for h-gr.  */
/* Set a value for h-gr.  */
 
 
void
void
lm32bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
lm32bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
{
  CPU (h_gr[regno]) = newval;
  CPU (h_gr[regno]) = newval;
}
}
 
 
/* Get the value of h-csr.  */
/* Get the value of h-csr.  */
 
 
SI
SI
lm32bf_h_csr_get (SIM_CPU *current_cpu, UINT regno)
lm32bf_h_csr_get (SIM_CPU *current_cpu, UINT regno)
{
{
  return CPU (h_csr[regno]);
  return CPU (h_csr[regno]);
}
}
 
 
/* Set a value for h-csr.  */
/* Set a value for h-csr.  */
 
 
void
void
lm32bf_h_csr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
lm32bf_h_csr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
{
  CPU (h_csr[regno]) = newval;
  CPU (h_csr[regno]) = newval;
}
}
 
 
/* Record trace results for INSN.  */
/* Record trace results for INSN.  */
 
 
void
void
lm32bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
lm32bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
                            int *indices, TRACE_RECORD *tr)
                            int *indices, TRACE_RECORD *tr)
{
{
}
}
 
 

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