/* Lattice Mico32 simulator support code.
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/* Lattice Mico32 simulator support code.
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Contributed by Jon Beniston <jon@beniston.com>
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Contributed by Jon Beniston <jon@beniston.com>
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Copyright (C) 2009, 2010 Free Software Foundation, Inc.
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Copyright (C) 2009, 2010 Free Software Foundation, Inc.
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This file is part of GDB.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#define WANT_CPU lm32bf
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#define WANT_CPU lm32bf
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#define WANT_CPU_LM32BF
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#define WANT_CPU_LM32BF
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#include "sim-main.h"
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#include "sim-main.h"
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#include "cgen-mem.h"
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#include "cgen-mem.h"
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#include "cgen-ops.h"
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#include "cgen-ops.h"
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/* The contents of BUF are in target byte order. */
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/* The contents of BUF are in target byte order. */
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int
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int
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lm32bf_fetch_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
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lm32bf_fetch_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
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int len)
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int len)
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{
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{
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if (rn < 32)
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if (rn < 32)
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SETTSI (buf, lm32bf_h_gr_get (current_cpu, rn));
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SETTSI (buf, lm32bf_h_gr_get (current_cpu, rn));
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else
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else
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switch (rn)
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switch (rn)
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{
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{
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case SIM_LM32_PC_REGNUM:
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case SIM_LM32_PC_REGNUM:
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SETTSI (buf, lm32bf_h_pc_get (current_cpu));
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SETTSI (buf, lm32bf_h_pc_get (current_cpu));
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break;
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break;
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default:
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default:
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return 0;
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return 0;
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}
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}
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return -1;
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return -1;
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}
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}
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/* The contents of BUF are in target byte order. */
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/* The contents of BUF are in target byte order. */
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int
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int
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lm32bf_store_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
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lm32bf_store_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
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int len)
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int len)
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{
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{
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if (rn < 32)
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if (rn < 32)
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lm32bf_h_gr_set (current_cpu, rn, GETTSI (buf));
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lm32bf_h_gr_set (current_cpu, rn, GETTSI (buf));
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else
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else
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switch (rn)
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switch (rn)
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{
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{
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case SIM_LM32_PC_REGNUM:
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case SIM_LM32_PC_REGNUM:
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lm32bf_h_pc_set (current_cpu, GETTSI (buf));
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lm32bf_h_pc_set (current_cpu, GETTSI (buf));
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break;
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break;
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default:
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default:
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return 0;
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return 0;
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}
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}
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return -1;
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return -1;
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}
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}
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#if WITH_PROFILE_MODEL_P
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#if WITH_PROFILE_MODEL_P
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/* Initialize cycle counting for an insn.
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/* Initialize cycle counting for an insn.
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FIRST_P is non-zero if this is the first insn in a set of parallel
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FIRST_P is non-zero if this is the first insn in a set of parallel
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insns. */
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insns. */
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void
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void
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lm32bf_model_insn_before (SIM_CPU * cpu, int first_p)
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lm32bf_model_insn_before (SIM_CPU * cpu, int first_p)
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{
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{
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}
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}
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/* Record the cycles computed for an insn.
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/* Record the cycles computed for an insn.
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LAST_P is non-zero if this is the last insn in a set of parallel insns,
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LAST_P is non-zero if this is the last insn in a set of parallel insns,
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and we update the total cycle count.
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and we update the total cycle count.
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CYCLES is the cycle count of the insn. */
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CYCLES is the cycle count of the insn. */
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void
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void
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lm32bf_model_insn_after (SIM_CPU * cpu, int last_p, int cycles)
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lm32bf_model_insn_after (SIM_CPU * cpu, int last_p, int cycles)
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{
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{
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}
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}
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int
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int
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lm32bf_model_lm32_u_exec (SIM_CPU * cpu, const IDESC * idesc,
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lm32bf_model_lm32_u_exec (SIM_CPU * cpu, const IDESC * idesc,
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int unit_num, int referenced)
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int unit_num, int referenced)
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{
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{
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return idesc->timing->units[unit_num].done;
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return idesc->timing->units[unit_num].done;
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}
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}
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#endif /* WITH_PROFILE_MODEL_P */
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#endif /* WITH_PROFILE_MODEL_P */
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