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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [newlib-1.18.0/] [newlib-1.18.0-or32-1.0rc1/] [libgloss/] [sparc/] [erc32-io.c] - Diff between revs 207 and 345

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Rev 207	Rev 345
`#define USE_PORT_A`	`#define USE_PORT_A`

`#define RXADATA (int *) 0x01F800E0`	`#define RXADATA (int *) 0x01F800E0`
`#define RXBDATA (int *) 0x01F800E4`	`#define RXBDATA (int *) 0x01F800E4`
`#define RXSTAT (int *) 0x01F800E8`	`#define RXSTAT (int *) 0x01F800E8`

`void`	`void`
`outbyte (int c)`	`outbyte (int c)`
`{`	`{`
`volatile int *rxstat;`	`volatile int *rxstat;`
`volatile int *rxadata;`	`volatile int *rxadata;`
`int rxmask;`	`int rxmask;`

`rxstat = RXSTAT;`	`rxstat = RXSTAT;`
`#ifdef USE_PORT_A`	`#ifdef USE_PORT_A`
`rxadata = RXADATA;`	`rxadata = RXADATA;`
`rxmask = 6;`	`rxmask = 6;`
`#else`	`#else`
`rxadata = RXBDATA;`	`rxadata = RXBDATA;`
`rxmask = 0x60000;`	`rxmask = 0x60000;`
`#endif`	`#endif`

`while ((*rxstat & rxmask) == 0);`	`while ((*rxstat & rxmask) == 0);`

`*rxadata = c;`	`*rxadata = c;`
`}`	`}`

`int`	`int`
`inbyte (void)`	`inbyte (void)`
`{`	`{`
`volatile int *rxstat;`	`volatile int *rxstat;`
`volatile int *rxadata;`	`volatile int *rxadata;`
`int rxmask;`	`int rxmask;`

`rxstat = RXSTAT;`	`rxstat = RXSTAT;`
`#ifdef USE_PORT_A`	`#ifdef USE_PORT_A`
`rxadata = RXADATA;`	`rxadata = RXADATA;`
`rxmask = 1;`	`rxmask = 1;`
`#else`	`#else`
`rxadata = RXBDATA;`	`rxadata = RXBDATA;`
`rxmask = 0x10000;`	`rxmask = 0x10000;`
`#endif`	`#endif`

`while ((*rxstat & rxmask) == 0);`	`while ((*rxstat & rxmask) == 0);`

`return *rxadata;`	`return *rxadata;`
`}`	`}`

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