/*
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/*
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* Copyright (c) 1996 Cygnus Support
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* Copyright (c) 1996 Cygnus Support
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*
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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* they apply.
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*/
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*/
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#include <string.h>
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#include <string.h>
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#include <signal.h>
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#include <signal.h>
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#include "debug.h"
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#include "debug.h"
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#include "asm.h"
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#include "asm.h"
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#include "slite.h"
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#include "slite.h"
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extern unsigned long rdtbr();
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extern unsigned long rdtbr();
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extern struct trap_entry fltr_proto;
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extern struct trap_entry fltr_proto;
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extern void trap_low();
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extern void trap_low();
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exception_t default_trap_hook = trap_low;
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exception_t default_trap_hook = trap_low;
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void target_reset();
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void target_reset();
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void flush_i_cache();
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void flush_i_cache();
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char *target_read_registers(unsigned long *);
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char *target_read_registers(unsigned long *);
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char *target_write_registers(unsigned long *);
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char *target_write_registers(unsigned long *);
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char *target_dump_state(unsigned long *);
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char *target_dump_state(unsigned long *);
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#define NUMREGS 72
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#define NUMREGS 72
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/* Number of bytes of registers. */
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/* Number of bytes of registers. */
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#define NUMREGBYTES (NUMREGS * 4)
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#define NUMREGBYTES (NUMREGS * 4)
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enum regnames {G0, G1, G2, G3, G4, G5, G6, G7,
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enum regnames {G0, G1, G2, G3, G4, G5, G6, G7,
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O0, O1, O2, O3, O4, O5, SP, O7,
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O0, O1, O2, O3, O4, O5, SP, O7,
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L0, L1, L2, L3, L4, L5, L6, L7,
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L0, L1, L2, L3, L4, L5, L6, L7,
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I0, I1, I2, I3, I4, I5, FP, I7,
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I0, I1, I2, I3, I4, I5, FP, I7,
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F0, F1, F2, F3, F4, F5, F6, F7,
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F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15,
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F8, F9, F10, F11, F12, F13, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23,
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F16, F17, F18, F19, F20, F21, F22, F23,
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F24, F25, F26, F27, F28, F29, F30, F31,
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F24, F25, F26, F27, F28, F29, F30, F31,
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Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR };
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Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR };
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/*
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/*
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* Each entry in the trap vector occupies four words, typically a jump
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* Each entry in the trap vector occupies four words, typically a jump
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* to the processing routine.
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* to the processing routine.
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*/
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*/
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struct trap_entry {
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struct trap_entry {
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unsigned sethi_filler:10;
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unsigned sethi_filler:10;
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unsigned sethi_imm22:22;
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unsigned sethi_imm22:22;
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unsigned jmpl_filler:19;
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unsigned jmpl_filler:19;
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unsigned jmpl_simm13:13;
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unsigned jmpl_simm13:13;
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unsigned long filler[2];
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unsigned long filler[2];
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};
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};
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/*
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/*
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* This table contains the mapping between SPARC hardware trap types, and
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* This table contains the mapping between SPARC hardware trap types, and
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* signals, which are primarily what GDB understands. It also indicates
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* signals, which are primarily what GDB understands. It also indicates
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* which hardware traps we need to commandeer when initializing the stub.
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* which hardware traps we need to commandeer when initializing the stub.
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*/
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*/
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struct trap_info hard_trap_info[] = {
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struct trap_info hard_trap_info[] = {
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{1, SIGSEGV}, /* instruction access error */
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{1, SIGSEGV}, /* instruction access error */
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{2, SIGILL}, /* privileged instruction */
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{2, SIGILL}, /* privileged instruction */
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{3, SIGILL}, /* illegal instruction */
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{3, SIGILL}, /* illegal instruction */
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{4, SIGEMT}, /* fp disabled */
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{4, SIGEMT}, /* fp disabled */
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{36, SIGEMT}, /* cp disabled */
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{36, SIGEMT}, /* cp disabled */
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{7, SIGBUS}, /* mem address not aligned */
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{7, SIGBUS}, /* mem address not aligned */
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{9, SIGSEGV}, /* data access exception */
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{9, SIGSEGV}, /* data access exception */
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{10, SIGEMT}, /* tag overflow */
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{10, SIGEMT}, /* tag overflow */
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{128+1, SIGTRAP}, /* ta 1 - normal breakpoint instruction */
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{128+1, SIGTRAP}, /* ta 1 - normal breakpoint instruction */
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{0, 0} /* Must be last */
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{0, 0} /* Must be last */
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};
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};
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extern struct trap_entry fltr_proto;
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extern struct trap_entry fltr_proto;
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void
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void
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exception_handler (int tt, unsigned long routine)
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exception_handler (int tt, unsigned long routine)
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{
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{
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struct trap_entry *tb; /* Trap vector base address */
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struct trap_entry *tb; /* Trap vector base address */
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DEBUG (1, "Entering exception_handler()");
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DEBUG (1, "Entering exception_handler()");
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if (tt != 256) {
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if (tt != 256) {
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tb = (struct trap_entry *) (rdtbr() & ~0xfff);
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tb = (struct trap_entry *) (rdtbr() & ~0xfff);
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} else {
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} else {
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tt = 255;
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tt = 255;
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tb = (struct trap_entry *) 0;
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tb = (struct trap_entry *) 0;
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}
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}
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tb[tt] = fltr_proto;
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tb[tt] = fltr_proto;
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tb[tt].sethi_imm22 = routine >> 10;
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tb[tt].sethi_imm22 = routine >> 10;
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tb[tt].jmpl_simm13 = routine & 0x3ff;
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tb[tt].jmpl_simm13 = routine & 0x3ff;
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DEBUG (1, "Leaving exception_handler()");
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DEBUG (1, "Leaving exception_handler()");
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}
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}
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/*
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/*
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* This is so we can trap a memory fault when reading or writing
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* This is so we can trap a memory fault when reading or writing
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* directly to memory.
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* directly to memory.
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*/
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*/
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void
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void
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set_mem_fault_trap(enable)
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set_mem_fault_trap(enable)
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int enable;
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int enable;
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{
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{
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extern void fltr_set_mem_err();
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extern void fltr_set_mem_err();
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DEBUG (1, "Entering set_mem_fault_trap()");
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DEBUG (1, "Entering set_mem_fault_trap()");
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mem_err = 0;
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mem_err = 0;
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if (enable)
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if (enable)
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exception_handler(9, (unsigned long)fltr_set_mem_err);
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exception_handler(9, (unsigned long)fltr_set_mem_err);
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else
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else
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exception_handler(9, (unsigned long)trap_low);
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exception_handler(9, (unsigned long)trap_low);
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DEBUG (1, "Leaving set_mem_fault_trap()");
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DEBUG (1, "Leaving set_mem_fault_trap()");
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}
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}
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/*
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/*
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* This function does all command procesing for interfacing to gdb. It
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* This function does all command procesing for interfacing to gdb. It
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* returns 1 if you should skip the instruction at the trap address, 0
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* returns 1 if you should skip the instruction at the trap address, 0
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* otherwise.
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* otherwise.
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*/
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*/
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extern void breakinst();
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extern void breakinst();
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void
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void
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handle_exception (registers)
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handle_exception (registers)
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unsigned long *registers;
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unsigned long *registers;
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{
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{
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int sigval;
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int sigval;
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/* First, we must force all of the windows to be spilled out */
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/* First, we must force all of the windows to be spilled out */
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DEBUG (1, "Entering handle_exception()");
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DEBUG (1, "Entering handle_exception()");
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/* asm("mov %g0, %wim ; nop; nop; nop"); */
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/* asm("mov %g0, %wim ; nop; nop; nop"); */
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asm(" save %sp, -64, %sp \n\
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asm(" save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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save %sp, -64, %sp \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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restore \n\
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");
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");
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if (registers[PC] == (unsigned long)breakinst) {
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if (registers[PC] == (unsigned long)breakinst) {
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registers[PC] = registers[NPC];
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registers[PC] = registers[NPC];
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registers[NPC] += 4;
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registers[NPC] += 4;
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}
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}
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/* get the last know signal number from the trap register */
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/* get the last know signal number from the trap register */
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sigval = computeSignal((registers[TBR] >> 4) & 0xff);
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sigval = computeSignal((registers[TBR] >> 4) & 0xff);
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/* call the main command processing loop for gdb */
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/* call the main command processing loop for gdb */
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gdb_event_loop (sigval, registers);
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gdb_event_loop (sigval, registers);
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}
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}
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/*
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/*
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* This function will generate a breakpoint exception. It is used at the
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* This function will generate a breakpoint exception. It is used at the
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* beginning of a program to sync up with a debugger and can be used
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* beginning of a program to sync up with a debugger and can be used
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* otherwise as a quick means to stop program execution and "break" into
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* otherwise as a quick means to stop program execution and "break" into
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* the debugger.
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* the debugger.
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*/
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*/
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void
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void
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breakpoint()
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breakpoint()
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{
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{
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DEBUG (1, "Entering breakpoint()");
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DEBUG (1, "Entering breakpoint()");
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if (!initialized)
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if (!initialized)
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return;
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return;
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asm(" .globl " STRINGSYM(breakinst) " \n\
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asm(" .globl " STRINGSYM(breakinst) " \n\
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" STRINGSYM(breakinst) ": ta 128+1 \n\
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" STRINGSYM(breakinst) ": ta 128+1 \n\
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nop \n\
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nop \n\
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nop \n\
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nop \n\
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");
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");
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}
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}
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/*
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/*
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* This is just a test vector for debugging excpetions.
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* This is just a test vector for debugging excpetions.
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*/
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*/
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void
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void
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bad_trap(tt)
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bad_trap(tt)
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int tt;
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int tt;
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{
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{
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print ("Got a bad trap #");
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print ("Got a bad trap #");
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outbyte (tt);
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outbyte (tt);
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outbyte ('\n');
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outbyte ('\n');
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asm("ta 0 \n\
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asm("ta 0 \n\
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nop \n\
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nop \n\
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nop \n\
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nop \n\
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");
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");
|
}
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}
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|
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/*
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/*
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* This is just a test vector for debugging excpetions.
|
* This is just a test vector for debugging excpetions.
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*/
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*/
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void
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void
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soft_trap(tt)
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soft_trap(tt)
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int tt;
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int tt;
|
{
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{
|
print ("Got a soft trap #");
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print ("Got a soft trap #");
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outbyte (tt);
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outbyte (tt);
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outbyte ('\n');
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outbyte ('\n');
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asm("ta 0 \n\
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asm("ta 0 \n\
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nop \n\
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nop \n\
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nop \n\
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nop \n\
|
");
|
");
|
}
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}
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|
|
/*
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/*
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* Flush the instruction cache. We need to do this for the debugger stub so
|
* Flush the instruction cache. We need to do this for the debugger stub so
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* that breakpoints, et. al. become visible to the instruction stream after
|
* that breakpoints, et. al. become visible to the instruction stream after
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* storing them in memory.
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* storing them in memory.
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*
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*
|
* For the sparclite, we need to do something here, but for a standard
|
* For the sparclite, we need to do something here, but for a standard
|
* sparc (which SIS simulates), we don't.
|
* sparc (which SIS simulates), we don't.
|
*/
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*/
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|
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void
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void
|
flush_i_cache ()
|
flush_i_cache ()
|
{
|
{
|
}
|
}
|
|
|
/*
|
/*
|
* This will reset the processor, so we never return from here.
|
* This will reset the processor, so we never return from here.
|
*/
|
*/
|
void
|
void
|
target_reset()
|
target_reset()
|
{
|
{
|
asm ("call 0 \n\
|
asm ("call 0 \n\
|
nop ");
|
nop ");
|
}
|
}
|
|
|
/*
|
/*
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* g - read registers.
|
* g - read registers.
|
* no params.
|
* no params.
|
* returns a vector of words, size is NUM_REGS.
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* returns a vector of words, size is NUM_REGS.
|
*/
|
*/
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char *
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char *
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target_read_registers(unsigned long *registers)
|
target_read_registers(unsigned long *registers)
|
{
|
{
|
char *ptr;
|
char *ptr;
|
unsigned long *sp;
|
unsigned long *sp;
|
|
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DEBUG (1, "In target_read_registers()");
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DEBUG (1, "In target_read_registers()");
|
|
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ptr = packet_out_buf;
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ptr = packet_out_buf;
|
ptr = mem2hex((char *)registers, ptr, 16 * 4, 0); /* G & O regs */
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ptr = mem2hex((char *)registers, ptr, 16 * 4, 0); /* G & O regs */
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ptr = mem2hex((unsigned char *)(sp + 0), ptr, 16 * 4, 0); /* L & I regs */
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ptr = mem2hex((unsigned char *)(sp + 0), ptr, 16 * 4, 0); /* L & I regs */
|
memset(ptr, '0', 32 * 8); /* Floating point */
|
memset(ptr, '0', 32 * 8); /* Floating point */
|
mem2hex((char *)®isters[Y],
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mem2hex((char *)®isters[Y],
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ptr + 32 * 4 * 2,
|
ptr + 32 * 4 * 2,
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8 * 4,
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8 * 4,
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0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
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0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
|
return (ptr);
|
return (ptr);
|
}
|
}
|
|
|
/*
|
/*
|
* G - write registers.
|
* G - write registers.
|
* param is a vector of words, size is NUM_REGS.
|
* param is a vector of words, size is NUM_REGS.
|
* returns an OK or an error number.
|
* returns an OK or an error number.
|
*/
|
*/
|
char *
|
char *
|
target_write_registers(unsigned long *registers)
|
target_write_registers(unsigned long *registers)
|
{
|
{
|
unsigned char *ptr;
|
unsigned char *ptr;
|
unsigned long *sp;
|
unsigned long *sp;
|
unsigned long *newsp, psr;
|
unsigned long *newsp, psr;
|
|
|
DEBUG (1, "In target_write_registers()");
|
DEBUG (1, "In target_write_registers()");
|
|
|
psr = registers[PSR];
|
psr = registers[PSR];
|
|
|
ptr = &packet_in_buf[1];
|
ptr = &packet_in_buf[1];
|
|
|
hex2mem(ptr, (char *)registers, 16 * 4, 0); /* G & O regs */
|
hex2mem(ptr, (char *)registers, 16 * 4, 0); /* G & O regs */
|
hex2mem(ptr + 16 * 4 * 2, (unsigned char *)(sp + 0), 16 * 4, 0); /* L & I regs */
|
hex2mem(ptr + 16 * 4 * 2, (unsigned char *)(sp + 0), 16 * 4, 0); /* L & I regs */
|
hex2mem(ptr + 64 * 4 * 2, (char *)®isters[Y],
|
hex2mem(ptr + 64 * 4 * 2, (char *)®isters[Y],
|
8 * 4, 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
|
8 * 4, 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
|
|
|
/*
|
/*
|
* see if the stack pointer has moved. If so, then copy the saved
|
* see if the stack pointer has moved. If so, then copy the saved
|
* locals and ins to the new location. This keeps the window
|
* locals and ins to the new location. This keeps the window
|
* overflow and underflow routines happy.
|
* overflow and underflow routines happy.
|
*/
|
*/
|
|
|
newsp = (unsigned long *)registers[SP];
|
newsp = (unsigned long *)registers[SP];
|
if (sp != newsp)
|
if (sp != newsp)
|
sp = memcpy(newsp, sp, 16 * 4);
|
sp = memcpy(newsp, sp, 16 * 4);
|
|
|
/* Don't allow CWP to be modified. */
|
/* Don't allow CWP to be modified. */
|
|
|
if (psr != registers[PSR])
|
if (psr != registers[PSR])
|
registers[PSR] = (psr & 0x1f) | (registers[PSR] & ~0x1f);
|
registers[PSR] = (psr & 0x1f) | (registers[PSR] & ~0x1f);
|
|
|
return (ptr);
|
return (ptr);
|
}
|
}
|
|
|
char *
|
char *
|
target_dump_state(unsigned long *registers)
|
target_dump_state(unsigned long *registers)
|
{
|
{
|
int tt; /* Trap type */
|
int tt; /* Trap type */
|
int sigval;
|
int sigval;
|
char *ptr;
|
char *ptr;
|
unsigned long *sp;
|
unsigned long *sp;
|
|
|
DEBUG (1, "In target_dump_state()");
|
DEBUG (1, "In target_dump_state()");
|
|
|
sp = (unsigned long *)registers[SP];
|
sp = (unsigned long *)registers[SP];
|
|
|
tt = (registers[TBR] >> 4) & 0xff;
|
tt = (registers[TBR] >> 4) & 0xff;
|
|
|
/* reply to host that an exception has occurred */
|
/* reply to host that an exception has occurred */
|
sigval = computeSignal(tt);
|
sigval = computeSignal(tt);
|
ptr = packet_out_buf;
|
ptr = packet_out_buf;
|
|
|
*ptr++ = 'T';
|
*ptr++ = 'T';
|
*ptr++ = hexchars[sigval >> 4];
|
*ptr++ = hexchars[sigval >> 4];
|
*ptr++ = hexchars[sigval & 0xf];
|
*ptr++ = hexchars[sigval & 0xf];
|
|
|
*ptr++ = hexchars[PC >> 4];
|
*ptr++ = hexchars[PC >> 4];
|
*ptr++ = hexchars[PC & 0xf];
|
*ptr++ = hexchars[PC & 0xf];
|
*ptr++ = ':';
|
*ptr++ = ':';
|
ptr = mem2hex((unsigned char *)®isters[PC], ptr, 4, 0);
|
ptr = mem2hex((unsigned char *)®isters[PC], ptr, 4, 0);
|
*ptr++ = ';';
|
*ptr++ = ';';
|
|
|
*ptr++ = hexchars[FP >> 4];
|
*ptr++ = hexchars[FP >> 4];
|
*ptr++ = hexchars[FP & 0xf];
|
*ptr++ = hexchars[FP & 0xf];
|
*ptr++ = ':';
|
*ptr++ = ':';
|
ptr = mem2hex((unsigned char *)(sp + 8 + 6), ptr, 4, 0); /* FP */
|
ptr = mem2hex((unsigned char *)(sp + 8 + 6), ptr, 4, 0); /* FP */
|
*ptr++ = ';';
|
*ptr++ = ';';
|
|
|
*ptr++ = hexchars[SP >> 4];
|
*ptr++ = hexchars[SP >> 4];
|
*ptr++ = hexchars[SP & 0xf];
|
*ptr++ = hexchars[SP & 0xf];
|
*ptr++ = ':';
|
*ptr++ = ':';
|
ptr = mem2hex((unsigned char *)&sp, ptr, 4, 0);
|
ptr = mem2hex((unsigned char *)&sp, ptr, 4, 0);
|
*ptr++ = ';';
|
*ptr++ = ';';
|
|
|
*ptr++ = hexchars[NPC >> 4];
|
*ptr++ = hexchars[NPC >> 4];
|
|
|
return (packet_out_buf);
|
return (packet_out_buf);
|
}
|
}
|
|
|
void
|
void
|
write_pc(unsigned long *registers, unsigned long addr)
|
write_pc(unsigned long *registers, unsigned long addr)
|
{
|
{
|
DEBUG (1, "In write_pc");
|
DEBUG (1, "In write_pc");
|
|
|
registers[PC] = addr;
|
registers[PC] = addr;
|
registers[NPC] = addr + 4;
|
registers[NPC] = addr + 4;
|
}
|
}
|
|
|
