/*
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/*
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* Copyright (c) 2008 ARM Ltd
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* Copyright (c) 2008 ARM Ltd
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* modification, are permitted provided that the following conditions
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* are met:
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* products derived from this software without specific prior written
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* permission.
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* permission.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#include "arm_asm.h"
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#include "arm_asm.h"
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#include <_ansi.h>
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#include <_ansi.h>
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#include <string.h>
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#include <string.h>
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#ifdef __thumb2__
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#ifdef __thumb2__
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#define magic1(REG) "#0x01010101"
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#define magic1(REG) "#0x01010101"
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#define magic2(REG) "#0x80808080"
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#define magic2(REG) "#0x80808080"
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#else
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#else
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#define magic1(REG) #REG
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#define magic1(REG) #REG
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#define magic2(REG) #REG ", lsl #7"
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#define magic2(REG) #REG ", lsl #7"
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#endif
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#endif
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char* __attribute__((naked))
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char* __attribute__((naked))
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strcpy (char* dst, const char* src)
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strcpy (char* dst, const char* src)
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{
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{
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asm (
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asm (
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#if !(defined(__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \
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#if !(defined(__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \
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(defined (__thumb__) && !defined (__thumb2__)))
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(defined (__thumb__) && !defined (__thumb2__)))
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"optpld r1\n\t"
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"optpld r1\n\t"
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"eor r2, r0, r1\n\t"
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"eor r2, r0, r1\n\t"
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"mov ip, r0\n\t"
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"mov ip, r0\n\t"
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"tst r2, #3\n\t"
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"tst r2, #3\n\t"
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"bne 4f\n\t"
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"bne 4f\n\t"
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"tst r1, #3\n\t"
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"tst r1, #3\n\t"
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"bne 3f\n"
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"bne 3f\n"
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"5:\n\t"
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"5:\n\t"
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#ifndef __thumb2__
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#ifndef __thumb2__
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"str r5, [sp, #-4]!\n\t"
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"str r5, [sp, #-4]!\n\t"
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"mov r5, #0x01\n\t"
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"mov r5, #0x01\n\t"
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"orr r5, r5, r5, lsl #8\n\t"
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"orr r5, r5, r5, lsl #8\n\t"
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"orr r5, r5, r5, lsl #16\n\t"
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"orr r5, r5, r5, lsl #16\n\t"
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#endif
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#endif
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"str r4, [sp, #-4]!\n\t"
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"str r4, [sp, #-4]!\n\t"
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"tst r1, #4\n\t"
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"tst r1, #4\n\t"
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"ldr r3, [r1], #4\n\t"
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"ldr r3, [r1], #4\n\t"
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"beq 2f\n\t"
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"beq 2f\n\t"
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"sub r2, r3, "magic1(r5)"\n\t"
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"sub r2, r3, "magic1(r5)"\n\t"
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"bics r2, r2, r3\n\t"
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"bics r2, r2, r3\n\t"
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"tst r2, "magic2(r5)"\n\t"
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"tst r2, "magic2(r5)"\n\t"
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"itt eq\n\t"
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"itt eq\n\t"
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"streq r3, [ip], #4\n\t"
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"streq r3, [ip], #4\n\t"
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"ldreq r3, [r1], #4\n"
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"ldreq r3, [r1], #4\n"
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"bne 1f\n\t"
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"bne 1f\n\t"
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/* Inner loop. We now know that r1 is 64-bit aligned, so we
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/* Inner loop. We now know that r1 is 64-bit aligned, so we
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can safely fetch up to two words. This allows us to avoid
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can safely fetch up to two words. This allows us to avoid
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load stalls. */
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load stalls. */
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".p2align 2\n"
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".p2align 2\n"
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"2:\n\t"
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"2:\n\t"
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"optpld r1, #8\n\t"
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"optpld r1, #8\n\t"
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"ldr r4, [r1], #4\n\t"
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"ldr r4, [r1], #4\n\t"
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"sub r2, r3, "magic1(r5)"\n\t"
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"sub r2, r3, "magic1(r5)"\n\t"
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"bics r2, r2, r3\n\t"
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"bics r2, r2, r3\n\t"
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"tst r2, "magic2(r5)"\n\t"
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"tst r2, "magic2(r5)"\n\t"
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"sub r2, r4, "magic1(r5)"\n\t"
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"sub r2, r4, "magic1(r5)"\n\t"
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"bne 1f\n\t"
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"bne 1f\n\t"
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"str r3, [ip], #4\n\t"
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"str r3, [ip], #4\n\t"
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"bics r2, r2, r4\n\t"
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"bics r2, r2, r4\n\t"
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"tst r2, "magic2(r5)"\n\t"
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"tst r2, "magic2(r5)"\n\t"
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"itt eq\n\t"
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"itt eq\n\t"
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"ldreq r3, [r1], #4\n\t"
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"ldreq r3, [r1], #4\n\t"
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"streq r4, [ip], #4\n\t"
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"streq r4, [ip], #4\n\t"
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"beq 2b\n\t"
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"beq 2b\n\t"
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"mov r3, r4\n"
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"mov r3, r4\n"
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"1:\n\t"
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"1:\n\t"
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#ifdef __ARMEB__
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#ifdef __ARMEB__
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"rors r3, r3, #24\n\t"
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"rors r3, r3, #24\n\t"
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#endif
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#endif
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"strb r3, [ip], #1\n\t"
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"strb r3, [ip], #1\n\t"
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"tst r3, #0xff\n\t"
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"tst r3, #0xff\n\t"
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#ifdef __ARMEL__
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#ifdef __ARMEL__
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"ror r3, r3, #8\n\t"
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"ror r3, r3, #8\n\t"
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#endif
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#endif
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"bne 1b\n\t"
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"bne 1b\n\t"
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"ldr r4, [sp], #4\n\t"
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"ldr r4, [sp], #4\n\t"
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#ifndef __thumb2__
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#ifndef __thumb2__
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"ldr r5, [sp], #4\n\t"
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"ldr r5, [sp], #4\n\t"
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#endif
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#endif
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"RETURN\n"
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"RETURN\n"
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|
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/* Strings have the same offset from word alignment, but it's
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/* Strings have the same offset from word alignment, but it's
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not zero. */
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not zero. */
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"3:\n\t"
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"3:\n\t"
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"tst r1, #1\n\t"
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"tst r1, #1\n\t"
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"beq 1f\n\t"
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"beq 1f\n\t"
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"ldrb r2, [r1], #1\n\t"
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"ldrb r2, [r1], #1\n\t"
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"strb r2, [ip], #1\n\t"
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"strb r2, [ip], #1\n\t"
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"cmp r2, #0\n\t"
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"cmp r2, #0\n\t"
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"it eq\n"
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"it eq\n"
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"RETURN eq\n"
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"RETURN eq\n"
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"1:\n\t"
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"1:\n\t"
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"tst r1, #2\n\t"
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"tst r1, #2\n\t"
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"beq 5b\n\t"
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"beq 5b\n\t"
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"ldrh r2, [r1], #2\n\t"
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"ldrh r2, [r1], #2\n\t"
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#ifdef __ARMEB__
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#ifdef __ARMEB__
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"tst r2, #0xff00\n\t"
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"tst r2, #0xff00\n\t"
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"iteet ne\n\t"
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"iteet ne\n\t"
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"strneh r2, [ip], #2\n\t"
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"strneh r2, [ip], #2\n\t"
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"lsreq r2, r2, #8\n\t"
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"lsreq r2, r2, #8\n\t"
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"streqb r2, [ip]\n\t"
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"streqb r2, [ip]\n\t"
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"tstne r2, #0xff\n\t"
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"tstne r2, #0xff\n\t"
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#else
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#else
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"tst r2, #0xff\n\t"
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"tst r2, #0xff\n\t"
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"itet ne\n\t"
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"itet ne\n\t"
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"strneh r2, [ip], #2\n\t"
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"strneh r2, [ip], #2\n\t"
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"streqb r2, [ip]\n\t"
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"streqb r2, [ip]\n\t"
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"tstne r2, #0xff00\n\t"
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"tstne r2, #0xff00\n\t"
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#endif
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#endif
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"bne 5b\n\t"
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"bne 5b\n\t"
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"RETURN\n"
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"RETURN\n"
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|
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/* src and dst do not have a common word-alignement. Fall back to
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/* src and dst do not have a common word-alignement. Fall back to
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byte copying. */
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byte copying. */
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"4:\n\t"
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"4:\n\t"
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"ldrb r2, [r1], #1\n\t"
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"ldrb r2, [r1], #1\n\t"
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"strb r2, [ip], #1\n\t"
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"strb r2, [ip], #1\n\t"
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"cmp r2, #0\n\t"
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"cmp r2, #0\n\t"
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"bne 4b\n\t"
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"bne 4b\n\t"
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"RETURN"
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"RETURN"
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#elif !defined (__thumb__) || defined (__thumb2__)
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#elif !defined (__thumb__) || defined (__thumb2__)
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"mov r3, r0\n\t"
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"mov r3, r0\n\t"
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"1:\n\t"
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"1:\n\t"
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"ldrb r2, [r1], #1\n\t"
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"ldrb r2, [r1], #1\n\t"
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"strb r2, [r3], #1\n\t"
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"strb r2, [r3], #1\n\t"
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"cmp r2, #0\n\t"
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"cmp r2, #0\n\t"
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"bne 1b\n\t"
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"bne 1b\n\t"
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"RETURN"
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"RETURN"
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#else
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#else
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"mov r3, r0\n\t"
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"mov r3, r0\n\t"
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"1:\n\t"
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"1:\n\t"
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"ldrb r2, [r1]\n\t"
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"ldrb r2, [r1]\n\t"
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"add r1, r1, #1\n\t"
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"add r1, r1, #1\n\t"
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"strb r2, [r3]\n\t"
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"strb r2, [r3]\n\t"
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"add r3, r3, #1\n\t"
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"add r3, r3, #1\n\t"
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"cmp r2, #0\n\t"
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"cmp r2, #0\n\t"
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"bne 1b\n\t"
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"bne 1b\n\t"
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"RETURN"
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"RETURN"
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#endif
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#endif
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);
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);
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}
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}
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