/*
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/*
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* Copyright (c) 2008 ARM Ltd
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* Copyright (c) 2008 ARM Ltd
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* modification, are permitted provided that the following conditions
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* are met:
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* products derived from this software without specific prior written
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* permission.
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* permission.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#include "arm_asm.h"
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#include "arm_asm.h"
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#include <_ansi.h>
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#include <_ansi.h>
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#include <string.h>
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#include <string.h>
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#include <limits.h>
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#include <limits.h>
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#if defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \
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#if defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \
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(defined (__thumb__) && !defined (__thumb2__))
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(defined (__thumb__) && !defined (__thumb2__))
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size_t
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size_t
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strlen (const char* str)
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strlen (const char* str)
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{
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{
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int scratch;
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int scratch;
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#if defined (__thumb__) && !defined (__thumb2__)
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#if defined (__thumb__) && !defined (__thumb2__)
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size_t len;
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size_t len;
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asm ("mov %0, #0\n"
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asm ("mov %0, #0\n"
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"1:\n\t"
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"1:\n\t"
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"ldrb %1, [%2, %0]\n\t"
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"ldrb %1, [%2, %0]\n\t"
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"add %0, %0, #1\n\t"
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"add %0, %0, #1\n\t"
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"cmp %1, #0\n\t"
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"cmp %1, #0\n\t"
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"bne 1b"
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"bne 1b"
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: "=&r" (len), "=&r" (scratch) : "r" (str) : "memory", "cc");
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: "=&r" (len), "=&r" (scratch) : "r" (str) : "memory", "cc");
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return len - 1;
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return len - 1;
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#else
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#else
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const char* end;
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const char* end;
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asm ("1:\n\t"
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asm ("1:\n\t"
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"ldrb %1, [%0], #1\n\t"
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"ldrb %1, [%0], #1\n\t"
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"cmp %1, #0\n\t"
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"cmp %1, #0\n\t"
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"bne 1b"
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"bne 1b"
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: "=&r" (end), "=&r" (scratch) : "0" (str) : "memory", "cc");
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: "=&r" (end), "=&r" (scratch) : "0" (str) : "memory", "cc");
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return end - str - 1;
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return end - str - 1;
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#endif
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#endif
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}
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}
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#else
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#else
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size_t __attribute__((naked))
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size_t __attribute__((naked))
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strlen (const char* str)
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strlen (const char* str)
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{
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{
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asm ("len .req r0\n\t"
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asm ("len .req r0\n\t"
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"data .req r3\n\t"
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"data .req r3\n\t"
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"addr .req r1\n\t"
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"addr .req r1\n\t"
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"optpld r0\n\t"
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"optpld r0\n\t"
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/* Word-align address */
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/* Word-align address */
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"bic addr, r0, #3\n\t"
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"bic addr, r0, #3\n\t"
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/* Get adjustment for start ... */
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/* Get adjustment for start ... */
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"ands len, r0, #3\n\t"
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"ands len, r0, #3\n\t"
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"neg len, len\n\t"
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"neg len, len\n\t"
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/* First word of data */
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/* First word of data */
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"ldr data, [addr], #4\n\t"
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"ldr data, [addr], #4\n\t"
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/* Ensure bytes preceeding start ... */
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/* Ensure bytes preceeding start ... */
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"add ip, len, #4\n\t"
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"add ip, len, #4\n\t"
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"mov ip, ip, asl #3\n\t"
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"mov ip, ip, asl #3\n\t"
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"mvn r2, #0\n\t"
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"mvn r2, #0\n\t"
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/* ... are masked out */
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/* ... are masked out */
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#ifdef __thumb__
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#ifdef __thumb__
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"itt ne\n\t"
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"itt ne\n\t"
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# ifdef __ARMEB__
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# ifdef __ARMEB__
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"lslne r2, ip\n\t"
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"lslne r2, ip\n\t"
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# else
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# else
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"lsrne r2, ip\n\t"
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"lsrne r2, ip\n\t"
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# endif
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# endif
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"orrne data, data, r2\n\t"
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"orrne data, data, r2\n\t"
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#else
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#else
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"it ne\n\t"
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"it ne\n\t"
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# ifdef __ARMEB__
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# ifdef __ARMEB__
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"orrne data, data, r2, lsl ip\n\t"
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"orrne data, data, r2, lsl ip\n\t"
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# else
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# else
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"orrne data, data, r2, lsr ip\n\t"
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"orrne data, data, r2, lsr ip\n\t"
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# endif
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# endif
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#endif
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#endif
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/* Magic const 0x01010101 */
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/* Magic const 0x01010101 */
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#ifdef _ISA_ARM_7
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#ifdef _ISA_ARM_7
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"movw ip, #0x101\n\t"
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"movw ip, #0x101\n\t"
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#else
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#else
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"mov ip, #0x1\n\t"
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"mov ip, #0x1\n\t"
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"orr ip, ip, ip, lsl #8\n\t"
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"orr ip, ip, ip, lsl #8\n\t"
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#endif
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#endif
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"orr ip, ip, ip, lsl #16\n"
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"orr ip, ip, ip, lsl #16\n"
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/* This is the main loop. We subtract one from each byte in
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/* This is the main loop. We subtract one from each byte in
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the word: the sign bit changes iff the byte was zero or
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the word: the sign bit changes iff the byte was zero or
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0x80 -- we eliminate the latter case by anding the result
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0x80 -- we eliminate the latter case by anding the result
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with the 1-s complement of the data. */
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with the 1-s complement of the data. */
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"1:\n\t"
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"1:\n\t"
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/* test (data - 0x01010101) */
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/* test (data - 0x01010101) */
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"sub r2, data, ip\n\t"
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"sub r2, data, ip\n\t"
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/* ... & ~data */
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/* ... & ~data */
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"bic r2, r2, data\n\t"
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"bic r2, r2, data\n\t"
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/* ... & 0x80808080 == 0? */
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/* ... & 0x80808080 == 0? */
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"ands r2, r2, ip, lsl #7\n\t"
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"ands r2, r2, ip, lsl #7\n\t"
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#ifdef _ISA_ARM_7
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#ifdef _ISA_ARM_7
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/* yes, get more data... */
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/* yes, get more data... */
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"itt eq\n\t"
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"itt eq\n\t"
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"ldreq data, [addr], #4\n\t"
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"ldreq data, [addr], #4\n\t"
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/* and 4 more bytes */
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/* and 4 more bytes */
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"addeq len, len, #4\n\t"
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"addeq len, len, #4\n\t"
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/* If we have PLD, then unroll the loop a bit. */
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/* If we have PLD, then unroll the loop a bit. */
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"optpld addr, #8\n\t"
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"optpld addr, #8\n\t"
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/* test (data - 0x01010101) */
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/* test (data - 0x01010101) */
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"ittt eq\n\t"
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"ittt eq\n\t"
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"subeq r2, data, ip\n\t"
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"subeq r2, data, ip\n\t"
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/* ... & ~data */
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/* ... & ~data */
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"biceq r2, r2, data\n\t"
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"biceq r2, r2, data\n\t"
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/* ... & 0x80808080 == 0? */
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/* ... & 0x80808080 == 0? */
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"andeqs r2, r2, ip, lsl #7\n\t"
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"andeqs r2, r2, ip, lsl #7\n\t"
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#endif
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#endif
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"itt eq\n\t"
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"itt eq\n\t"
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/* yes, get more data... */
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/* yes, get more data... */
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"ldreq data, [addr], #4\n\t"
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"ldreq data, [addr], #4\n\t"
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/* and 4 more bytes */
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/* and 4 more bytes */
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"addeq len, len, #4\n\t"
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"addeq len, len, #4\n\t"
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"beq 1b\n\t"
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"beq 1b\n\t"
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#ifdef __ARMEB__
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#ifdef __ARMEB__
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"tst data, #0xff000000\n\t"
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"tst data, #0xff000000\n\t"
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"itttt ne\n\t"
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"itttt ne\n\t"
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"addne len, len, #1\n\t"
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"addne len, len, #1\n\t"
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"tstne data, #0xff0000\n\t"
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"tstne data, #0xff0000\n\t"
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"addne len, len, #1\n\t"
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"addne len, len, #1\n\t"
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"tstne data, #0xff00\n\t"
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"tstne data, #0xff00\n\t"
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"it ne\n\t"
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"it ne\n\t"
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"addne len, len, #1\n\t"
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"addne len, len, #1\n\t"
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#else
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#else
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# ifdef _ISA_ARM_5
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# ifdef _ISA_ARM_5
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/* R2 is the residual sign bits from the above test. All we
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/* R2 is the residual sign bits from the above test. All we
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need to do now is establish the position of the first zero
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need to do now is establish the position of the first zero
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byte... */
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byte... */
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/* Little-endian is harder, we need the number of trailing
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/* Little-endian is harder, we need the number of trailing
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zeros / 8 */
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zeros / 8 */
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# ifdef _ISA_ARM_7
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# ifdef _ISA_ARM_7
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"rbit r2, r2\n\t"
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"rbit r2, r2\n\t"
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"clz r2, r2\n\t"
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"clz r2, r2\n\t"
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# else
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# else
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"rsb r1, r2, #0\n\t"
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"rsb r1, r2, #0\n\t"
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"and r2, r2, r1\n\t"
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"and r2, r2, r1\n\t"
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"clz r2, r2\n\t"
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"clz r2, r2\n\t"
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"rsb r2, r2, #31\n\t"
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"rsb r2, r2, #31\n\t"
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# endif
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# endif
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"add len, len, r2, lsr #3\n\t"
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"add len, len, r2, lsr #3\n\t"
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# else /* No CLZ instruction */
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# else /* No CLZ instruction */
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"tst data, #0xff\n\t"
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"tst data, #0xff\n\t"
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"itttt ne\n\t"
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"itttt ne\n\t"
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"addne len, len, #1\n\t"
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"addne len, len, #1\n\t"
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"tstne data, #0xff00\n\t"
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"tstne data, #0xff00\n\t"
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"addne len, len, #1\n\t"
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"addne len, len, #1\n\t"
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"tstne data, #0xff0000\n\t"
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"tstne data, #0xff0000\n\t"
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"it ne\n\t"
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"it ne\n\t"
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"addne len, len, #1\n\t"
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"addne len, len, #1\n\t"
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# endif
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# endif
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#endif
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#endif
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"RETURN");
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"RETURN");
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}
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}
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#endif
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#endif
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