/* A memmove for CRIS.
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/* A memmove for CRIS.
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Copyright (C) 2000-2005 Axis Communications.
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Copyright (C) 2000-2005 Axis Communications.
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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modification, are permitted provided that the following conditions
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are met:
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are met:
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1. Redistributions of source code must retain the above copyright
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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notice, this list of conditions and the following disclaimer.
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2. Neither the name of Axis Communications nor the names of its
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2. Neither the name of Axis Communications nor the names of its
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contributors may be used to endorse or promote products derived
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
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THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
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``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
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COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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POSSIBILITY OF SUCH DAMAGE. */
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/* FIXME: This file should really only be used for reference, as the
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/* FIXME: This file should really only be used for reference, as the
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result is somewhat depending on gcc generating what we expect rather
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result is somewhat depending on gcc generating what we expect rather
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than what we describe. An assembly file should be used instead.
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than what we describe. An assembly file should be used instead.
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Even worse, we base it on memcpy, on the assumption that overlapping
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Even worse, we base it on memcpy, on the assumption that overlapping
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moves are rare, and we will do no worse than the generic memmove. */
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moves are rare, and we will do no worse than the generic memmove. */
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#include <stddef.h>
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#include <stddef.h>
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/* Break even between movem and move16 is really at 38.7 * 2, but
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/* Break even between movem and move16 is really at 38.7 * 2, but
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modulo 44, so up to the next multiple of 44, we use ordinary code. */
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modulo 44, so up to the next multiple of 44, we use ordinary code. */
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#define MEMMOVE_BY_BLOCK_THRESHOLD (44 * 2)
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#define MEMMOVE_BY_BLOCK_THRESHOLD (44 * 2)
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/* No name ambiguities in this file. */
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/* No name ambiguities in this file. */
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__asm__ (".syntax no_register_prefix");
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__asm__ (".syntax no_register_prefix");
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void *
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void *
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memmove(void *pdst, const void *psrc, size_t pn)
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memmove(void *pdst, const void *psrc, size_t pn)
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{
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{
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/* Now we want the parameters put in special registers.
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/* Now we want the parameters put in special registers.
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Make sure the compiler is able to make something useful of this.
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Make sure the compiler is able to make something useful of this.
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As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
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As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
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If gcc was allright, it really would need no temporaries, and no
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If gcc was allright, it really would need no temporaries, and no
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stack space to save stuff on. */
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stack space to save stuff on. */
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register void *return_dst __asm__ ("r10") = pdst;
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register void *return_dst __asm__ ("r10") = pdst;
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register unsigned char *dst __asm__ ("r13") = pdst;
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register unsigned char *dst __asm__ ("r13") = pdst;
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register unsigned const char *src __asm__ ("r11") = psrc;
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register unsigned const char *src __asm__ ("r11") = psrc;
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register int n __asm__ ("r12") = pn;
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register int n __asm__ ("r12") = pn;
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/* Check and handle overlap. */
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/* Check and handle overlap. */
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if (src < dst && dst < src + n)
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if (src < dst && dst < src + n)
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{
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{
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/* Destructive overlap. We could optimize this, but we don't (for
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/* Destructive overlap. We could optimize this, but we don't (for
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the moment). */
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the moment). */
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src += n;
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src += n;
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dst += n;
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dst += n;
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while (n--)
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while (n--)
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{
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{
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*--dst = *--src;
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*--dst = *--src;
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}
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}
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return return_dst;
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return return_dst;
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}
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}
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/* Whew, no overlap. Proceed as with memcpy. We could call it instead
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/* Whew, no overlap. Proceed as with memcpy. We could call it instead
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of having a copy here. That would spoil some of the optimization, so
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of having a copy here. That would spoil some of the optimization, so
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we take the trouble with having two copies. */
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we take the trouble with having two copies. */
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/* When src is aligned but not dst, this makes a few extra needless
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/* When src is aligned but not dst, this makes a few extra needless
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cycles. I believe it would take as many to check that the
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cycles. I believe it would take as many to check that the
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re-alignment was unnecessary. */
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re-alignment was unnecessary. */
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if (((unsigned long) dst & 3) != 0
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if (((unsigned long) dst & 3) != 0
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/* Don't align if we wouldn't copy more than a few bytes; so we
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/* Don't align if we wouldn't copy more than a few bytes; so we
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don't have to check further for overflows. */
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don't have to check further for overflows. */
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&& n >= 3)
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&& n >= 3)
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{
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{
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if ((unsigned long) dst & 1)
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if ((unsigned long) dst & 1)
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{
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{
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n--;
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n--;
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*dst = *src;
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*dst = *src;
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src++;
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src++;
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dst++;
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dst++;
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}
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}
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if ((unsigned long) dst & 2)
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if ((unsigned long) dst & 2)
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{
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{
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n -= 2;
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n -= 2;
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*(short *) dst = *(short *) src;
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*(short *) dst = *(short *) src;
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src += 2;
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src += 2;
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dst += 2;
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dst += 2;
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}
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}
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}
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}
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/* Decide which copying method to use. */
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/* Decide which copying method to use. */
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if (n >= MEMMOVE_BY_BLOCK_THRESHOLD)
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if (n >= MEMMOVE_BY_BLOCK_THRESHOLD)
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{
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{
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/* It is not optimal to tell the compiler about clobbering any
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/* It is not optimal to tell the compiler about clobbering any
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registers; that will move the saving/restoring of those registers
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registers; that will move the saving/restoring of those registers
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to the function prologue/epilogue, and make non-movem sizes
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to the function prologue/epilogue, and make non-movem sizes
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suboptimal. */
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suboptimal. */
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__asm__ volatile
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__asm__ volatile
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("\
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("\
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;; GCC does promise correct register allocations, but let's \n\
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;; GCC does promise correct register allocations, but let's \n\
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;; make sure it keeps its promises. \n\
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;; make sure it keeps its promises. \n\
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.ifnc %0-%1-%2,$r13-$r11-$r12 \n\
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.ifnc %0-%1-%2,$r13-$r11-$r12 \n\
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.error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
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.error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
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.endif \n\
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.endif \n\
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\n\
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\n\
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;; Save the registers we'll use in the movem process \n\
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;; Save the registers we'll use in the movem process \n\
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;; on the stack. \n\
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;; on the stack. \n\
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subq 11*4,sp \n\
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subq 11*4,sp \n\
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movem r10,[sp] \n\
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movem r10,[sp] \n\
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\n\
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\n\
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;; Now we've got this: \n\
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;; Now we've got this: \n\
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;; r11 - src \n\
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;; r11 - src \n\
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;; r13 - dst \n\
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;; r13 - dst \n\
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;; r12 - n \n\
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;; r12 - n \n\
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\n\
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\n\
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;; Update n for the first loop. \n\
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;; Update n for the first loop. \n\
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subq 44,r12 \n\
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subq 44,r12 \n\
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0: \n\
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0: \n\
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"
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"
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#ifdef __arch_common_v10_v32
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#ifdef __arch_common_v10_v32
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/* Cater to branch offset difference between v32 and v10. We
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/* Cater to branch offset difference between v32 and v10. We
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assume the branch below has an 8-bit offset. */
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assume the branch below has an 8-bit offset. */
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" setf\n"
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" setf\n"
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#endif
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#endif
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" movem [r11+],r10 \n\
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" movem [r11+],r10 \n\
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subq 44,r12 \n\
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subq 44,r12 \n\
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bge 0b \n\
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bge 0b \n\
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movem r10,[r13+] \n\
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movem r10,[r13+] \n\
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\n\
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\n\
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;; Compensate for last loop underflowing n. \n\
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;; Compensate for last loop underflowing n. \n\
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addq 44,r12 \n\
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addq 44,r12 \n\
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\n\
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\n\
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;; Restore registers from stack. \n\
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;; Restore registers from stack. \n\
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movem [sp+],r10"
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movem [sp+],r10"
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/* Outputs. */
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/* Outputs. */
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: "=r" (dst), "=r" (src), "=r" (n)
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: "=r" (dst), "=r" (src), "=r" (n)
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/* Inputs. */
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/* Inputs. */
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: "0" (dst), "1" (src), "2" (n));
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: "0" (dst), "1" (src), "2" (n));
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}
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}
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while (n >= 16)
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while (n >= 16)
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{
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{
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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n -= 16;
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n -= 16;
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}
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}
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switch (n)
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switch (n)
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{
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{
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case 0:
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case 0:
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break;
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break;
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case 1:
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case 1:
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*dst = *src;
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*dst = *src;
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break;
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break;
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case 2:
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case 2:
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*(short *) dst = *(short *) src;
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*(short *) dst = *(short *) src;
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break;
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break;
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case 3:
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case 3:
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*(short *) dst = *(short *) src; dst += 2; src += 2;
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*(short *) dst = *(short *) src; dst += 2; src += 2;
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*dst = *src;
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*dst = *src;
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break;
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break;
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case 4:
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case 4:
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*(long *) dst = *(long *) src;
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*(long *) dst = *(long *) src;
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break;
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break;
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case 5:
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case 5:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*dst = *src;
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*dst = *src;
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break;
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break;
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case 6:
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case 6:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(short *) dst = *(short *) src;
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*(short *) dst = *(short *) src;
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break;
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break;
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case 7:
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case 7:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(short *) dst = *(short *) src; dst += 2; src += 2;
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*(short *) dst = *(short *) src; dst += 2; src += 2;
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*dst = *src;
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*dst = *src;
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break;
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break;
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case 8:
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case 8:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src;
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*(long *) dst = *(long *) src;
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break;
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break;
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case 9:
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case 9:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*dst = *src;
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*dst = *src;
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break;
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break;
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case 10:
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case 10:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(short *) dst = *(short *) src;
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*(short *) dst = *(short *) src;
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break;
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break;
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case 11:
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case 11:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(short *) dst = *(short *) src; dst += 2; src += 2;
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*(short *) dst = *(short *) src; dst += 2; src += 2;
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*dst = *src;
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*dst = *src;
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break;
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break;
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case 12:
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case 12:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src;
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*(long *) dst = *(long *) src;
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break;
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break;
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case 13:
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case 13:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*dst = *src;
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*dst = *src;
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break;
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break;
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case 14:
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case 14:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(short *) dst = *(short *) src;
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*(short *) dst = *(short *) src;
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break;
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break;
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case 15:
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case 15:
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(long *) dst = *(long *) src; dst += 4; src += 4;
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*(short *) dst = *(short *) src; dst += 2; src += 2;
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*(short *) dst = *(short *) src; dst += 2; src += 2;
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*dst = *src;
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*dst = *src;
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break;
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break;
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}
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}
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return return_dst;
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return return_dst;
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}
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}
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