OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [newlib-1.18.0/] [newlib-1.18.0-or32-1.0rc1/] [newlib/] [libc/] [machine/] [m68k/] [strcpy.c] - Diff between revs 207 and 345

Only display areas with differences | Details | Blame | View Log

Rev 207 Rev 345
/*
/*
 *  C library strcpy routine
 *  C library strcpy routine
 *
 *
 *  This routine has been optimized for the CPU32+.
 *  This routine has been optimized for the CPU32+.
 *  It should run on all 68k machines.
 *  It should run on all 68k machines.
 *
 *
 *  W. Eric Norum
 *  W. Eric Norum
 *  Saskatchewan Accelerator Laboratory
 *  Saskatchewan Accelerator Laboratory
 *  University of Saskatchewan
 *  University of Saskatchewan
 *  Saskatoon, Saskatchewan, CANADA
 *  Saskatoon, Saskatchewan, CANADA
 *  eric@skatter.usask.ca
 *  eric@skatter.usask.ca
 */
 */
 
 
#include <string.h>
#include <string.h>
 
 
/*
/*
 * Copy bytes using CPU32+ loop mode if possible
 * Copy bytes using CPU32+ loop mode if possible
 */
 */
 
 
char *
char *
strcpy (char *to, const char *from)
strcpy (char *to, const char *from)
{
{
        char *pto = to;
        char *pto = to;
        unsigned int n = 0xFFFF;
        unsigned int n = 0xFFFF;
 
 
        asm volatile ("1:\n"
        asm volatile ("1:\n"
             "\tmove.b (%0)+,(%1)+\n"
             "\tmove.b (%0)+,(%1)+\n"
#if defined(__mcpu32__)
#if defined(__mcpu32__)
             "\tdbeq %2,1b\n"
             "\tdbeq %2,1b\n"
#endif
#endif
             "\tbne.b 1b\n" :
             "\tbne.b 1b\n" :
                "=a" (from), "=a" (pto), "=d" (n) :
                "=a" (from), "=a" (pto), "=d" (n) :
                 "0" (from),  "1" (pto), "2" (n) :
                 "0" (from),  "1" (pto), "2" (n) :
                 "cc", "memory");
                 "cc", "memory");
        return to;
        return to;
}
}
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.