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Rev 345 |
/* We want to pretend we're in SHmedia mode, even when assembling for
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/* We want to pretend we're in SHmedia mode, even when assembling for
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SHcompact. */
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SHcompact. */
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#if __SH5__ == 32 && ! __SHMEDIA__
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#if __SH5__ == 32 && ! __SHMEDIA__
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# undef __SHMEDIA__
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# undef __SHMEDIA__
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# define __SHMEDIA__ 1
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# define __SHMEDIA__ 1
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#endif
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#endif
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#if __SHMEDIA__
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#if __SHMEDIA__
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.mode SHmedia
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.mode SHmedia
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#endif
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#endif
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#include "asm.h"
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#include "asm.h"
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ENTRY(setjmp)
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ENTRY(setjmp)
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#if __SH5__
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#if __SH5__
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ptabs r18, tr0
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ptabs r18, tr0
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gettr tr5, r5
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gettr tr5, r5
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gettr tr6, r6
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gettr tr6, r6
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gettr tr7, r7
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gettr tr7, r7
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st.q r2, 0*8, r18
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st.q r2, 0*8, r18
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st.q r2, 1*8, r10
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st.q r2, 1*8, r10
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st.q r2, 2*8, r11
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st.q r2, 2*8, r11
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st.q r2, 3*8, r12
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st.q r2, 3*8, r12
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st.q r2, 4*8, r13
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st.q r2, 4*8, r13
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st.q r2, 5*8, r14
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st.q r2, 5*8, r14
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st.q r2, 6*8, r15
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st.q r2, 6*8, r15
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st.q r2, 7*8, r28
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st.q r2, 7*8, r28
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st.q r2, 8*8, r29
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st.q r2, 8*8, r29
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st.q r2, 9*8, r30
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st.q r2, 9*8, r30
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st.q r2, 10*8, r31
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st.q r2, 10*8, r31
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st.q r2, 11*8, r32
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st.q r2, 11*8, r32
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st.q r2, 12*8, r33
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st.q r2, 12*8, r33
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st.q r2, 13*8, r34
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st.q r2, 13*8, r34
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st.q r2, 14*8, r35
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st.q r2, 14*8, r35
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st.q r2, 15*8, r44
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st.q r2, 15*8, r44
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st.q r2, 16*8, r45
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st.q r2, 16*8, r45
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st.q r2, 17*8, r46
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st.q r2, 17*8, r46
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st.q r2, 18*8, r47
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st.q r2, 18*8, r47
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st.q r2, 19*8, r48
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st.q r2, 19*8, r48
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st.q r2, 20*8, r49
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st.q r2, 20*8, r49
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st.q r2, 21*8, r50
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st.q r2, 21*8, r50
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st.q r2, 22*8, r51
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st.q r2, 22*8, r51
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st.q r2, 23*8, r52
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st.q r2, 23*8, r52
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st.q r2, 24*8, r53
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st.q r2, 24*8, r53
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st.q r2, 25*8, r54
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st.q r2, 25*8, r54
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st.q r2, 26*8, r55
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st.q r2, 26*8, r55
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st.q r2, 27*8, r56
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st.q r2, 27*8, r56
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st.q r2, 28*8, r57
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st.q r2, 28*8, r57
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st.q r2, 29*8, r58
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st.q r2, 29*8, r58
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st.q r2, 30*8, r59
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st.q r2, 30*8, r59
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st.q r2, 31*8, r5
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st.q r2, 31*8, r5
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st.q r2, 32*8, r6
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st.q r2, 32*8, r6
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st.q r2, 33*8, r7
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st.q r2, 33*8, r7
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#if ! __SH4_NOFPU__
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#if ! __SH4_NOFPU__
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fst.d r2, 34*8, dr12
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fst.d r2, 34*8, dr12
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fst.d r2, 35*8, dr14
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fst.d r2, 35*8, dr14
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fst.d r2, 36*8, dr36
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fst.d r2, 36*8, dr36
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fst.d r2, 37*8, dr38
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fst.d r2, 37*8, dr38
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fst.d r2, 38*8, dr40
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fst.d r2, 38*8, dr40
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fst.d r2, 39*8, dr42
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fst.d r2, 39*8, dr42
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fst.d r2, 40*8, dr44
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fst.d r2, 40*8, dr44
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fst.d r2, 41*8, dr46
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fst.d r2, 41*8, dr46
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fst.d r2, 42*8, dr48
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fst.d r2, 42*8, dr48
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fst.d r2, 43*8, dr50
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fst.d r2, 43*8, dr50
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fst.d r2, 44*8, dr52
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fst.d r2, 44*8, dr52
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fst.d r2, 45*8, dr54
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fst.d r2, 45*8, dr54
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fst.d r2, 46*8, dr56
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fst.d r2, 46*8, dr56
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fst.d r2, 47*8, dr58
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fst.d r2, 47*8, dr58
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fst.d r2, 48*8, dr60
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fst.d r2, 48*8, dr60
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fst.d r2, 49*8, dr62
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fst.d r2, 49*8, dr62
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#endif
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#endif
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movi 0, r2
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movi 0, r2
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blink tr0, r63
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blink tr0, r63
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#else
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#else
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#if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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#if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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add #(13*4),r4
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add #(13*4),r4
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#else
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#else
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add #(9*4),r4
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add #(9*4),r4
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#endif
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#endif
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sts.l pr,@-r4
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sts.l pr,@-r4
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#if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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#if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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fmov.s fr15,@-r4 ! call saved floating point registers
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fmov.s fr15,@-r4 ! call saved floating point registers
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fmov.s fr14,@-r4
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fmov.s fr14,@-r4
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fmov.s fr13,@-r4
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fmov.s fr13,@-r4
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fmov.s fr12,@-r4
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fmov.s fr12,@-r4
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#endif
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#endif
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mov.l r15,@-r4 ! call saved integer registers
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mov.l r15,@-r4 ! call saved integer registers
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mov.l r14,@-r4
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mov.l r14,@-r4
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mov.l r13,@-r4
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mov.l r13,@-r4
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mov.l r12,@-r4
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mov.l r12,@-r4
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mov.l r11,@-r4
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mov.l r11,@-r4
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mov.l r10,@-r4
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mov.l r10,@-r4
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mov.l r9,@-r4
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mov.l r9,@-r4
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mov.l r8,@-r4
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mov.l r8,@-r4
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rts
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rts
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mov #0,r0
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mov #0,r0
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#endif /* __SH5__ */
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#endif /* __SH5__ */
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ENTRY(longjmp)
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ENTRY(longjmp)
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#if __SH5__
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#if __SH5__
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ld.q r2, 0*8, r18
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ld.q r2, 0*8, r18
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ptabs r18, tr0
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ptabs r18, tr0
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ld.q r2, 1*8, r10
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ld.q r2, 1*8, r10
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ld.q r2, 2*8, r11
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ld.q r2, 2*8, r11
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ld.q r2, 3*8, r12
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ld.q r2, 3*8, r12
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ld.q r2, 4*8, r13
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ld.q r2, 4*8, r13
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ld.q r2, 5*8, r14
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ld.q r2, 5*8, r14
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ld.q r2, 6*8, r15
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ld.q r2, 6*8, r15
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ld.q r2, 7*8, r28
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ld.q r2, 7*8, r28
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ld.q r2, 8*8, r29
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ld.q r2, 8*8, r29
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ld.q r2, 9*8, r30
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ld.q r2, 9*8, r30
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ld.q r2, 10*8, r31
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ld.q r2, 10*8, r31
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ld.q r2, 11*8, r32
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ld.q r2, 11*8, r32
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ld.q r2, 12*8, r33
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ld.q r2, 12*8, r33
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ld.q r2, 13*8, r34
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ld.q r2, 13*8, r34
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ld.q r2, 14*8, r35
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ld.q r2, 14*8, r35
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ld.q r2, 15*8, r44
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ld.q r2, 15*8, r44
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ld.q r2, 16*8, r45
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ld.q r2, 16*8, r45
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ld.q r2, 17*8, r46
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ld.q r2, 17*8, r46
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ld.q r2, 18*8, r47
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ld.q r2, 18*8, r47
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ld.q r2, 19*8, r48
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ld.q r2, 19*8, r48
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ld.q r2, 20*8, r49
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ld.q r2, 20*8, r49
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ld.q r2, 21*8, r50
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ld.q r2, 21*8, r50
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ld.q r2, 22*8, r51
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ld.q r2, 22*8, r51
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ld.q r2, 23*8, r52
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ld.q r2, 23*8, r52
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ld.q r2, 24*8, r53
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ld.q r2, 24*8, r53
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ld.q r2, 25*8, r54
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ld.q r2, 25*8, r54
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ld.q r2, 26*8, r55
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ld.q r2, 26*8, r55
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ld.q r2, 27*8, r56
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ld.q r2, 27*8, r56
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ld.q r2, 28*8, r57
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ld.q r2, 28*8, r57
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ld.q r2, 29*8, r58
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ld.q r2, 29*8, r58
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ld.q r2, 30*8, r59
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ld.q r2, 30*8, r59
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ld.q r2, 31*8, r5
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ld.q r2, 31*8, r5
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ld.q r2, 32*8, r6
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ld.q r2, 32*8, r6
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ld.q r2, 33*8, r7
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ld.q r2, 33*8, r7
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ptabs r5, tr5
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ptabs r5, tr5
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ptabs r6, tr6
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ptabs r6, tr6
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ptabs r7, tr7
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ptabs r7, tr7
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#if ! __SH4_NOFPU__
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#if ! __SH4_NOFPU__
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fld.d r2, 34*8, dr12
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fld.d r2, 34*8, dr12
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fld.d r2, 35*8, dr14
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fld.d r2, 35*8, dr14
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fld.d r2, 36*8, dr36
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fld.d r2, 36*8, dr36
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fld.d r2, 37*8, dr38
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fld.d r2, 37*8, dr38
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fld.d r2, 38*8, dr40
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fld.d r2, 38*8, dr40
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fld.d r2, 39*8, dr42
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fld.d r2, 39*8, dr42
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fld.d r2, 40*8, dr44
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fld.d r2, 40*8, dr44
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fld.d r2, 41*8, dr46
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fld.d r2, 41*8, dr46
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fld.d r2, 42*8, dr48
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fld.d r2, 42*8, dr48
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fld.d r2, 43*8, dr50
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fld.d r2, 43*8, dr50
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fld.d r2, 44*8, dr52
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fld.d r2, 44*8, dr52
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fld.d r2, 45*8, dr54
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fld.d r2, 45*8, dr54
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fld.d r2, 46*8, dr56
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fld.d r2, 46*8, dr56
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fld.d r2, 47*8, dr58
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fld.d r2, 47*8, dr58
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fld.d r2, 48*8, dr60
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fld.d r2, 48*8, dr60
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fld.d r2, 49*8, dr62
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fld.d r2, 49*8, dr62
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#endif
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#endif
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movi 1, r2
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movi 1, r2
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cmvne r3, r3, r2
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cmvne r3, r3, r2
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blink tr0, r63
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blink tr0, r63
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#else
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#else
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mov.l @r4+,r8
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mov.l @r4+,r8
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mov.l @r4+,r9
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mov.l @r4+,r9
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mov.l @r4+,r10
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mov.l @r4+,r10
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mov.l @r4+,r11
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mov.l @r4+,r11
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mov.l @r4+,r12
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mov.l @r4+,r12
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mov.l @r4+,r13
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mov.l @r4+,r13
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mov.l @r4+,r14
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mov.l @r4+,r14
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mov.l @r4+,r15
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mov.l @r4+,r15
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#if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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#if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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fmov.s @r4+,fr12 ! call saved floating point registers
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fmov.s @r4+,fr12 ! call saved floating point registers
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fmov.s @r4+,fr13
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fmov.s @r4+,fr13
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fmov.s @r4+,fr14
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fmov.s @r4+,fr14
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fmov.s @r4+,fr15
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fmov.s @r4+,fr15
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#endif
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#endif
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lds.l @r4+,pr
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lds.l @r4+,pr
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mov r5,r0
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mov r5,r0
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tst r0,r0
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tst r0,r0
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bf retr4
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bf retr4
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movt r0
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movt r0
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retr4: rts
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retr4: rts
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nop
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nop
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#endif /* __SH5__ */
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#endif /* __SH5__ */
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