/*
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/*
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(C) Copyright IBM Corp. 2008
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(C) Copyright IBM Corp. 2008
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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documentation and/or other materials provided with the distribution.
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* Neither the name of IBM nor the names of its contributors may be
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* Neither the name of IBM nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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used to endorse or promote products derived from this software without
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specific prior written permission.
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/* First-level interrupt handler. */
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/* First-level interrupt handler. */
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/* The following two convenience macros assist in the coding of the
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/* The following two convenience macros assist in the coding of the
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saving and restoring the volatile register starting from register
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saving and restoring the volatile register starting from register
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2 up to register 79.
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2 up to register 79.
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saveregs first, last Saves registers from first to the last.
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saveregs first, last Saves registers from first to the last.
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restoreregs first, last Restores registers from last down to first.
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restoreregs first, last Restores registers from last down to first.
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Note: first must be less than or equal to last. */
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Note: first must be less than or equal to last. */
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.macro saveregs first, last
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.macro saveregs first, last
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stqd $\first, -(STACK_SKIP+\first)*16($SP)
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stqd $\first, -(STACK_SKIP+\first)*16($SP)
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.if \last-\first
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.if \last-\first
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saveregs "(\first+1)",\last
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saveregs "(\first+1)",\last
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.endif
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.endif
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.endm
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.endm
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.macro restoreregs first, last
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.macro restoreregs first, last
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lqd $\last, (82-\last)*16($SP)
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lqd $\last, (82-\last)*16($SP)
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.if \last-\first
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.if \last-\first
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restoreregs \first,"(\last-1)"
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restoreregs \first,"(\last-1)"
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.endif
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.endif
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.endm
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.endm
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.section .interrupt,"ax"
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.section .interrupt,"ax"
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.align 3
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.align 3
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.type spu_flih, @function
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.type spu_flih, @function
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spu_flih:
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spu_flih:
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/* Adjust the stack pointer to skip the maximum register save area
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/* Adjust the stack pointer to skip the maximum register save area
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(STACK_SKIP quadword registers) in case an interrupt occurred while
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(STACK_SKIP quadword registers) in case an interrupt occurred while
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executing a leaf function that used the stack area without actually
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executing a leaf function that used the stack area without actually
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allocating its own stack frame. */
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allocating its own stack frame. */
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.set STACK_SKIP, 125
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.set STACK_SKIP, 125
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/* Save the current link register on a new stack frame for the
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/* Save the current link register on a new stack frame for the
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normal spu_flih() version of this file. */
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normal spu_flih() version of this file. */
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stqd $0, -(STACK_SKIP+80)*16($SP)
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stqd $0, -(STACK_SKIP+80)*16($SP)
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stqd $SP, -(STACK_SKIP+82)*16($SP) /* Save back chain pointer. */
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stqd $SP, -(STACK_SKIP+82)*16($SP) /* Save back chain pointer. */
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saveregs 2, 39
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saveregs 2, 39
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il $2, -(STACK_SKIP+82)*16 /* Stack frame size. */
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il $2, -(STACK_SKIP+82)*16 /* Stack frame size. */
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rdch $3, $SPU_RdEventStat /* Read event status. */
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rdch $3, $SPU_RdEventStat /* Read event status. */
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rdch $6, $SPU_RdEventMask /* Read event mask. */
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rdch $6, $SPU_RdEventMask /* Read event mask. */
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hbrp /* Open a slot for instruction prefetch. */
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hbrp /* Open a slot for instruction prefetch. */
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saveregs 40,59
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saveregs 40,59
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clz $4, $3 /* Get first slih index. */
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clz $4, $3 /* Get first slih index. */
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stqd $6, -(STACK_SKIP+1)*16($SP) /* Save event mask on stack. */
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stqd $6, -(STACK_SKIP+1)*16($SP) /* Save event mask on stack. */
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saveregs 60, 67
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saveregs 60, 67
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/* Do not disable/ack the decrementer event here.
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/* Do not disable/ack the decrementer event here.
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The timer library manages this and expects it
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The timer library manages this and expects it
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to be enabled upon entry to the SLIH. */
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to be enabled upon entry to the SLIH. */
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il $7, 0x20
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il $7, 0x20
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andc $5, $3, $7
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andc $5, $3, $7
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andc $7, $6, $5 /* Clear event bits. */
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andc $7, $6, $5 /* Clear event bits. */
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saveregs 68, 69
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saveregs 68, 69
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wrch $SPU_WrEventAck, $3 /* Ack events(s) - include decrementer event. */
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wrch $SPU_WrEventAck, $3 /* Ack events(s) - include decrementer event. */
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wrch $SPU_WrEventMask, $7 /* Disable event(s) - exclude decrementer event. */
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wrch $SPU_WrEventMask, $7 /* Disable event(s) - exclude decrementer event. */
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saveregs 70, 79
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saveregs 70, 79
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a $SP, $SP, $2 /* Instantiate flih stack frame. */
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a $SP, $SP, $2 /* Instantiate flih stack frame. */
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next_event:
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next_event:
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/* Fetch and dispatch the event handler for the first non-zero event. The
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/* Fetch and dispatch the event handler for the first non-zero event. The
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dispatch handler is indexed into the __spu_slih_handlers array using the
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dispatch handler is indexed into the __spu_slih_handlers array using the
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count of zero off the event status as an index. */
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count of zero off the event status as an index. */
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ila $5, __spu_slih_handlers /* Slih array offset. */
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ila $5, __spu_slih_handlers /* Slih array offset. */
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shli $4, $4, 2 /* Slih entry offset. */
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shli $4, $4, 2 /* Slih entry offset. */
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lqx $5, $4, $5 /* Load slih address. */
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lqx $5, $4, $5 /* Load slih address. */
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rotqby $5, $5, $4 /* Rotate to word 0. */
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rotqby $5, $5, $4 /* Rotate to word 0. */
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bisl $0, $5 /* Branch to slih. */
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bisl $0, $5 /* Branch to slih. */
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clz $4, $3 /* Get next slih index. */
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clz $4, $3 /* Get next slih index. */
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brnz $3, next_event
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brnz $3, next_event
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lqd $2, 81*16($SP) /* Read event mask from stack. */
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lqd $2, 81*16($SP) /* Read event mask from stack. */
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restoreregs 40, 79
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restoreregs 40, 79
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wrch $SPU_WrEventMask, $2 /* Restore event mask. */
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wrch $SPU_WrEventMask, $2 /* Restore event mask. */
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hbrp /* Open a slot for instruction pre-fetch. */
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hbrp /* Open a slot for instruction pre-fetch. */
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restoreregs 2, 39
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restoreregs 2, 39
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/* Restore the link register from the new stack frame for the
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/* Restore the link register from the new stack frame for the
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normal spu_flih() version of this file. */
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normal spu_flih() version of this file. */
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lqd $0, 2*16($SP)
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lqd $0, 2*16($SP)
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lqd $SP, 0*16($SP) /* restore stack pointer from back chain ptr. */
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lqd $SP, 0*16($SP) /* restore stack pointer from back chain ptr. */
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irete /* Return from interrupt and re-enable interrupts. */
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irete /* Return from interrupt and re-enable interrupts. */
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.size spu_flih, .-spu_flih
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.size spu_flih, .-spu_flih
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/* spu_slih_handlers[]
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/* spu_slih_handlers[]
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Here we initialize 33 default event handlers. The first entry in this array
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Here we initialize 33 default event handlers. The first entry in this array
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corresponds to the event handler for the event associated with bit 0 of
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corresponds to the event handler for the event associated with bit 0 of
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Channel 0 (External Event Status). The 32nd entry in this array corresponds
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Channel 0 (External Event Status). The 32nd entry in this array corresponds
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to bit 31 of Channel 0 (DMA Tag Status Update Event). The 33rd entry in
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to bit 31 of Channel 0 (DMA Tag Status Update Event). The 33rd entry in
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this array is a special case entry to handle "phantom events" which occur
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this array is a special case entry to handle "phantom events" which occur
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when the channel count for Channel 0 is 1, causing an asynchronous SPU
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when the channel count for Channel 0 is 1, causing an asynchronous SPU
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interrupt, but the value returned for a read of Channel 0 is 0. The index
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interrupt, but the value returned for a read of Channel 0 is 0. The index
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calculated into this array by spu_flih() for this case is 32, hence the
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calculated into this array by spu_flih() for this case is 32, hence the
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33rd entry. */
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33rd entry. */
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.data
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.data
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.align 4
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.align 4
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.extern __spu_default_slih
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.extern __spu_default_slih
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.global __spu_slih_handlers
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.global __spu_slih_handlers
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.type __spu_slih_handlers, @object
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.type __spu_slih_handlers, @object
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__spu_slih_handlers:
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__spu_slih_handlers:
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.rept 33
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.rept 33
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.long __spu_default_slih
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.long __spu_default_slih
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.endr
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.endr
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.size __spu_slih_handlers, .-__spu_slih_handlers
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.size __spu_slih_handlers, .-__spu_slih_handlers
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