/*
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/*
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(C) Copyright 2006, 2007
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(C) Copyright 2006, 2007
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International Business Machines Corporation,
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International Business Machines Corporation,
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Sony Computer Entertainment, Incorporated,
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Sony Computer Entertainment, Incorporated,
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Toshiba Corporation,
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Toshiba Corporation,
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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documentation and/or other materials provided with the distribution.
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* Neither the names of the copyright holders nor the names of their
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* Neither the names of the copyright holders nor the names of their
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contributors may be used to endorse or promote products derived from this
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contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#ifndef _SYS_FENV_H
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#ifndef _SYS_FENV_H
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#define _SYS_FENV_H
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#define _SYS_FENV_H
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/*
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/*
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* The exception macros are such that the functions to pack/unpack them
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* The exception macros are such that the functions to pack/unpack them
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* will map a 32 bit fenv_t from/to the 128 bit fpscr.
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* will map a 32 bit fenv_t from/to the 128 bit fpscr.
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*
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*
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* Suffixes:
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* Suffixes:
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* _SNGL: single precision
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* _SNGL: single precision
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* _DBL: double precision
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* _DBL: double precision
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* _N: element number, no suffix for element 0.
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* _N: element number, no suffix for element 0.
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*/
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*/
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#define FE_OVERFLOW_SNGL 0x08000000
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#define FE_OVERFLOW_SNGL 0x08000000
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#define FE_UNDERFLOW_SNGL 0x04000000
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#define FE_UNDERFLOW_SNGL 0x04000000
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#define FE_DIFF_SNGL 0x02000000
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#define FE_DIFF_SNGL 0x02000000
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#define FE_DIVBYZERO_SNGL 0x00000040
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#define FE_DIVBYZERO_SNGL 0x00000040
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#define FE_OVERFLOW_SNGL_1 0x00040000
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#define FE_OVERFLOW_SNGL_1 0x00040000
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#define FE_UNDERFLOW_SNGL_1 0x00020000
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#define FE_UNDERFLOW_SNGL_1 0x00020000
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#define FE_DIFF_SNGL_1 0x00010000
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#define FE_DIFF_SNGL_1 0x00010000
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#define FE_DIVBYZERO_SNGL_1 0x00000020
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#define FE_DIVBYZERO_SNGL_1 0x00000020
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#define FE_OVERFLOW_SNGL_2 0x00000200
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#define FE_OVERFLOW_SNGL_2 0x00000200
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#define FE_UNDERFLOW_SNGL_2 0x00000100
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#define FE_UNDERFLOW_SNGL_2 0x00000100
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#define FE_DIFF_SNGL_2 0x00000080
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#define FE_DIFF_SNGL_2 0x00000080
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#define FE_DIVBYZERO_SNGL_2 0x00000010
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#define FE_DIVBYZERO_SNGL_2 0x00000010
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#define FE_OVERFLOW_SNGL_3 0x00000004
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#define FE_OVERFLOW_SNGL_3 0x00000004
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#define FE_UNDERFLOW_SNGL_3 0x00000002
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#define FE_UNDERFLOW_SNGL_3 0x00000002
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#define FE_DIFF_SNGL_3 0x00000001
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#define FE_DIFF_SNGL_3 0x00000001
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#define FE_DIVBYZERO_SNGL_3 0x00000008
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#define FE_DIVBYZERO_SNGL_3 0x00000008
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#define FE_ALL_EXCEPT_SNGL (FE_OVERFLOW_SNGL | FE_UNDERFLOW_SNGL \
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#define FE_ALL_EXCEPT_SNGL (FE_OVERFLOW_SNGL | FE_UNDERFLOW_SNGL \
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| FE_DIFF_SNGL | FE_DIVBYZERO_SNGL)
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| FE_DIFF_SNGL | FE_DIVBYZERO_SNGL)
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#define FE_ALL_EXCEPT_SNGL_1 (FE_OVERFLOW_SNGL_1 | FE_UNDERFLOW_SNGL_1 \
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#define FE_ALL_EXCEPT_SNGL_1 (FE_OVERFLOW_SNGL_1 | FE_UNDERFLOW_SNGL_1 \
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| FE_DIFF_SNGL_1 | FE_DIVBYZERO_SNGL_1)
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| FE_DIFF_SNGL_1 | FE_DIVBYZERO_SNGL_1)
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#define FE_ALL_EXCEPT_SNGL_2 (FE_OVERFLOW_SNGL_2 | FE_UNDERFLOW_SNGL_2 \
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#define FE_ALL_EXCEPT_SNGL_2 (FE_OVERFLOW_SNGL_2 | FE_UNDERFLOW_SNGL_2 \
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| FE_DIFF_SNGL_2 | FE_DIVBYZERO_SNGL_2)
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| FE_DIFF_SNGL_2 | FE_DIVBYZERO_SNGL_2)
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#define FE_ALL_EXCEPT_SNGL_3 (FE_OVERFLOW_SNGL_3 | FE_UNDERFLOW_SNGL_3 \
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#define FE_ALL_EXCEPT_SNGL_3 (FE_OVERFLOW_SNGL_3 | FE_UNDERFLOW_SNGL_3 \
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| FE_DIFF_SNGL_3 | FE_DIVBYZERO_SNGL_3)
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| FE_DIFF_SNGL_3 | FE_DIVBYZERO_SNGL_3)
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#define FE_OVERFLOW_DBL 0x01000000
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#define FE_OVERFLOW_DBL 0x01000000
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#define FE_UNDERFLOW_DBL 0x00800000
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#define FE_UNDERFLOW_DBL 0x00800000
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#define FE_INEXACT_DBL 0x00400000
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#define FE_INEXACT_DBL 0x00400000
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#define FE_INVALID_DBL 0x00200000
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#define FE_INVALID_DBL 0x00200000
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#define FE_NC_NAN_DBL 0x00100000
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#define FE_NC_NAN_DBL 0x00100000
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#define FE_NC_DENORM_DBL 0x00080000
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#define FE_NC_DENORM_DBL 0x00080000
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#define FE_OVERFLOW_DBL_1 0x00008000
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#define FE_OVERFLOW_DBL_1 0x00008000
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#define FE_UNDERFLOW_DBL_1 0x00004000
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#define FE_UNDERFLOW_DBL_1 0x00004000
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#define FE_INEXACT_DBL_1 0x00002000
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#define FE_INEXACT_DBL_1 0x00002000
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#define FE_INVALID_DBL_1 0x00001000
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#define FE_INVALID_DBL_1 0x00001000
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#define FE_NC_NAN_DBL_1 0x00000800
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#define FE_NC_NAN_DBL_1 0x00000800
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#define FE_NC_DENORM_DBL_1 0x00000400
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#define FE_NC_DENORM_DBL_1 0x00000400
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#define FE_ALL_EXCEPT_DBL (FE_OVERFLOW_DBL | FE_UNDERFLOW_DBL | \
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#define FE_ALL_EXCEPT_DBL (FE_OVERFLOW_DBL | FE_UNDERFLOW_DBL | \
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FE_INEXACT_DBL | FE_INVALID_DBL | \
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FE_INEXACT_DBL | FE_INVALID_DBL | \
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FE_NC_NAN_DBL | FE_NC_DENORM_DBL)
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FE_NC_NAN_DBL | FE_NC_DENORM_DBL)
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#define FE_ALL_EXCEPT_DBL_1 (FE_OVERFLOW_DBL_1 | FE_UNDERFLOW_DBL_1 | \
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#define FE_ALL_EXCEPT_DBL_1 (FE_OVERFLOW_DBL_1 | FE_UNDERFLOW_DBL_1 | \
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FE_INEXACT_DBL_1 | FE_INVALID_DBL_1 | \
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FE_INEXACT_DBL_1 | FE_INVALID_DBL_1 | \
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FE_NC_NAN_DBL_1 | FE_NC_DENORM_DBL_1)
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FE_NC_NAN_DBL_1 | FE_NC_DENORM_DBL_1)
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#define FE_ALL_EXCEPT (FE_ALL_EXCEPT_SNGL | FE_ALL_EXCEPT_SNGL_1 | \
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#define FE_ALL_EXCEPT (FE_ALL_EXCEPT_SNGL | FE_ALL_EXCEPT_SNGL_1 | \
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FE_ALL_EXCEPT_SNGL_2 | FE_ALL_EXCEPT_SNGL_3 | \
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FE_ALL_EXCEPT_SNGL_2 | FE_ALL_EXCEPT_SNGL_3 | \
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FE_ALL_EXCEPT_DBL | FE_ALL_EXCEPT_DBL_1)
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FE_ALL_EXCEPT_DBL | FE_ALL_EXCEPT_DBL_1)
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/*
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/*
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* Warning: some of these are single and some double precision only,
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* Warning: some of these are single and some double precision only,
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* because of the hardware implementation.
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* because of the hardware implementation.
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*/
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*/
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#define FE_DIVBYZERO (FE_DIVBYZERO_SNGL | FE_DIVBYZERO_SNGL_1 | \
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#define FE_DIVBYZERO (FE_DIVBYZERO_SNGL | FE_DIVBYZERO_SNGL_1 | \
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FE_DIVBYZERO_SNGL_2 | FE_DIVBYZERO_SNGL_3)
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FE_DIVBYZERO_SNGL_2 | FE_DIVBYZERO_SNGL_3)
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#define FE_INEXACT (FE_INEXACT_DBL | FE_INEXACT_DBL_1)
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#define FE_INEXACT (FE_INEXACT_DBL | FE_INEXACT_DBL_1)
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#define FE_INVALID (FE_INVALID_DBL | FE_INVALID_DBL_1)
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#define FE_INVALID (FE_INVALID_DBL | FE_INVALID_DBL_1)
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#define FE_NC_NAN (FE_NC_NAN_DBL | FE_NC_NAN_DBL_1)
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#define FE_NC_NAN (FE_NC_NAN_DBL | FE_NC_NAN_DBL_1)
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#define FE_NC_DENORM (FE_NC_DENORM_DBL | FE_NC_DENORM_DBL_1)
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#define FE_NC_DENORM (FE_NC_DENORM_DBL | FE_NC_DENORM_DBL_1)
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/*
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/*
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* __FE_ROUND_ELE_n values are set so that they can easily be used as a
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* __FE_ROUND_ELE_n values are set so that they can easily be used as a
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* mask when setting the fpscr. These tell us whether we are setting the
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* mask when setting the fpscr. These tell us whether we are setting the
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* round mode for a specific element (double precision floating point
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* round mode for a specific element (double precision floating point
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* only, so there are only two elements).
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* only, so there are only two elements).
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*/
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*/
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#define __FE_ROUND_ELE_0 0xc00
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#define __FE_ROUND_ELE_0 0xc00
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#define __FE_ROUND_ELE_1 0x300
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#define __FE_ROUND_ELE_1 0x300
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/*
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/*
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* The following map directly to round values in the fpscr.
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* The following map directly to round values in the fpscr.
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*/
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*/
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#define __FE_SPU_TONEAREST 0
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#define __FE_SPU_TONEAREST 0
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#define __FE_SPU_TOWARDZERO 1
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#define __FE_SPU_TOWARDZERO 1
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#define __FE_SPU_UPWARD 2
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#define __FE_SPU_UPWARD 2
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#define __FE_SPU_DOWNWARD 3
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#define __FE_SPU_DOWNWARD 3
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#define FE_TONEAREST (__FE_ROUND_ELE_0 | (__FE_SPU_TONEAREST << 2))
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#define FE_TONEAREST (__FE_ROUND_ELE_0 | (__FE_SPU_TONEAREST << 2))
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#define FE_TOWARDZERO (__FE_ROUND_ELE_0 | (__FE_SPU_TOWARDZERO << 2))
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#define FE_TOWARDZERO (__FE_ROUND_ELE_0 | (__FE_SPU_TOWARDZERO << 2))
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#define FE_UPWARD (__FE_ROUND_ELE_0 | (__FE_SPU_UPWARD << 2))
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#define FE_UPWARD (__FE_ROUND_ELE_0 | (__FE_SPU_UPWARD << 2))
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#define FE_DOWNWARD (__FE_ROUND_ELE_0 | (__FE_SPU_DOWNWARD << 2))
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#define FE_DOWNWARD (__FE_ROUND_ELE_0 | (__FE_SPU_DOWNWARD << 2))
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#define FE_TONEAREST_1 (__FE_ROUND_ELE_1 | __FE_SPU_TONEAREST)
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#define FE_TONEAREST_1 (__FE_ROUND_ELE_1 | __FE_SPU_TONEAREST)
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#define FE_TOWARDZERO_1 (__FE_ROUND_ELE_1 | __FE_SPU_TOWARDZERO)
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#define FE_TOWARDZERO_1 (__FE_ROUND_ELE_1 | __FE_SPU_TOWARDZERO)
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#define FE_UPWARD_1 (__FE_ROUND_ELE_1 | __FE_SPU_UPWARD)
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#define FE_UPWARD_1 (__FE_ROUND_ELE_1 | __FE_SPU_UPWARD)
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#define FE_DOWNWARD_1 (__FE_ROUND_ELE_1 | __FE_SPU_DOWNWARD)
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#define FE_DOWNWARD_1 (__FE_ROUND_ELE_1 | __FE_SPU_DOWNWARD)
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typedef unsigned int fexcept_t;
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typedef unsigned int fexcept_t;
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typedef unsigned int fenv_t;
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typedef unsigned int fenv_t;
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extern const fenv_t __fe_dfl_env;
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extern const fenv_t __fe_dfl_env;
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#define FE_DFL_ENV (&__fe_dfl_env)
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#define FE_DFL_ENV (&__fe_dfl_env)
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#endif /* fenv.h */
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#endif /* fenv.h */
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