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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [newlib-1.18.0/] [newlib-1.18.0-or32-1.0rc1/] [newlib/] [libc/] [machine/] [xscale/] [strcpy.c] - Diff between revs 207 and 345

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Rev 207 Rev 345
#if defined __thumb__
#if defined __thumb__
 
 
#include "../../string/strcpy.c"
#include "../../string/strcpy.c"
 
 
#else
#else
 
 
#include <string.h>
#include <string.h>
#include "xscale.h"
#include "xscale.h"
 
 
char *
char *
strcpy (char *dest, const char *src)
strcpy (char *dest, const char *src)
{
{
  char *dest0 = dest;
  char *dest0 = dest;
 
 
  asm (PRELOADSTR ("%0") : : "r" (src));
  asm (PRELOADSTR ("%0") : : "r" (src));
 
 
#ifndef __OPTIMIZE_SIZE__
#ifndef __OPTIMIZE_SIZE__
  if (((long)src & 3) == ((long)dest & 3))
  if (((long)src & 3) == ((long)dest & 3))
    {
    {
      /* Skip unaligned part.  */
      /* Skip unaligned part.  */
      while ((long)src & 3)
      while ((long)src & 3)
        {
        {
          if (! (*dest++ = *src++))
          if (! (*dest++ = *src++))
            return dest0;
            return dest0;
        }
        }
 
 
  /* Load two constants:
  /* Load two constants:
     R4 = 0xfefefeff [ == ~(0x80808080 << 1) ]
     R4 = 0xfefefeff [ == ~(0x80808080 << 1) ]
     R5 = 0x80808080  */
     R5 = 0x80808080  */
 
 
  asm ("mov     r5, #0x80\n\
  asm ("mov     r5, #0x80\n\
        ldr     r1, [%1, #0]\n\
        ldr     r1, [%1, #0]\n\
        add     r5, r5, #0x8000\n\
        add     r5, r5, #0x8000\n\
        add     r5, r5, r5, lsl #16\n\
        add     r5, r5, r5, lsl #16\n\
        mvn     r4, r5, lsl #1\n\
        mvn     r4, r5, lsl #1\n\
\n\
\n\
        add     r3, r1, r5\n\
        add     r3, r1, r5\n\
        bic     r3, r3, r1\n\
        bic     r3, r3, r1\n\
        ands    r2, r3, r4\n\
        ands    r2, r3, r4\n\
        bne     1f\n\
        bne     1f\n\
0:\n\
0:\n\
        ldr     r3, [%1, #0]\n\
        ldr     r3, [%1, #0]\n\
        ldr     r1, [%1, #4]!\n\
        ldr     r1, [%1, #4]!\n\
"       PRELOADSTR("%1") "\n\
"       PRELOADSTR("%1") "\n\
        str     r3, [%0], #4\n\
        str     r3, [%0], #4\n\
        add     r2, r1, r4\n\
        add     r2, r1, r4\n\
        bic     r2, r2, r1\n\
        bic     r2, r2, r1\n\
        ands    r3, r2, r5\n\
        ands    r3, r2, r5\n\
        beq     0b\n\
        beq     0b\n\
1:"
1:"
       : "=&r" (dest), "=&r" (src)
       : "=&r" (dest), "=&r" (src)
       : "0" (dest), "1" (src)
       : "0" (dest), "1" (src)
       : "r1", "r2", "r3", "r4", "r5", "memory", "cc");
       : "r1", "r2", "r3", "r4", "r5", "memory", "cc");
    }
    }
#endif
#endif
 
 
  while (*dest++ = *src++)
  while (*dest++ = *src++)
    asm (PRELOADSTR ("%0") : : "r" (src));
    asm (PRELOADSTR ("%0") : : "r" (src));
  return dest0;
  return dest0;
}
}
 
 
#endif
#endif
 
 

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