//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// OR1200's DC FSM ////
|
//// OR1200's DC FSM ////
|
//// ////
|
//// ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// http://www.opencores.org/cores/or1k/ ////
|
//// http://www.opencores.org/cores/or1k/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Data cache state machine ////
|
//// Data cache state machine ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - make it smaller and faster ////
|
//// - make it smaller and faster ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
// Revision 1.8 2004/04/05 08:29:57 lampret
|
// Revision 1.8 2004/04/05 08:29:57 lampret
|
// Merged branch_qmem into main tree.
|
// Merged branch_qmem into main tree.
|
//
|
//
|
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
|
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
|
// Added embedded memory QMEM.
|
// Added embedded memory QMEM.
|
//
|
//
|
// Revision 1.7 2002/03/29 15:16:55 lampret
|
// Revision 1.7 2002/03/29 15:16:55 lampret
|
// Some of the warnings fixed.
|
// Some of the warnings fixed.
|
//
|
//
|
// Revision 1.6 2002/03/28 19:10:40 lampret
|
// Revision 1.6 2002/03/28 19:10:40 lampret
|
// Optimized cache controller FSM.
|
// Optimized cache controller FSM.
|
//
|
//
|
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
|
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
|
// First import of the "new" XESS XSV environment.
|
// First import of the "new" XESS XSV environment.
|
//
|
//
|
//
|
//
|
// Revision 1.5 2002/02/11 04:33:17 lampret
|
// Revision 1.5 2002/02/11 04:33:17 lampret
|
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
|
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
|
//
|
//
|
// Revision 1.4 2002/02/01 19:56:54 lampret
|
// Revision 1.4 2002/02/01 19:56:54 lampret
|
// Fixed combinational loops.
|
// Fixed combinational loops.
|
//
|
//
|
// Revision 1.3 2002/01/28 01:15:59 lampret
|
// Revision 1.3 2002/01/28 01:15:59 lampret
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
//
|
//
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
//
|
//
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
//
|
//
|
// Revision 1.9 2001/10/21 17:57:16 lampret
|
// Revision 1.9 2001/10/21 17:57:16 lampret
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
//
|
//
|
// Revision 1.8 2001/10/19 23:28:46 lampret
|
// Revision 1.8 2001/10/19 23:28:46 lampret
|
// Fixed some synthesis warnings. Configured with caches and MMUs.
|
// Fixed some synthesis warnings. Configured with caches and MMUs.
|
//
|
//
|
// Revision 1.7 2001/10/14 13:12:09 lampret
|
// Revision 1.7 2001/10/14 13:12:09 lampret
|
// MP3 version.
|
// MP3 version.
|
//
|
//
|
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
|
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
|
// no message
|
// no message
|
//
|
//
|
// Revision 1.2 2001/08/09 13:39:33 lampret
|
// Revision 1.2 2001/08/09 13:39:33 lampret
|
// Major clean-up.
|
// Major clean-up.
|
//
|
//
|
// Revision 1.1 2001/07/20 00:46:03 lampret
|
// Revision 1.1 2001/07/20 00:46:03 lampret
|
// Development version of RTL. Libraries are missing.
|
// Development version of RTL. Libraries are missing.
|
//
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
|
|
`define OR1200_DCFSM_IDLE 3'd0
|
`define OR1200_DCFSM_IDLE 3'd0
|
`define OR1200_DCFSM_CLOAD 3'd1
|
`define OR1200_DCFSM_CLOAD 3'd1
|
`define OR1200_DCFSM_LREFILL3 3'd2
|
`define OR1200_DCFSM_LREFILL3 3'd2
|
`define OR1200_DCFSM_CSTORE 3'd3
|
`define OR1200_DCFSM_CSTORE 3'd3
|
`define OR1200_DCFSM_SREFILL4 3'd4
|
`define OR1200_DCFSM_SREFILL4 3'd4
|
|
|
//
|
//
|
// Data cache FSM for cache line of 16 bytes (4x singleword)
|
// Data cache FSM for cache line of 16 bytes (4x singleword)
|
//
|
//
|
|
|
module or1200_dc_fsm(
|
module or1200_dc_fsm(
|
// Clock and reset
|
// Clock and reset
|
clk, rst,
|
clk, rst,
|
|
|
// Internal i/f to top level DC
|
// Internal i/f to top level DC
|
dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
|
dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
|
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
|
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
|
dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
|
dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
|
burst, tag_we, dc_addr
|
burst, tag_we, dc_addr
|
);
|
);
|
|
|
//
|
//
|
// I/O
|
// I/O
|
//
|
//
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input dc_en;
|
input dc_en;
|
input dcqmem_cycstb_i;
|
input dcqmem_cycstb_i;
|
input dcqmem_ci_i;
|
input dcqmem_ci_i;
|
input dcqmem_we_i;
|
input dcqmem_we_i;
|
input [3:0] dcqmem_sel_i;
|
input [3:0] dcqmem_sel_i;
|
input tagcomp_miss;
|
input tagcomp_miss;
|
input biudata_valid;
|
input biudata_valid;
|
input biudata_error;
|
input biudata_error;
|
input [31:0] start_addr;
|
input [31:0] start_addr;
|
output [31:0] saved_addr;
|
output [31:0] saved_addr;
|
output [3:0] dcram_we;
|
output [3:0] dcram_we;
|
output biu_read;
|
output biu_read;
|
output biu_write;
|
output biu_write;
|
output first_hit_ack;
|
output first_hit_ack;
|
output first_miss_ack;
|
output first_miss_ack;
|
output first_miss_err;
|
output first_miss_err;
|
output burst;
|
output burst;
|
output tag_we;
|
output tag_we;
|
output [31:0] dc_addr;
|
output [31:0] dc_addr;
|
|
|
//
|
//
|
// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
reg [31:0] saved_addr_r;
|
reg [31:0] saved_addr_r;
|
reg [2:0] state;
|
reg [2:0] state;
|
reg [2:0] cnt;
|
reg [2:0] cnt;
|
reg hitmiss_eval;
|
reg hitmiss_eval;
|
reg store;
|
reg store;
|
reg load;
|
reg load;
|
reg cache_inhibit;
|
reg cache_inhibit;
|
wire first_store_hit_ack;
|
wire first_store_hit_ack;
|
|
|
//
|
//
|
// Generate of DCRAM write enables
|
// Generate of DCRAM write enables
|
//
|
//
|
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
|
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
|
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
|
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
|
|
|
//
|
//
|
// BIU read and write
|
// BIU read and write
|
//
|
//
|
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
|
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
|
assign biu_write = store;
|
assign biu_write = store;
|
|
|
assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
|
assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
|
assign saved_addr = saved_addr_r;
|
assign saved_addr = saved_addr_r;
|
|
|
//
|
//
|
// Assert for cache hit first word ready
|
// Assert for cache hit first word ready
|
// Assert for store cache hit first word ready
|
// Assert for store cache hit first word ready
|
// Assert for cache miss first word stored/loaded OK
|
// Assert for cache miss first word stored/loaded OK
|
// Assert for cache miss first word stored/loaded with an error
|
// Assert for cache miss first word stored/loaded with an error
|
//
|
//
|
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
|
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
|
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
|
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
|
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
|
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
|
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
|
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
|
|
|
//
|
//
|
// Assert burst when doing reload of complete cache line
|
// Assert burst when doing reload of complete cache line
|
//
|
//
|
assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
|
assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
|
| (state == `OR1200_DCFSM_LREFILL3)
|
| (state == `OR1200_DCFSM_LREFILL3)
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
| (state == `OR1200_DCFSM_SREFILL4)
|
| (state == `OR1200_DCFSM_SREFILL4)
|
`endif
|
`endif
|
;
|
;
|
|
|
//
|
//
|
// Main DC FSM
|
// Main DC FSM
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
saved_addr_r <= #1 32'b0;
|
saved_addr_r <= #1 32'b0;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cnt <= #1 3'b000;
|
cnt <= #1 3'b000;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else
|
else
|
case (state) // synopsys parallel_case
|
case (state) // synopsys parallel_case
|
`OR1200_DCFSM_IDLE :
|
`OR1200_DCFSM_IDLE :
|
if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin // store
|
if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin // store
|
state <= #1 `OR1200_DCFSM_CSTORE;
|
state <= #1 `OR1200_DCFSM_CSTORE;
|
saved_addr_r <= #1 start_addr;
|
saved_addr_r <= #1 start_addr;
|
hitmiss_eval <= #1 1'b1;
|
hitmiss_eval <= #1 1'b1;
|
store <= #1 1'b1;
|
store <= #1 1'b1;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (dc_en & dcqmem_cycstb_i) begin // load
|
else if (dc_en & dcqmem_cycstb_i) begin // load
|
state <= #1 `OR1200_DCFSM_CLOAD;
|
state <= #1 `OR1200_DCFSM_CLOAD;
|
saved_addr_r <= #1 start_addr;
|
saved_addr_r <= #1 start_addr;
|
hitmiss_eval <= #1 1'b1;
|
hitmiss_eval <= #1 1'b1;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
load <= #1 1'b1;
|
load <= #1 1'b1;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else begin // idle
|
else begin // idle
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
`OR1200_DCFSM_CLOAD: begin // load
|
`OR1200_DCFSM_CLOAD: begin // load
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
cache_inhibit <= #1 1'b1;
|
cache_inhibit <= #1 1'b1;
|
if (hitmiss_eval)
|
if (hitmiss_eval)
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
if ((hitmiss_eval & !dcqmem_cycstb_i) || // load aborted (usually caused by DMMU)
|
if ((hitmiss_eval & !dcqmem_cycstb_i) || // load aborted (usually caused by DMMU)
|
(biudata_error) || // load terminated with an error
|
(biudata_error) || // load terminated with an error
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // load from cache-inhibited area
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // load from cache-inhibited area
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
|
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
|
state <= #1 `OR1200_DCFSM_LREFILL3;
|
state <= #1 `OR1200_DCFSM_LREFILL3;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
cnt <= #1 `OR1200_DCLS-2;
|
cnt <= #1 `OR1200_DCLS-2;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (!tagcomp_miss & !dcqmem_ci_i) begin // load hit, finish immediately
|
else if (!tagcomp_miss & !dcqmem_ci_i) begin // load hit, finish immediately
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else // load in-progress
|
else // load in-progress
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
end
|
end
|
`OR1200_DCFSM_LREFILL3 : begin
|
`OR1200_DCFSM_LREFILL3 : begin
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 3'd1;
|
cnt <= #1 cnt - 3'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
end
|
end
|
else if (biudata_valid) begin // last load of line refill
|
else if (biudata_valid) begin // last load of line refill
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`OR1200_DCFSM_CSTORE: begin // store
|
`OR1200_DCFSM_CSTORE: begin // store
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
cache_inhibit <= #1 1'b1;
|
cache_inhibit <= #1 1'b1;
|
if (hitmiss_eval)
|
if (hitmiss_eval)
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
if ((hitmiss_eval & !dcqmem_cycstb_i) || // store aborted (usually caused by DMMU)
|
if ((hitmiss_eval & !dcqmem_cycstb_i) || // store aborted (usually caused by DMMU)
|
(biudata_error) || // store terminated with an error
|
(biudata_error) || // store terminated with an error
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // store to cache-inhibited area
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // store to cache-inhibited area
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and doq load refill
|
else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and doq load refill
|
state <= #1 `OR1200_DCFSM_SREFILL4;
|
state <= #1 `OR1200_DCFSM_SREFILL4;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
load <= #1 1'b1;
|
load <= #1 1'b1;
|
cnt <= #1 `OR1200_DCLS-1;
|
cnt <= #1 `OR1200_DCLS-1;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
`endif
|
`endif
|
else if (biudata_valid) begin // store hit, finish write-through
|
else if (biudata_valid) begin // store hit, finish write-through
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else // store write-through in-progress
|
else // store write-through in-progress
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
end
|
end
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
`OR1200_DCFSM_SREFILL4 : begin
|
`OR1200_DCFSM_SREFILL4 : begin
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 1'd1;
|
cnt <= #1 cnt - 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
end
|
end
|
else if (biudata_valid) begin // last load of line refill
|
else if (biudata_valid) begin // last load of line refill
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
default:
|
default:
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|