//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's register file read operands mux ////
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//// OR1200's register file read operands mux ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Mux for two register file read operands. ////
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//// Mux for two register file read operands. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.9 2001/11/12 01:45:40 lampret
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// Revision 1.9 2001/11/12 01:45:40 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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// no message
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//
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.1 2001/07/20 00:46:05 lampret
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// Revision 1.1 2001/07/20 00:46:05 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_operandmuxes(
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module or1200_operandmuxes(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Internal i/f
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// Internal i/f
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id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
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id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
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simm, sel_a, sel_b, operand_a, operand_b, muxed_b
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simm, sel_a, sel_b, operand_a, operand_b, muxed_b
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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//
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//
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
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input ex_freeze;
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input [width-1:0] rf_dataa;
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input [width-1:0] rf_dataa;
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input [width-1:0] rf_datab;
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input [width-1:0] rf_datab;
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input [width-1:0] ex_forw;
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input [width-1:0] ex_forw;
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input [width-1:0] wb_forw;
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input [width-1:0] wb_forw;
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input [width-1:0] simm;
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input [width-1:0] simm;
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input [`OR1200_SEL_WIDTH-1:0] sel_a;
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input [`OR1200_SEL_WIDTH-1:0] sel_a;
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input [`OR1200_SEL_WIDTH-1:0] sel_b;
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input [`OR1200_SEL_WIDTH-1:0] sel_b;
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output [width-1:0] operand_a;
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output [width-1:0] operand_a;
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output [width-1:0] operand_b;
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output [width-1:0] operand_b;
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output [width-1:0] muxed_b;
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output [width-1:0] muxed_b;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [width-1:0] operand_a;
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reg [width-1:0] operand_a;
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reg [width-1:0] operand_b;
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reg [width-1:0] operand_b;
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reg [width-1:0] muxed_a;
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reg [width-1:0] muxed_a;
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reg [width-1:0] muxed_b;
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reg [width-1:0] muxed_b;
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reg saved_a;
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reg saved_a;
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reg saved_b;
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reg saved_b;
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//
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//
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// Operand A register
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// Operand A register
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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operand_a <= #1 32'd0;
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operand_a <= #1 32'd0;
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saved_a <= #1 1'b0;
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saved_a <= #1 1'b0;
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end else if (!ex_freeze && id_freeze && !saved_a) begin
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end else if (!ex_freeze && id_freeze && !saved_a) begin
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operand_a <= #1 muxed_a;
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operand_a <= #1 muxed_a;
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saved_a <= #1 1'b1;
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saved_a <= #1 1'b1;
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end else if (!ex_freeze && !saved_a) begin
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end else if (!ex_freeze && !saved_a) begin
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operand_a <= #1 muxed_a;
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operand_a <= #1 muxed_a;
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end else if (!ex_freeze && !id_freeze)
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end else if (!ex_freeze && !id_freeze)
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saved_a <= #1 1'b0;
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saved_a <= #1 1'b0;
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end
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end
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//
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//
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// Operand B register
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// Operand B register
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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operand_b <= #1 32'd0;
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operand_b <= #1 32'd0;
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saved_b <= #1 1'b0;
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saved_b <= #1 1'b0;
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end else if (!ex_freeze && id_freeze && !saved_b) begin
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end else if (!ex_freeze && id_freeze && !saved_b) begin
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operand_b <= #1 muxed_b;
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operand_b <= #1 muxed_b;
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saved_b <= #1 1'b1;
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saved_b <= #1 1'b1;
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end else if (!ex_freeze && !saved_b) begin
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end else if (!ex_freeze && !saved_b) begin
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operand_b <= #1 muxed_b;
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operand_b <= #1 muxed_b;
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end else if (!ex_freeze && !id_freeze)
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end else if (!ex_freeze && !id_freeze)
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saved_b <= #1 1'b0;
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saved_b <= #1 1'b0;
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end
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end
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//
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//
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// Forwarding logic for operand A register
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// Forwarding logic for operand A register
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//
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//
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always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
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always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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casex (sel_a) // synopsys parallel_case infer_mux
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casex (sel_a) // synopsys parallel_case infer_mux
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`else
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`else
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casex (sel_a) // synopsys parallel_case
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casex (sel_a) // synopsys parallel_case
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`endif
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`endif
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`OR1200_SEL_EX_FORW:
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`OR1200_SEL_EX_FORW:
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muxed_a = ex_forw;
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muxed_a = ex_forw;
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`OR1200_SEL_WB_FORW:
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`OR1200_SEL_WB_FORW:
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muxed_a = wb_forw;
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muxed_a = wb_forw;
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default:
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default:
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muxed_a = rf_dataa;
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muxed_a = rf_dataa;
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endcase
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endcase
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end
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end
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//
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//
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// Forwarding logic for operand B register
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// Forwarding logic for operand B register
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//
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//
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always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
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always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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casex (sel_b) // synopsys parallel_case infer_mux
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casex (sel_b) // synopsys parallel_case infer_mux
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`else
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`else
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casex (sel_b) // synopsys parallel_case
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casex (sel_b) // synopsys parallel_case
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`endif
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`endif
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`OR1200_SEL_IMM:
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`OR1200_SEL_IMM:
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muxed_b = simm;
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muxed_b = simm;
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`OR1200_SEL_EX_FORW:
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`OR1200_SEL_EX_FORW:
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muxed_b = ex_forw;
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muxed_b = ex_forw;
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`OR1200_SEL_WB_FORW:
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`OR1200_SEL_WB_FORW:
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muxed_b = wb_forw;
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muxed_b = wb_forw;
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default:
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default:
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muxed_b = rf_datab;
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muxed_b = rf_datab;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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