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OpenRISC 1200
IP Core
Specification
Author: Damjan Lampret
lampret@opencores.org
Rev. 0.7
Sep 6, 2001
Preliminary Draft
Revision History
Rev.DateAuthorDescription0.128/3/01Damjan LampretFirst Draft0.216/4/01Damjan LampretFirst time published0.329/4/01Damjan LampretAll chapters almost finished. Some bugs hidden waiting for an update. Awaiting feedback.0.416/5/01Damjan LampretSynchronization with OR1K Arch Manual0.524/5/01Damjan LampretFixed bugs0.628/5/01Damjan LampretChanged some SPR addresses.0.706/9/01Damjan LampretSimplified debug unit. Table Of Contents
TOC \o "2-2" \h \z \t "Headeing 1 Name,1" HYPERLINK \l "_Toc511161474" Introduction PAGEREF _Toc511161474 \h 7
HYPERLINK \l "_Toc511161475" OpenRISC Family PAGEREF _Toc511161475 \h 7
HYPERLINK \l "_Toc511161476" OpenRISC 1200 PAGEREF _Toc511161476 \h 8
HYPERLINK \l "_Toc511161477" Features PAGEREF _Toc511161477 \h 8
HYPERLINK \l "_Toc511161478" Architecture PAGEREF _Toc511161478 \h 9
HYPERLINK \l "_Toc511161479" CPU/DSP PAGEREF _Toc511161479 \h 10
HYPERLINK \l "_Toc511161480" Data Cache PAGEREF _Toc511161480 \h 13
HYPERLINK \l "_Toc511161481" Instruction Cache PAGEREF _Toc511161481 \h 15
HYPERLINK \l "_Toc511161482" Data MMU PAGEREF _Toc511161482 \h 17
HYPERLINK \l "_Toc511161483" Instruction MMU PAGEREF _Toc511161483 \h 19
HYPERLINK \l "_Toc511161484" Programmable Interrupt Controller PAGEREF _Toc511161484 \h 21
HYPERLINK \l "_Toc511161485" Tick Timer PAGEREF _Toc511161485 \h 21
HYPERLINK \l "_Toc511161486" Power Management Support PAGEREF _Toc511161486 \h 22
HYPERLINK \l "_Toc511161487" Debug unit PAGEREF _Toc511161487 \h 22
HYPERLINK \l "_Toc511161488" Clocks & Reset PAGEREF _Toc511161488 \h 23
HYPERLINK \l "_Toc511161489" WISHBONE Interfaces PAGEREF _Toc511161489 \h 23
HYPERLINK \l "_Toc511161490" Operation PAGEREF _Toc511161490 \h 25
HYPERLINK \l "_Toc511161491" Reset PAGEREF _Toc511161491 \h 25
HYPERLINK \l "_Toc511161492" CPU/DSP PAGEREF _Toc511161492 \h 25
HYPERLINK \l "_Toc511161493" Data Cache Operation PAGEREF _Toc511161493 \h 32
HYPERLINK \l "_Toc511161494" Instruction Cache Operation PAGEREF _Toc511161494 \h 35
HYPERLINK \l "_Toc511161495" Data MMU PAGEREF _Toc511161495 \h 37
HYPERLINK \l "_Toc511161496" Instruction MMU PAGEREF _Toc511161496 \h 41
HYPERLINK \l "_Toc511161497" Programmable Interrupt Controller PAGEREF _Toc511161497 \h 44
HYPERLINK \l "_Toc511161498" Tick Timer PAGEREF _Toc511161498 \h 45
HYPERLINK \l "_Toc511161499" Power Management PAGEREF _Toc511161499 \h 45
HYPERLINK \l "_Toc511161500" Debug Unit PAGEREF _Toc511161500 \h 46
HYPERLINK \l "_Toc511161501" Development Interface PAGEREF _Toc511161501 \h 47
HYPERLINK \l "_Toc511161502" Registers PAGEREF _Toc511161502 \h 50
HYPERLINK \l "_Toc511161503" Registers list PAGEREF _Toc511161503 \h 50
HYPERLINK \l "_Toc511161504" Register VR description PAGEREF _Toc511161504 \h 51
HYPERLINK \l "_Toc511161505" Register UPR description PAGEREF _Toc511161505 \h 52
HYPERLINK \l "_Toc511161506" Register CPUCFGR description PAGEREF _Toc511161506 \h 53
HYPERLINK \l "_Toc511161507" Register DMMUCFGR description PAGEREF _Toc511161507 \h 53
HYPERLINK \l "_Toc511161508" Register IMMUCFGR description PAGEREF _Toc511161508 \h 54
HYPERLINK \l "_Toc511161509" Register DCCFGR description PAGEREF _Toc511161509 \h 54
HYPERLINK \l "_Toc511161510" Register ICCFGR description PAGEREF _Toc511161510 \h 55
HYPERLINK \l "_Toc511161511" Register DCFGR description PAGEREF _Toc511161511 \h 56
HYPERLINK \l "_Toc511161512" IO ports PAGEREF _Toc511161512 \h 57
HYPERLINK \l "_Toc511161513" Instruction WISHBONE Master Interface PAGEREF _Toc511161513 \h 57
HYPERLINK \l "_Toc511161514" Data WISHBONE Master Interface PAGEREF _Toc511161514 \h 58
HYPERLINK \l "_Toc511161515" System Interface PAGEREF _Toc511161515 \h 59
HYPERLINK \l "_Toc511161516" Development Interface PAGEREF _Toc511161516 \h 59
HYPERLINK \l "_Toc511161517" Power Management Interface PAGEREF _Toc511161517 \h 59
HYPERLINK \l "_Toc511161518" Interrupt Interface PAGEREF _Toc511161518 \h 60
HYPERLINK \l "_Toc511161519" Core HW Configuration PAGEREF _Toc511161519 \h 61
Table Of Figures
TOC \h \z \c "Figure" HYPERLINK \l "_Toc511161520" Figure 1. Core's Architecture PAGEREF _Toc511161520 \h 9
HYPERLINK \l "_Toc511161521" Figure 2. CPU/DSP Block Diagram PAGEREF _Toc511161521 \h 10
HYPERLINK \l "_Toc511161522" Figure 3. Block Diagram of Debug Unit PAGEREF _Toc511161522 \h 23
HYPERLINK \l "_Toc511161523" Figure 4. Power-Up and Reset Sequence PAGEREF _Toc511161523 \h 25
HYPERLINK \l "_Toc511161524" Figure 5. Power-Up and Reset Sequence w/ Gated Clock PAGEREF _Toc511161524 \h 25
HYPERLINK \l "_Toc511161525" Figure 6. WISHBONE Write Cycle PAGEREF _Toc511161525 \h 33
HYPERLINK \l "_Toc511161526" Figure 7. WISHBONE Block Read Cycle PAGEREF _Toc511161526 \h 33
HYPERLINK \l "_Toc511161527" Figure 8. WISHBONE Block Read/Write Cycle PAGEREF _Toc511161527 \h 34
HYPERLINK \l "_Toc511161528" Figure 9. WISHBONE Block Read Cycle PAGEREF _Toc511161528 \h 36
HYPERLINK \l "_Toc511161529" Figure 10. 32-bit Address Translation Mechanism using Two-Level Page Table PAGEREF _Toc511161529 \h 38
HYPERLINK \l "_Toc511161530" Figure 11. 32-bit Address Translation Mechanism using Two-Level Page Table PAGEREF _Toc511161530 \h 42
HYPERLINK \l "_Toc511161531" Figure 12. Development Interface Cycles PAGEREF _Toc511161531 \h 48
HYPERLINK \l "_Toc511161532" Figure 13. Assertion of External Watchpoint Trigger PAGEREF _Toc511161532 \h 49
HYPERLINK \l "_Toc511161533" Figure 14. Cores Interfaces PAGEREF _Toc511161533 \h 57
Table Of Tables
TOC \h \z \c "Table" HYPERLINK \l "_Toc511161534" Table 1. Possible Data Cache Configurations of OR1200 PAGEREF _Toc511161534 \h 13
HYPERLINK \l "_Toc511161535" Table 2. Possible Instruction Cache Configurations of OR1200 PAGEREF _Toc511161535 \h 15
HYPERLINK \l "_Toc511161536" Table 3. Possible Data TLB Configurations of OR1200 PAGEREF _Toc511161536 \h 17
HYPERLINK \l "_Toc511161537" Table 4. Possible Instruction TLB Configurations of OR1200 PAGEREF _Toc511161537 \h 19
HYPERLINK \l "_Toc511161538" Table 5. Block Diagram of the Interrupt Controller PAGEREF _Toc511161538 \h 21
HYPERLINK \l "_Toc511161539" Table 6. Power Consumption PAGEREF _Toc511161539 \h 22
HYPERLINK \l "_Toc511161540" Table 7. List of 32-bit Implemented Instructions PAGEREF _Toc511161540 \h 29
HYPERLINK \l "_Toc511161541" Table 8. Execution Time of Integer Instructions PAGEREF _Toc511161541 \h 30
HYPERLINK \l "_Toc511161542" Table 9. List of Implemented Exceptions PAGEREF _Toc511161542 \h 32
HYPERLINK \l "_Toc511161543" Table 10. Protection Attributes for Load/Store Accesses PAGEREF _Toc511161543 \h 39
HYPERLINK \l "_Toc511161544" Table 11. Cached and uncached regions PAGEREF _Toc511161544 \h 40
HYPERLINK \l "_Toc511161545" Table 11. Protection Attributes for Instruction Fetch Accesses PAGEREF _Toc511161545 \h 43
HYPERLINK \l "_Toc511161546" Table 13. Cached and uncached regions PAGEREF _Toc511161546 \h 44
HYPERLINK \l "_Toc511161547" Table 12. Development Interface Operation Commands PAGEREF _Toc511161547 \h 47
HYPERLINK \l "_Toc511161548" Table 13. Status of the Load/Store Unit PAGEREF _Toc511161548 \h 48
HYPERLINK \l "_Toc511161549" Table 14. Status of the Instruction Unit PAGEREF _Toc511161549 \h 49
HYPERLINK \l "_Toc511161550" Table 15. List of All Registers PAGEREF _Toc511161550 \h 51
HYPERLINK \l "_Toc511161551" Table 16. VR Register PAGEREF _Toc511161551 \h 52
HYPERLINK \l "_Toc511161552" Table 17. UPR Register PAGEREF _Toc511161552 \h 52
HYPERLINK \l "_Toc511161553" Table 18. CPUCFGR Register PAGEREF _Toc511161553 \h 53
HYPERLINK \l "_Toc511161554" Table 19. DMMUCFGR Register PAGEREF _Toc511161554 \h 54
HYPERLINK \l "_Toc511161555" Table 20. IMMUCFGR Register PAGEREF _Toc511161555 \h 54
HYPERLINK \l "_Toc511161556" Table 21. DCCFGR Register PAGEREF _Toc511161556 \h 55
HYPERLINK \l "_Toc511161557" Table 22. ICCFGR Register PAGEREF _Toc511161557 \h 55
HYPERLINK \l "_Toc511161558" Table 23. DCFGR Register PAGEREF _Toc511161558 \h 56
HYPERLINK \l "_Toc511161559" Table 24. Instruction WISHBONE Master Interface Signals PAGEREF _Toc511161559 \h 58
HYPERLINK \l "_Toc511161560" Table 25. Data WISHBONE Master Interface Signals PAGEREF _Toc511161560 \h 58
HYPERLINK \l "_Toc511161561" Table 26. System Interface Signals PAGEREF _Toc511161561 \h 59
HYPERLINK \l "_Toc511161562" Table 27. Development Interface PAGEREF _Toc511161562 \h 59
HYPERLINK \l "_Toc511161563" Table 28. Power Management Interface PAGEREF _Toc511161563 \h 60
HYPERLINK \l "_Toc511161564" Table 29. Interrupt Interface PAGEREF _Toc511161564 \h 60
1
Introduction
Purpose of this document is to define specifications of the OpenRISC 1200 implementation. This specification defines all implementation specific variables that are not part of the general architecture specification. This includes type and size of data and instruction caches, type and size of data and instruction MMUs, details of all execution pipelines, implementation of exception unit, interrupt controller and other supplemental units.
This document does not cover general architecture topics like instruction set, memory addressing modes and other architectural definitions. See OpenRISC 1000 System Architecture Manual for more information about architecture.
OpenRISC Family
OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.
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All OpenRISC implementations, whose first digit in identification number is 1, belong to OpenRISC 1000 family. Second digit defines which features of OpenRISC 1000 architecture are implemented and in which way they are implemented. Last two digits define how an implementation is configured before it is used in a real application.
OpenRISC 1200
The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.
By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB.
Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.
When implemented in a typical 0.18u 6LM process it should provide over 300 dhrystone 2.1 MIPS at 300MHz and 300 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class. OR1200 in default configuration has about 1M transistors.
OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system.
Competitors include ARM10, ARC and Tensilica RISC processors.
Features
The following lists the main features of OR1200 IP core:
All major characteristics of the core can be set by the user
High performance of 300 Dhrystone 2.1 MIPS at 300 MHz using 0.18u process
High performance cache and MMU subsystems
WISHBONE SoC Interconnection Rev. B compliant interface
2
Architecture
REF _Ref511206923 \h Figure 1 below shows general architecture of OR1200 IP core. It consists of several building blocks:
CPU/DSP central block
Direct-mapped data cache
Direct-mapped instruction cache
Data MMU based on hash based DTLB
Instruction MMU based on hash based ITLB
Power management unit and power management interface
Tick timer
Debug unit and development interface
Interrupt controller and interrupt interface
Instruction and Data WISHBONE host interfaces
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Figure SEQ Figure \* ARABIC 1. Core's Architecture
CPU/DSP
CPU/DSP is a central part of the OR1200 RISC processor. REF _Ref511208730 \h \* MERGEFORMAT Figure 2 shows basic block diagram of the CPU/DSP.
OR1200 CPU/DSP implements only 32-bit part of the OpenRISC 1000 architecture. 64-bit part of the architecture as well as floating-point and vector operations are not implemented in OR1200.
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Figure SEQ Figure \* ARABIC 2. CPU/DSP Block Diagram
Instruction unit
The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them to available execution units, and maintains a state history to ensure a precise exception model and that operations finish in order. It also executes conditional branch and unconditional jump instructions.
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is available. The execution unit must discern whether source data is available and to ensure that no other instruction is targeting the same destination register.
Instruction unit handles only ORBIS32 instruction class. ORFPX32/64 and ORVDX64 instruction classes are not supported by current OR1200.
General-Purpose Registers
OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of register file to implement fast switching between working contexts, however this feature is not implemented in current OR1200 implementation.
OR1200 implements general-purpose register file as two synchronous dual-port memories with capacity of 32 words by 32 bits per word.
Load/Store Unit
The load/store unit (LSU) transfers all data between the GPRs and the CPU's internal bus. It is implemented as an independent execution unit so that stalls in memory subsystem only affect master pipeline if there is a data dependency.
The following are LSU's main features:
all load/store instruction implemented in hardware (atomic instructions included)
address entry buffer
pipelined operation
aligned accesses for fast memory access
When load and store instructions are issued, the LSU determines if all operands are available. These operands include the following:
address register operand
source data register operand (for store instructions)
destination data register operand (for load instructions)
Integer Execution Pipeline
The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions
Most integer instructions can execute in one cycle. For details about timing see table TBD.
MAC Unit
The MAC unit executes DSP MAC operations. MAC operations are 32x32 with 48-bit accumulator. MAC unit is fully pipelined and can accept new MAC operation in each new clock cycle.
System Unit
The system unit connects all other signals of the CPU/DSP that are not connected through instruction and data interfaces. It also implements all system special-purpose registers (e.g. supervisor register).
Exceptions
Core exceptions can be generated when an exception condition occurs. Exception sources in OR1200 include the following:
External interrupt request
Certain memory access condition
Internal errors, such as an attempt to execute unimplemented opcode
System call
Internal exception, such as breakpoint exceptions
Exception handling is transparent to user software and uses the same mechanism to handle all types of exceptions. When an exception is taken, control is transferred to an exception handler at an offset defined by for the type of exception encountered. Exceptions are handled in supervisor mode.
Data Cache
The default configuration of OR1200 data cache is 8-Kbyte, 1-way direct-mapped data cache, which allows rapid core access to data. However data cache can be configured according to the REF _Ref512098491 \h \* MERGEFORMAT Table 1.
Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table SEQ Table \* ARABIC 1. Possible Data Cache Configurations of OR1200
Features:
data cache is separate from instruction cache (Harvard architecture)
data cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
write-through operation
it can be disabled or invalidated by writing to cache special purpose registers
On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Data cache provides storage for cache tags and performs cache line replacement function.
Data cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The data cache supplies data to the GPRs by means of a 32-bit interface to the load/store unit. The LSU provides all logic required to calculate effective addresses, handles data alignment to and from the data cache, and provides sequencing for load and store operations. Write operations to the data cache can be performed on a byte, half-word or word basis.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag.
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Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.
Instruction Cache
The default configuration of OR1200 instruction cache is 8-Kbyte, 1-way direct mapped instruction cache, which allows rapid core access to instructions. However instruction cache can be configured according to the REF _Ref512099081 \h \* MERGEFORMAT
Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table 2.
Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table SEQ Table \* ARABIC 2. Possible Instruction Cache Configurations of OR1200
Features:
instruction cache is separate from data cache (Harvard architecture)
instruction cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
it can be disabled or invalidated by writing to cache special purpose registers
On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Instruction cache provides storage for cache tags and performs cache line replacement function.
Instruction cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The instruction cache supplies instructions to the instruction sequencer by means of a 32-bit interface to the instruction fetch subunit. The instruction fetch subunit provides all logic required to calculate effective addresses.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag.
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Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.
Data MMU
The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.
Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable SEQ Table \* ARABIC 4. Possible Data TLB Configurations of OR1200
Features:
data MMU is separate from instruction MMU
page size 8-Kbyte
comprehensive page protection scheme
direct mapped hash based translation lookaside buffer (DTLB) with the default of 1 way and the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
variable number DTLB entries with default of 64 per each way
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The MMU hardware supports two-level software tablewalk.
Instruction MMU
The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.
Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable SEQ Table \* ARABIC 5. Possible Instruction TLB Configurations of OR1200
Features:
instruction MMU is separate from data MMU
pages size 8-Kbyte
comprehensive page protection scheme
1 way direct-mapped hash based translation lookaside buffer (ITLB) with the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
Variable number of ITLB entries with default of 64 entries per way
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The MMU hardware supports two-level software tablewalk.
Programmable Interrupt Controller
The interrupt controller receives interrupts from external sources and forwards them as low or high priority interrupt exception to the CPU core.
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Table SEQ Table \* ARABIC 6. Block Diagram of the Interrupt Controller
Programmable interrupt controller has three special-purpose registers and 32 interrupt inputs. Interrupt input 0 and 1 are always enabled and connected to high and low priority interrupt input, respectively.
30 other interrupt inputs can be masked and assigned low or high priority through programming special-purpose registers.
Tick Timer
OR1200 implements tick timer facility. Basically this is a timer that is clocked by RISC clock and is used by the operating system to precisely measure time and schedule system tasks.
OR1200 precisely follow architectural definition of the tick timer facility:
Maximum timer count of 2^32 clock cycles
Maximum time period of 2^28 clock cycles between interrupts
Maskable tick timer interrupt
Single run, restartable or continues timer
Tick timer operates from independent clock source so that doze power management mode can be implemented.
Power Management Support
To optimize power consumption, the OR1200 provides low-power modes that can be used to dynamically activate and deactivate certain internal modules.
OR1200 has three major features to minimize power consumption:
Slow and Idle Modes (SW controlled clock freq reduction)
Doze and Sleep Modes (interrupt wake-up)
Power Minimization FeatureApprox Power Consumption ReductionSlow and Idle mode2x 10xDoze mode100xSleep mode200xDynamic clock gatingN/ATable SEQ Table \* ARABIC 7. Power Consumption
Slow down mode takes advantage of the low-power dividers in external clock generation circuitry to enable full functionality, but at a lower frequency so that a power consumption is reduced.
PMR[SDF] 4 bits are broadcasted on pm_clksd and external clock generation for the RISC should adapt RISC clock frequency according to the value on pm_clksd.
When software initiates the doze mode, software processing on the core suspends. The clocks to the RISC internal modules are disabled except to the tick timer. However any other on-chip blocks can continue to function as normal.
The OR1200 will leave doze mode and enter normal mode when a pending interrupt occurs.
In sleep mode, all OR1200 internal units are disabled and clocks gated. Optionally implementation may choose to lower the operating voltage of the OR1200 core.
The OR1200 should leave sleep mode and enter normal mode when a pending interrupt occurs.
Dynamic Clock gating (unit clock gating on clock by clock basis) is not supported by OR1200.
Debug unit
Debug unit assists software developers to debug their systems. It provides support only for basic debugging and does not have support for more advanced debug features of OpenRISC 1000 architecture such as watchpoints, breakpoints and program-flow control registers.
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Figure SEQ Figure \* ARABIC 3. Block Diagram of Debug Unit
Watchpoints and breakpoints are events triggered by program- or data-flow matching the conditions programmed in the debug registers. Breakpoints unlike watchpoints also suspend execution of the current program-flow and start breakpoint exception.
Clocks & Reset
The OR1200 core has several clock inputs. Clock input clk_cpu clocks CPU/DSP block and all other parts of the RISC that do not have separate clocks. Data cache is clocked by clk_dc, instruction cache is clocked by clk_ic, data MMU is clocked by clk_dmmu, instruction MMU is clocked by clk_immu and tick timer is clocked by clk_tt. All clocks must have the same phase and as low clock skew as possible.
OR1200 has asynchronous reset signal. Reset signal rst, when asserted high, immediately resets all flip-flops inside OR1200. When deasserted, OR1200 will start reset exception.
WISHBONE Interfaces
Two WISHBONE interfaces connect OR1200 core to external peripherals and external memory subsystem. They are WISHBONE SoC Interconnection specification Rev. B compliant. The implementation implements a 32-bit bus width and does not support other bus widths.
3
Operation
This section describes the operation of the OR1200 core. For operations that pertain to the architectural definitions, see OpenRISC 1000 System Architecture Manual.
Reset
OR1200 has one asynchronous reset signal that can be used by a soft and hard reset on a higher system hierarchy levels.
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Figure SEQ Figure \* ARABIC 4. Power-Up and Reset Sequence
REF _Ref513206810 \h Figure 4 shows how asynchronous reset is applied after powering up the OR1200 core. Reset is connected to asynchronous reset of almost all flip-flops inside RISC core. Special care must be taken to ensure hold and setup times of all flip-flops compared to main RISC clock.
If system implements gated clocks, then clock gating can be used to ensure proper reset timing.
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Figure SEQ Figure \* ARABIC 5. Power-Up and Reset Sequence w/ Gated Clock
CPU/DSP
CPU/DSP is implementation of the 32-bit part of the OpenRISC 1000 architecture and only a subset of all features is implemented.
Instructions
REF _Ref515320693 \h Table 8 shows all instructions implemented by OR1200.
Insn313131313126252525252120202020161515151511109877743330l.addopcode 0x38DABreservedopcode 0x0reservedopcode 0x0313029282726252423222120191817161514131211109876543210l.addcopcode 0x38DABreservedopcode 0x0reservedopcode 0x1313029282726252423222120191817161514131211109876543210l.addiopcode 0x27DAI313029282726252423222120191817161514131211109876543210l.andopcode 0x38DABreservedopcode 0x0reservedopcode 0x3313029282726252423222120191817161514131211109876543210l.andiopcode 0x29DAK313029282726252423222120191817161514131211109876543210l.bfopcode 0x4N313029282726252423222120191817161514131211109876543210l.bnfopcode 0x3N313029282726252423222120191817161514131211109876543210l.trapopcode 0x2100K313029282726252423222120191817161514131211109876543210l.jopcode 0x0N313029282726252423222120191817161514131211109876543210l.jalopcode 0x1N313029282726252423222120191817161514131211109876543210l.jalropcode 0x12ReservedBreserved313029282726252423222120191817161514131211109876543210l.jropcode 0x11ReservedBreserved313029282726252423222120191817161514131211109876543210l.lbsopcode 0x24DAI313029282726252423222120191817161514131211109876543210l.lbzopcode 0x23DAI313029282726252423222120191817161514131211109876543210l.lhsopcode 0x26DAI313029282726252423222120191817161514131211109876543210l.lhzopcode 0x25DAI313029282726252423222120191817161514131211109876543210l.lwsopcode 0x22DAI313029282726252423222120191817161514131211109876543210l.lwzopcode 0x21DAI313029282726252423222120191817161514131211109876543210l.mfspropcode 0x7DAK313029282726252423222120191817161514131211109876543210l.movhiopcode 0x6DReservedK313029282726252423222120191817161514131211109876543210l.mtspropcode 0x10KABK313029282726252423222120191817161514131211109876543210l.mulopcode 0x38DABreservedopcode 0x3reservedopcode 0x6313029282726252423222120191817161514131211109876543210l.muliopcode 0x2cDAI313029282726252423222120191817161514131211109876543210l.muluopcode 0x38DABreservedopcode 0x3reservedopcode 0xb313029282726252423222120191817161514131211109876543210l.nopopcode 0x15reserved313029282726252423222120191817161514131211109876543210l.oropcode 0x38DABreservedopcode 0x0reservedopcode 0x4313029282726252423222120191817161514131211109876543210l.oriopcode 0x2aDAK313029282726252423222120191817161514131211109876543210l.rfeopcode 0x9reserved313029282726252423222120191817161514131211109876543210l.roriopcode 0x2eDAreservedopcode 0x3L313029282726252423222120191817161514131211109876543210l.sbopcode 0x36IABI313029282726252423222120191817161514131211109876543210l.sfeqopcode 0x720ABreserved313029282726252423222120191817161514131211109876543210l.sfgesopcode 0x72bABreserved313029282726252423222120191817161514131211109876543210l.sfgeuopcode 0x723ABreserved313029282726252423222120191817161514131211109876543210l.sfgtsopcode 0x72aABreserved313029282726252423222120191817161514131211109876543210l.sfgtuopcode 0x722ABreserved313029282726252423222120191817161514131211109876543210l.sflesopcode 0x72dABreserved313029282726252423222120191817161514131211109876543210l.sfleuopcode 0x725ABreserved313029282726252423222120191817161514131211109876543210l.sfltsopcode 0x72cABreserved313029282726252423222120191817161514131211109876543210l.sfltuopcode 0x724ABreserved313029282726252423222120191817161514131211109876543210l.sfneopcode 0x721ABreserved313029282726252423222120191817161514131211109876543210l.shopcode 0x37IABI313029282726252423222120191817161514131211109876543210l.sllopcode 0x38DABreservedopcode 0x0reservedopcode 0x8313029282726252423222120191817161514131211109876543210l.slliopcode 0x2eDAreservedopcode 0x0L313029282726252423222120191817161514131211109876543210l.sraopcode 0x38DABreservedopcode 0x2reservedopcode 0x8313029282726252423222120191817161514131211109876543210l.sraiopcode 0x2eDAreservedopcode 0x2L313029282726252423222120191817161514131211109876543210l.srlopcode 0x38DABreservedopcode 0x1reservedopcode 0x8313029282726252423222120191817161514131211109876543210l.srliopcode 0x2eDAreservedopcode 0x1L313029282726252423222120191817161514131211109876543210l.subopcode 0x38DABreservedopcode 0x0reservedopcode 0x2313029282726252423222120191817161514131211109876543210l.swopcode 0x35IABI313029282726252423222120191817161514131211109876543210l.sysopcode 0x2000K313029282726252423222120191817161514131211109876543210l.xoropcode 0x38DABreservedopcode 0x0reservedopcode 0x5313029282726252423222120191817161514131211109876543210l.xoriopcode 0x2bDAITable SEQ Table \* ARABIC 8. List of 32-bit Implemented Instructions
For a complete description how instruction operate refer to OpenRISC 1000 System Architecture Manual.
Instruction Unit
Instruction unit generates instruction fetch effective address and fetches instructions from instruction cache. Each clock cycle one instruction can be fetched. Instruction fetch EA is further translated into physical address by IMMU.
General-Purpose Registers
General-purpose register file can supply two read operands each clock cycle and store one result in a destination register.
GPRs can be also read and written through development interface.
Load/Store Unit
LSU can execute one load instruction every two clock cycles assuming load instruction have a hit in the data cache. Execution of store instructions takes one clock cycle assuming they have a hit in the data cache.
LSU performs calculation of the load/store effective address. EA is further translated into physical address by DMMU.
Load/store effective address and load and store data can be also accessed through development interface.
Integer Execution Pipeline
The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions
Instruction GroupClock Cycles to ExecuteArithmetic except Multiply/Divide1Multiply3DivideNot implementedCompare1Logical1Rotate and Shift1Others1Table SEQ Table \* ARABIC 9. Execution Time of Integer Instructions
REF _Ref513308588 \h \* MERGEFORMAT Table 9 lists execution times for instructions executed by integer execution pipeline. Most instructions are executed in one clock cycle.
MAC Unit
MAC unit executes l.mac instructions. MAC unit implements 32x32 fully pipelined multiplier and 48-bit accumulator. MAC unit can accept one new l.mac instruction each clock cycle.
System Unit
System unit implements system control and status special-purpose registers and executes all l.mtspr/l.mfspr instructions.
Exceptions
The core implements a precise exception model. This means that when an exception is taken, the following conditions are met:
Subsequent instructions in program flow are discarded
Previous instructions finish and write back their results
The address of faulting instruction is saved in EPCR registers and the machine state is saved to ESR registers
Exception TypeVector Offsetcausing conditionsReset0x100Caused by reset.Bus Error0x200Caused by an attempt to access invalid physical address.Data Page Fault0x300Generated artificially by DTLB miss exception handler when no matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400Generated artificially by ITLB miss exception handler when no matching PTE found in page tables or page protection violation for instruction fetch.Low Priority External Interrupt0x500Low priority external interrupt asserted.Alignment0x600Load/store access to naturally not aligned location.Illegal Instruction0x700Illegal instruction in the instruction stream.High Priority External Interrupt0x800High priority external interrupt asserted.D-TLB Miss0x900No matching entry in DTLB (DTLB miss).I-TLB Miss0xA00No matching entry in ITLB (ITLB miss).System Call0xC00System call initiated by software.Breakpoint0xD00Initiated by the debug unit.Table SEQ Table \* ARABIC 10. List of Implemented Exceptions
The OR1200 exception support does not include support for fast context switching.
Data Cache Operation
Data Cache Load/Store Access
Load/store unit requests data from the data cache and stores them into the general-purpose register file and forwards them to integer execution units. Therefore LSU is tightly coupled with the data cache.
If there is no data cache line miss nor DTLB miss, load operations take two clock cycles to execute and store operations take one clock cycle to execute. LSU does all the data alignment work.
Data can be written to the data cache on a word, half-word or byte basis. Since data cache only operates in write-through mode, all writes are immediately written back to main memory or to the next level of caches.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 6. WISHBONE Write Cycle
REF _Ref513193242 \h Figure 6 shows how a write-through cycle on data WISHBONE interface is performed when a store instruction hits in the data cache.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.
Data Cache Line Fill Operation
When executing load instruction and a cache miss occurs, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the load/store unit to minimize performance loss because of the cache miss.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 7. WISHBONE Block Read Cycle
REF _Ref513194821 \h Figure 7 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.
When executing store instruction and a cache miss occurs, a 4 beat sequential read burst with critical word first is performed. After read burst single word write is performed to write data of the store instruction back to main memory or next level of caches. Regardless of the wideness of store instruction, always a word write is performed.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 8. WISHBONE Block Read/Write Cycle
REF _Ref513195072 \h Figure 8 shows how a cache line is read in WISHBONE read block cycle followed by a write transfer.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.
Cache/Memory Coherency
Data cache in OR1200 operates only in write-through mode. Furthermore OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local data cache and caches of other processors or main memory is implemented.
Data Cache Enabling/Disabling
Data cache is disabled at power up. Entire data cache can be enabled by setting bit SR[DCE] to one. Before data cache is enabled, it must be invalidated.
Data Cache Invalidation
Data cache in OR1200 does not support invalidation of entire data cache. Normal procedure to invalidate entire data cache is to cycle through all data cache lines and invalidate each line separately.
Data Cache Locking
Data cache implements way locking bits in data cache control register DCCR. Bits LWx lock individual ways when they are set to one.
Data Cache Line Prefetch
Data cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.
Data Cache Line Flush
Because data cache operates only in write-through mode, data cache line flush performs only line invalidation. Operation is performed by writing effective address to the DCBFR register.
Virtually the is no difference between data cache line flush and data cache line invalidate operation.
Data Cache Line Invalidate
Data cache line invalidate invalidates a single data cache line. Operation is performed by writing effective address to the DCBIR register.
Data Cache Line Write-back
Data cache line write-back operation does not do anything because data cache operates only in write-through mode.
Data Cache Line Lock
Locking of individual data cache lines is not implemented in OR1200.
Instruction Cache Operation
Instruction Cache Instruction Fetch Access
Instruction unit requests instruction from the instruction cache and forwards them to the instruction queue inside instruction unit. Therefore instruction unit is tightly coupled with the instruction cache.
If there is no instruction cache line miss nor ITLB miss, instruction fetch operation takes one clock cycle to execute.
Instruction cache cannot be explicitly modified like data cache can be with store instructions.
Instruction Cache Line Fill Operation
On a cache miss, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the instruction unit to minimize performance loss because of the cache miss.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 9. WISHBONE Block Read Cycle
REF _Ref513197552 \h Figure 9 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If iwb_ERR_I or iwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.
Cache/Memory Coherency
OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local instruction cache and caches of other processors or main memory is implemented.
Instruction Cache Enabling/Disabling
Instruction cache is disabled at power up. Entire instruction cache can be enabled by setting bit SR[ICE] to one. Before instruction cache is enabled, it must be invalidated.
Instruction Cache Invalidation
Instruction cache in OR1200 does not support invalidation of entire instruction cache. Normal procedure to invalidate entire instruction cache is to cycle through all instruction cache lines and invalidate each line separately.
Instruction Cache Locking
Instruction cache implements way locking bits in instruction cache control register ICCR. Bits LWx lock individual ways when they are set to one.
Instruction Cache Line Prefetch
Instruction cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.
Instruction Cache Line Invalidate
Instruction cache line invalidate invalidates a single instruction cache line. Operation is performed by writing effective address to the ICBIR register.
Instruction Cache Line Lock
Locking of individual instruction cache lines is not implemented in OR1200.
Data MMU
Translation Disabled
Load/store address translation can be disabled by clearing bit SR[DME]. If translation is disabled, then physical address used to access data cache and optionally provided on dwb_ADDR_O, is the same as load/store effective address.
Translation Enabled
Load/store address translation can be enabled by setting bit SR[DME]. If translation is enabled, it provides load/store effective address to physical address translation and page protection for memory accesses.
EMBED Visio.Drawing.6
Figure SEQ Figure \* ARABIC 10. 32-bit Address Translation Mechanism using Two-Level Page Table
In OR1200 case, page tables must be managed by operating systems virtual memory management subsystem. REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.
DMMUCR and Flush of Entire DTLB
DMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire DTLB must be performed by software flush of every DTLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.
Page Protection
After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, a data page fault exception is generated.
The memory protection mechanism allows selectively granting read access and write access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.
Protection attributeMeaningDTLBWyTR[SREx]Enable load operations in supervisor mode to the page.DTLBWyTR[SWEx]Enable store operations in supervisor mode to the page.DTLBWyTR[UREx]Enable load operations in user mode to the page.DTLBWyTR[UWEx]Enable store operations in user mode to the page.Table SEQ Table \* ARABIC 11. Protection Attributes for Load/Store Accesses
REF _Ref513346094 \h \* MERGEFORMAT Table 11 lists page protection attributes defined in DTLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with the PPI field of the PTE. Because OR1200 does not implement DMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into DTLBWyTR.
DTLB Entry Reload
OR1200 does not implement DTLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the DTLB. Software is responsible for maintaining accessed and dirty bits in the page tables.
When LSU computes load/store effective address whose physical address is not already cached by DTLB, a DTLB miss exception is invoked.
DTLB reload routine must load the correct PTE to correct DTLBWyMR and DTLBWyTR register from one of possible DTLB ways.
DTLB Entry Invalidation
Special-purpose register DTLBEIR must be written with the effective address and corresponding DTLB entry will be invalidated in the local DTLB.
Locking DTLB Entries
Since all DTLB entry reloads are performed in software, there is no hardware locking of DTLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.
Page Attribute Dirty (D)
Dirty (D) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate dirty attribute bit with page protection mechanism.
Page Attribute Accessed (A)
Accessed (A) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.
Page Attribute Weakly Ordered Memory (WOM)
Weakly ordered memory (WOM) attribute is not needed in OR1200 because all memory accesses are serialized and therefore this attribute is not implemented.
Page Attribute Write-Back Cache (WBC)
Write-back cache (WBC) attribute is not needed in OR1200 because data cache operates only in write-through mode and therefore this attribute is not implemented.
Page Attribute Caching-Inhibited (CI)
Caching-inhibited (CI) attribute is not implemented in OR1200 DTLB. Cached and uncached regions are divided by bit 30 of data effective address.
Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable SEQ Table \* ARABIC 12. Cached and uncached regions
Uncached accesses must be performed when I/O registers are memory mapped and all reads and writes must be always performed directly to the external interface and not to the data cache.
Page Attribute Cache Coherency (CC)
Cache coherency (CC) attribute is not needed in OR1200 because it doesnt implement support for multiprocessor environments and because data cache operates only in write-through mode and therefore this attribute is not implemented.
Instruction MMU
Translation Disabled
Instruction fetch address translation can be disabled by clearing bit SR[IME]. If translation is disabled, then physical address used to access instruction cache and optionally provided on iwb_ADDR_O, is the same as instruction fetch effective address.
Translation Enabled
Instruction fetch address translation can be enabled by setting bit SR[IME]. If translation is enabled, it provides instruction fetch effective address to physical address translation and page protection for instruction fetch accesses.
EMBED Visio.Drawing.6
Figure SEQ Figure \* ARABIC 11. 32-bit Address Translation Mechanism using Two-Level Page Table
In OR1200 case, page tables must be managed by operating systems virtual memory management subsystem. REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.
IMMUCR and Flush of Entire ITLB
IMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire ITLB must be performed by software flush of every ITLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.
Page Protection
After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, an instruction page fault exception is generated.
The memory protection mechanism allows selectively granting execute access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.
Protection attributeMeaningITLBWyTR[SXEx]Enable execute operations in supervisor mode of the page.ITLBWyTR[UXEx]Enable execute operations in user mode of the page.Table SEQ Table \* ARABIC 13. Protection Attributes for Instruction Fetch Accesses
REF _Ref513346094 \h \* MERGEFORMAT Table 11 lists page protection attributes defined in ITLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with PPI field of the PTE. Because OR1200 does not implement IMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into ITLBWyTR.
ITLB Entry Reload
OR1200 does not implement ITLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the ITLB. Software is responsible for maintaining accessed bit in the page tables.
When LSU computes instruction fetch effective address whose physical address is not already cached by ITLB, an ITLB miss exception is invoked.
ITLB reload routine must load the correct PTE to correct ITLBWyMR and ITLBWyTR register from one of possible ITLB ways.
ITLB Entry Invalidation
Special-purpose register ITLBEIR must be written with the effective address and corresponding ITLB entry will be invalidated in the local ITLB.
Locking ITLB Entries
Since all ITLB entry reloads are performed in software, there is no hardware locking of ITLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.
Page Attribute Dirty (D)
Dirty (D) attribute resides in the PTE but it is not used by the IMMU.
Page Attribute Accessed (A)
Accessed (A) attribute is not implemented in OR1200 ITLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.
Page Attribute Weakly Ordered Memory (WOM)
Weakly ordered memory (WOM) attribute is not needed in OR1200 because all instruction fetch accesses are serialized and therefore this attribute is not implemented.
Page Attribute Write-Back Cache (WBC)
Write-back cache (WBC) attribute resides in the PTE but it is not used by the IMMU.
Page Attribute Caching-Inhibited (CI)
Caching-inhibited (CI) attribute is not implemented in OR1200 ITLB. Cached and uncached regions are divided by bit 30 of instruction effective address.
Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable SEQ Table \* ARABIC 14. Cached and uncached regions
Page Attribute Cache Coherency (CC)
Cache coherency (CC) attribute resides in the PTE but it is not used by the IMMU.
Programmable Interrupt Controller
PICMR special-purpose register is used to mask or unmask up to 30 programmable interrupt sources. PICPR special-purpose register is used to assign low or high priority to maximum of 30 interrupt sources.
PICSR special-purpose register is used to determine status of each interrupt input. Bits in PICSR represent status of the interrupt inputs and the actual interrupt must be cleared in the device that is the source of a pending interrupt.
Tick Timer
Tick timer facility is enabled with TTMR[M]. TTCR is incremented with each clock cycle and a high priority interrupt can be asserted whenever lower 28 bits of TTCR match TTMR[TP] and TTMR[IE] is set.
TTCR restarts counting from zero when match event happens and TTMR[M] is 0x1. If TTMR[M] is 0x2, TTCR is stoped when match event happens and TTCR must be changed to start counting again. When TTMR[M] is 0x3, TTCR keeps counting even when match event happens.
Power Management
Clock Gating and Frequency Changing Versus CPU Stalling
If system doesnt support clock gating and if changing clock frequency in slow down mode is not possible, CPU can be stalled for certain number of clock cycles. This is much lower benefit on power consumption however it still reduces power consumption.
Slow Down Mode
Slow down mode is software controlled with the 4-bit value in PMR[SDF]. Lower value specifies higher expected performance from the processor core. Usually PMR[SDF] is dynamically set by the operating systems idle routine, that monitors the usage of the processor core.
PMR[SDF] is broadcasted on pm_clksd. External clock generator should adjust clock frequency according to the value of pm_clksd. Exact slow down factors are not defined but 0xF should go all the way down to 32.768 KHz.
With pm_clksd equal to 0xF, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.
Doze Mode
To switch to doze mode, software should set the PMR[DME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation circuitry should enable all clocks. Once clocks are running RISC is switched back again to the normal mode and PMR[DME] is cleared.
When doze mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate and pm_cpugate are asserted. As a result all clocks except clk_tt should be gated by external clock generation circuitry.
Sleep Mode
To switch to sleep mode, software should set the PMR[SME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation should enable all clocks. Once clocks are running, RISC is switched back again to the normal mode and PMR[SME] is cleared.
When sleep mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate, pm_cpu_gate and pm_tt_gate are asserted. As a result all clocks including clk_tt should be gated by external clock generation circuitry.
In sleep mode, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.
Clock Gating
Clock gating feature is not implemented in OR1200 power management.
Disabled Units Force Clock Gating
Units that are disabled in special-purpose register SR, have their clock gate signals asserted. Cleared bits SR[DCE], SR[ICE], SR[DME] and SR[IME] directly force assertion of pm_dc_gate, pm_ic_gate, pm_dmmu_gate and pm_immu_gate.
Debug Unit
Debug unit can be controlled through development interface or it can operate independently programmed and handled by the RISCs resident debug software.
Watchpoints
OR1200 debug unit does not implement OR12000 architecture watchpoints.
Breakpoint Exception
Which breakpointDMR2[WGB] bits specify which watchpoints invoke breakpoint exception. By invoking breakpoint exception, target resident debugger can be built.
Breakpoint is broadcasted on development interface on dbg_bp_o.
Development Interface
An additional development and debug interface IP core may be used to connect OpenRISC 1200 to standard debuggers using IEEE.1149.1 (JTAG) protocol.
Debugging Through Development Interface
The DSR special-purpose register specifies which exceptions cause the core to stop the execution of the exception handler and turn over control to development interface. It can be programmed by the resident debug software or by the development interface.
The DRR special-purpose register is specifies which event caused the core to stop the execution of program flow and turned over control to the development interface. It should be cleared by the resident debug software or by the development interface.
The DIR special-purpose register is not implemented.
Reading PC, Load/Store EA, Load Data, Store Data, Instruction
Crucial information like program counter (PC), load/store effective address (LSEA), load data, store data and current instruction in execution pipeline can be asynchronously read through the development interface.
dbg_op_i[2:0]Meaning0x0Reading Program Counter (PC)0x1Reading Load/Store Effective Address0x2Reading Load Data0x3Reading Store Data0x4Reading SPR0x5Writing SPR0x6Reading Instruction in Execution Pipeline0x7ReservedTable SEQ Table \* ARABIC 15. Development Interface Operation Commands
REF _Ref513329306 \h \* MERGEFORMAT Table 15 lists operation commands that control what is read or written through development interface. All reads except reads and writes of SPRs are asynchronous.
Reading and Writing SPRs Through Development Interface
For reads and write to SPRs dbg_op_i must be set to 0x4 and 0x5, respectively.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 12. Development Interface Cycles
REF _Ref513329852 \h \* MERGEFORMAT Figure 12 shows development interface cycles. Writes must be synchronous to the main RISC clock positive edge and should take one clock cycle. Reads must take two clock cycles because access to synchronous cache lines or to TLB entries introduces one clock cycle of delay.
If required, external debugger can stop the CPU core by asserting dbg_stall_i. This way it can have enough time to read all interesting registers from the RISC or guarantee that writes into SPRs are performed without RISC writing to the same registers.
Tracking Data Flow
An external debugger can monitor and record data flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the load/store unit, load/store effective address and load/store data, all available at the development interface.
dbg_lss_o[3:0]Load/Store Instruction in Execution0x0No load/store instruction in execution0x1Reserved for load doubleword0x2Load byte and zero extend0x3Load byte and sign extend0x4Load halfword and zero extend0x5Load halfword and sign extend0x6Load singleword and zero extend0x7Load singleword and sign extend0x8Reserved for store doubleword0x9Reserved0xAStore byte0xBReserved0xCStore halfword0xDReserved0xEStore singleword0xFReservedTable SEQ Table \* ARABIC 16. Status of the Load/Store Unit
External trace buffer can capture all interesting data flow events by analyzing status of the load/store unit available on dbg_lss_o. REF _Ref513326484 \h Table 16 lists different status encoding for the load/store unit.
Tracking Program Flow
An external debugger can monitor and record program flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the instruction unit, PC and fetched instruction word, all available at the development interface.
dbg_is_o[1:0]Instruction Fetch Status0x0No instruction fetch in progress0x1Normal instruction fetch0x2Executing branch instruction0x3Fetching instruction in delay slotTable SEQ Table \* ARABIC 17. Status of the Instruction Unit
External trace buffer can capture all interesting program flow events by analyzing status of the instruction unit available on dbg_is_o. REF _Ref513326219 \h \* MERGEFORMAT Table 17 lists different status encoding for the instruction unit.
Triggering External Watcpoint Event
REF _Ref513324670 \h \* MERGEFORMAT Figure 13 shows how development interface can assert dbg_ewt_I and cause watchpoint event. If programmed, external watchpoint event will cause a breakpoint exception.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 13. Assertion of External Watchpoint Trigger
4
Registers
This section describes all registers inside the OR1200 core. Shifting GRP number 11 bits left and adding REG number computes the address of each special-purpose register. All registers are 32 bits wide from software perspective. USER MODE and SUPV MODE specify the valid access types for each register in user mode and supervisor mode of operation. R/W stands for read and write access and R stands for read only access.
Registers list
Grp
#Reg #Reg NameUSER MODESUPV
MODEDescription00VRRVersion Register01UPRRUnit Present Register02CPUCFGRRCPU Configuration Register03DMMUCFGRRData MMU Configuration Register04IMMUCFGRRInstruction MMU Configuration Register05DCCFGRRData Cache Configuration Register06ICCFGRRInstruction Cache Configuration Register07DCFGRRDebug Configuration Register016PCR/WPC mapped to SPR space017SRR/WSupervision Register032EPCR0R/WException PC Register048EEAR0R/WException EA Register064ESR0R/WException SR Register01024-1055GPR0-GPR31R/WGPRs mapped to SPR space12DTLBEIRWData TLB Entry Invalidate Register11024-1151DTLBW0MR0-DTLBW0MR127R/WData TLB Match Registers Way 011536-1663DTLBW0TR0-DTLBW0TR127R/WData TLB Translate Registers Way 022ITLBEIRWInstruction TLB Entry Invalidate Register21024-1151ITLBW0MR0-ITLBW0MR127R/WInstruction TLB Match Registers Way 021536-1663ITLBW0TR0-ITLBW0TR127R/WInstruction TLB Translate Registers Way 030DCCRR/WDC Control Register31DCBIRWDC Block Invalidate Register3257DCBFRWWDC Block Flush Register40ICCRR/WIC Control Register4256ICBIRWWIC Block Invalidate Register5256MACLOR/WR/WMAC Low5257MACHIR/WR/WMAC High616DMR1R/WDebug Mode Register 1617DMR2R/WDebug Mode Register 2620DSRR/WDebug Stop Register621DRRR/WDebug Reason Register80PMRR/WPower Management Register91PICMRR/WPIC Mask Register92PICPRR/WPIC Priority Register93PICSRR/WPIC Status Register100TTMRR/WTick Timer Mode Register10256TTCRR*R/WTick Timer Count RegisterTable SEQ Table \* ARABIC 18. List of All Registers
REF _Ref513309410 \h \* MERGEFORMAT Table 18 lists all OpenRISC 1000 special-purpose registers implemented in OR1200. Registers VR and UPR are described below. For description of other registers refer to OpenRISC 1000 System Architecture Manual document.
Register VR description
Special-purpose register VR identifies the version (model) and revision level of the OpenRISC 1000 processor. It also specifies possible standard template on which this implementation is based.
Bit #AccessResetDescription5:0RRevisionREV
Revision number15:6R0x0Reserved23:16R0x00CFG
Configuration should be read from UPR and configuration registers31:24R0x12VER
Version number for OR1200 is fixed at 0x1200.Table SEQ Table \* ARABIC 19. VR Register
Register UPR description
Special-purpose register UPR identifies the units present in the processor. It has a bit for each implemented unit or functionality. Lower sixteen bits identify present units defined in the OpenRISC 1000 architecture. Upper sixteen bits define present custom units.
Bit #AccessResetDescription0R1UP
UPR present1R1DCP
Data cache present2R1ICP
Instruction cache present3R1DMP
Data MMU present4R1IMP
Instruction MMU present5R1MP
MAC present6R1DUP
Debug unit present7R0PCUP
Performance counters unit not present8R1PMP
Power Management Present9R1PICP
Programmable interrupt controller present10R1TTP
Tick timer present23:11RXReserved31:24R0xXXXXCUP
The user of the OR1200 core adds custom units.Table SEQ Table \* ARABIC 20. UPR Register
Register CPUCFGR description
Special-purpose register CPUCFGR identifies the capabilities and configuration of the CPU.
Bit #AccessResetDescription3:0R0x0NSGF
Zero number of shadow GPR files4R0HGF
No half GPR files5R1OB32S
ORBIS32 supported6R0OB64S
ORBIS64 not supported7R0OF32S
ORFPX32 not supported8R0OF64S
ORFPX64 not supported9R0OV64S
ORVDX64 not supportedTable SEQ Table \* ARABIC 21. CPUCFGR Register
Register DMMUCFGR description
Special-purpose register DMMUCFGR identifies the capabilities and configuration of the DMMU.
Bit #AccessResetDescription1:0R0x0NTW
One DTLB way4:2R0x4 0x7NTS
16, 32, 64 or 128 DTLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No DMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
DTLB entry invalidate register implemented11R0HTR
No hardware DTLB reloadTable SEQ Table \* ARABIC 22. DMMUCFGR Register
Register IMMUCFGR description
Special-purpose register IMMUCFGR identifies the capabilities and configuration of the IMMU.
Bit #AccessResetDescription1:0R0x0NTW
One ITLB way4:2R0x4 0x7NTS
16, 32, 64 or 128 ITLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No IMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
ITLB entry invalidate register implemented11R0HTR
No hardware ITLB reloadTable SEQ Table \* ARABIC 23. IMMUCFGR Register
Register DCCFGR description
Special-purpose register DCCFGR identifies the capabilities and configuration of the data cache.
Bit #AccessResetDescription2:0R0x0NCW
One DC way6:3R0x4 0x7NCS
16, 32, 64 or 128 DC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
DC control register implemented10R1CBIRI
DC block invalidate register implemented11R0CBPRI
DC block prefetch register not implemented12R0CBLRI
DC block lock register not implemented13R1CBFRI
DC block flush register implemented14R0CBWBRI
DC block write-back register not implementedTable SEQ Table \* ARABIC 24. DCCFGR Register
Register ICCFGR description
Special-purpose register ICCFGR identifies the capabilities and configuration of the instruction cache.
Bit #AccessResetDescription2:0R0x0NCW
One IC way6:3R0x4 0x7NCS
16, 32, 64 or 128 IC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
IC control register implemented10R1CBIRI
IC block invalidate register implemented11R0CBPRI
IC block prefetch register not implemented12R0CBLRI
IC block lock register not implemented13R1CBFRI
IC block flush register implemented14R0CBWBRI
IC block write-back register not implementedTable SEQ Table \* ARABIC 25. ICCFGR Register
Register DCFGR description
Special-purpose register DCFGR identifies the capabilities and configuration of the debut unit.
Bit #AccessResetDescription2:0R0x0NDP
Zero DVR/DCR pairs3R0 WPCI
Watchpoint counters not implementedTable SEQ Table \* ARABIC 26. DCFGR Register
5
IO ports
OR1200 IP core has several interfaces. REF _Ref507257694 \h Figure 14 below shows all interfaces:
Instruction and data WISHBONE host interfaces
Power management interface
Development interface
Interrupts interface
EMBED Visio.Drawing.6
Figure SEQ Figure \* ARABIC 14. Cores Interfaces
Instruction WISHBONE Master Interface
OR1200 has two master WISHBONE Rev B compliant interfaces. Instruction interface is used to connect OR1200 core to memory subsystem for purpose of fetching instructions or instruction cache lines.
PortWidthDirectionDescriptioniwb_CLK_I1InputClock inputiwb_RST_I1InputReset inputiwb_CYC_O1OutputIndicates valid bus cycle (core select)iwb_ADR_O32OutputsAddress outputsiwb_DAT_I32InputsData inputsiwb_DAT_O32OutputsData outputsiwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)iwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)iwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)iwb_RTY_I1InputIn OR1200 treated same way as iwb_ERR_I.iwb_WE_O1OutputWrite transaction when asserted highiwb_STB_O1OutputsIndicates valid data transfer cycleTable SEQ Table \* ARABIC 27. Instruction WISHBONE Master Interface Signals
Data WISHBONE Master Interface
OR1200 has two master WISHBONE Rev B compliant interfaces. Data interface is used to connect OR1200 core to external peripherals and memory subsystem for purpose of reading and writing data or data cache lines.
PortWidthDirectionDescriptiondwb_CLK_I1InputClock inputdwb_RST_I1InputReset inputdwb_CYC_O1OutputIndicates valid bus cycle (core select)dwb_ADR_O32OutputsAddress outputsdwb_DAT_I32InputsData inputsdwb_DAT_O32OutputsData outputsdwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)dwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)dwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)dwb_RTY_I1InputIn OR1200 treated same way as dwb_ERR_I.dwb_WE_O1OutputWrite transaction when asserted highdwb_STB_O1OutputsIndicates valid data transfer cycleTable SEQ Table \* ARABIC 28. Data WISHBONE Master Interface Signals
System Interface
System interface connects reset, clock and other system signals to the OR1200 core.
PortWidthDirectionDescriptionRst1InputAsynchronous resetclk_cpu1InputMain clock input to the RISCclk_dc1InputData cache clockclk_ic1InputInstruction cache clockclk_dmmu1InputData MMU clockclk_immu1InputInstruction MMU clockclk_tt1InputTick timer clockTable SEQ Table \* ARABIC 29. System Interface Signals
Development Interface
Development interface connects external development port to the RISCs internal debug facility. Debug facility allows control over program execution inside RISC, setting of breakpoints and watchpoints, and tracing of instruction and data flows.
PortWidthDirectionDescriptiondbg_dat_o32OutputTransfer of data from RISC to external development interfacedbg_dat_i32InputTransfer of data from external development interface to RISCdbg_adr_i32InputAddress of special-purpose register to be read or writtendbg_op_I3InputOperation select for development interfacedbg_lss_o4OutputStatus of load/store unitdbg_is_o2OutputStatus of instruction fetch unitdbg_wp_o11OutputStatus of watchpointsdbg_bp_o1OutputStatus of the breakpointdbg_stall_i1InputStalls RISC CPU coredbg_ewt_i1InputExternal watchpoint triggerTable SEQ Table \* ARABIC 30. Development Interface
Power Management Interface
Power management interface provides signals for interfacing RISC core with external power management circuitry. External power management circuitry is required to implement functions that are technology specific and cannot be implemented inside OR1200 core.
PortWidthDirectionGenerationDescriptionpm_clksd4OutputStatic (in SW)Slow down outputs that control reduction of RISC clock frequencypm_cpustall1Input-Synchronous stall of the RISCs CPU corepm_dc_gate1OutputDynamic (in HW)Gating of data cache clockpm_ic_gate1OutputDynamic (in HW)Gating of instruction cache clockpm_dmmu_gate1OutputDynamic (in HW)Gating of data MMU clockpm_immu_gate1OutputDynamic (in HW)Gating of instruction MMU clockpm_tt_gate1OutputDynamic (in HW)Gating of tick timer clockpm_cpu_gate1OutputStatic (in SW)Gating of main CPU clockpm_wakeup1OutputDynamic (in HW)Activate all clockspm_lvolt1OutputStatic (in SW)Lower voltageTable SEQ Table \* ARABIC 31. Power Management Interface
Interrupt Interface
Interrupt interface has interrupt inputs for interfacing external peripherals interrupt outputs to the RISC core. All interrupt inputs are evaluated on positive edge of main RISC clock.
PortWidthDirectionDescriptionpic_intsPIC_INTSInputExternal interruptsTable SEQ Table \* ARABIC 32. Interrupt Interface
A
Core HW Configuration
This section describes parameters that are set by the user of the core and define configuration of the core. Parameters must be set by the user before actual use of the core in simulation or synthesis.
Variable NameRangeDefaultDescriptionEADDR_WIDTH3232Effective address widthVADDR_WIDTH3232Virtual address widthPADDR_WIDTH24 3632Physical address widthDATA_WIDTH3232Data width / Operation widthDC_IMPL0 11Data cache implementationDC_SETS512512Data cache number of setsDC_WAYS11Data cache number of waysDC_LINE1616Data cache line sizeIC_IMPL0 11Instruction cache implementationIC_SETS512512Instruction cache number of setsIC_WAYS11Instruction cache number of waysIC_LINE1616Instruction cache line size in bytesDMMU_IMPL0 11Data MMU implementationDTLB_SETS6464Data TLB number of setsDTLB_WAYS11Data TLB number of waysIMMU_IMPL0 11Instruction MMU implementationITLB_SETS6464Instruction TLB number of setsITLB_WAYS11Instruction TLB number of waysPIC_INTS2 3230Number of interrupt inputs
OpenCores TITLEOpenRISC 1200 IP Core DATE \@"M/d/yy" 4/6/01
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.6 Preliminary PAGE 19 of NUMPAGES 63
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C o m p O b j T V i O b j I n f o W C O N T E N T S }0
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Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
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Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
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! " # $ % & ' ( ) * + , - . 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n p q r s t u v w x y z { | } ~ Timing Diagram Editor v7.1g - Output File
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PROJECT
|
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BaseTimeUnit 1
|
|
DisplayTimeUnit 2
|
|
TextGridX 250.000000
|
|
TextGridY 6
|
|
EdgeGridX 250.000000
|
|
ImportStartTime 0.000000
|
|
ImportEndTime 281474976710656.000000
|
|
TimePerPixel 6.497175
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
|
ColWidths 144,216,288,423,488
|
|
ScrollPos 0.000000,0.000009,0.000000
|
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
|
SigLabelFontHeight 10
|
|
LabelHeight 12
|
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
|
LibPath
|
|
EntireTime YES
|
|
PrintTimeSpecified NO
|
|
FromTime 0
|
|
ToTime 5.75
|
|
AllSignals YES
|
|
CurrSelSigs NO
|
|
PrintTo 2
|
|
PrintFileName C:\DOCS\reset.wmf
|
|
PreviewInterchange YES
|
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
|
PrintTimeLine NO
|
|
PrintBorderBox YES
|
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
|
AddPreviewToEPS NO
|
|
PreviewRes 150
|
|
MarginLR 1.25
|
|
MifImageWidth 6.00
|
|
MarginTB Auto
|
|
Header %d %t;%f;%p
|
|
Footer
|
|
ScaleHorz 100
|
|
ScaleVert 100
|
|
ScaleHPage 1
|
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
|
DefaultClock Unclocked
|
|
DefaultEdgeLevel neg
|
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
|
DefaultClockEnable Not Used
|
|
DefaultClockToOutLH 0
|
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
|
DefaultHold 0
|
|
DefaultRegStartupState unknown
|
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
|
DefaultAsyncSetClear True
|
|
DefaultActiveLowClockEnable True
|
|
SigLabelFontHeight 10
|
|
PROPS!
|
|
!
|
|
|
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
|
DrawWndFont DEFAULT
|
|
DrawWndColor DEFAULT
|
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
|
LabelWndColor DEFAULT
|
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
|
SignalColor 2
|
|
LabelOffset 4
|
|
BusDisplay 0
|
|
WaveFormWidth 0.500000
|
|
WaveFormColor 0
|
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
|
SlantAngle 75
|
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
|
!
|
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
|
FilesInsideDiagramModelDeclarationSection
|
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
|
VerboseSequenceVerification 0
|
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
|
DefaultCycleClock Unclocked
|
|
DefaultCycleEdge neg
|
|
!
|
|
|
|
MACROS
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CLOCK clk_risc
|
|
PERIODE 1
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL LOW
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION input
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E5 1 2500 2500 1 0 DR 0
|
|
E6 0 3000 3000 1 0 DR 0
|
|
E7 0 3500 3500 1 0 DR 0
|
|
E9 1 4500 4500 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL rst
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 1750 1750 1 0 DR 0
|
|
E1 1 3750 3750 1 0 DR 0
|
|
E2 0 5750 5750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_dat_o
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 X 1750 1750 1 0 DR 0
|
|
E1 V 4750 4750 0x0 1 0 DR 0
|
|
E2 V 5750 5750 0x4 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_op_i
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 3
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 V 5750 5750 READ PC 0x0 1 0 DR 0
|
|
!
|
|
|
|
PARM Trs
|
|
MIN NULL
|
|
MAX NULL
|
|
COMMENT Reset Setup Time
|
|
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trs}
|
|
MinRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
|
MaxRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
|
CommentRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Setup Time}
|
|
CLOCKNAME Unclocked
|
|
CLOCKEDGE neg
|
|
IsApplyInput False
|
|
PROPS!
|
|
!
|
|
|
|
PARM Trh
|
|
MIN NULL
|
|
MAX NULL
|
|
COMMENT Reset Hold Time
|
|
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trh}
|
|
MinRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
|
MaxRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
|
CommentRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Hold Time}
|
|
CLOCKNAME Unclocked
|
|
CLOCKEDGE neg
|
|
IsApplyInput False
|
|
PROPS!
|
|
!
|
|
|
|
SETUP Trs
|
|
FROM clk_risc E9 S0
|
|
TO rst E1 S1
|
|
OUTARROWS 0
|
|
USERPLACED 0
|
|
DISPLAYAS 6
|
|
CUSTDISPSTRING %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
EnableHdlCodeGeneration False
|
|
OrderIndex 1
|
|
PROPS!
|
|
!
|
|
|
|
HOLD Trh
|
|
FROM clk_risc E7 S0
|
|
TO rst E1 S1
|
|
OUTARROWS 0
|
|
USERPLACED 0
|
|
DISPLAYAS 6
|
|
CUSTDISPSTRING %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
EnableHdlCodeGeneration False
|
|
OrderIndex 2
|
|
PROPS!
|
|
!
|
|
|
|
MARKER MARK0
|
|
ATTACH rst NULL S1
|
|
TIME 2750.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
_ 1 0 5 0 0 7 8 8 3 7 Z Q<= Kuy `} `} O l e
|
|
C o m p O b j Y [ i O b j I n f o \ C O N T E N T S ?( _ 1 0 5 0 0 6 4 4 0 9 l _ Q<= Kuy `} @9 O l e
|
|
C o m p O b j ^ ` i Timing Diagram Editor v7.1g - Output File
|
|
|
|
PROJECT
|
|
BaseTimeUnit 1
|
|
DisplayTimeUnit 2
|
|
TextGridX 250.000000
|
|
TextGridY 6
|
|
EdgeGridX 250.000000
|
|
ImportStartTime 0.000000
|
|
ImportEndTime 281474976710656.000000
|
|
TimePerPixel 6.497175
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
|
ColWidths 144,216,288,423,488
|
|
ScrollPos 0.000000,0.000000,0.000000
|
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
|
SigLabelFontHeight 10
|
|
LabelHeight 12
|
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
|
LibPath
|
|
EntireTime YES
|
|
PrintTimeSpecified NO
|
|
FromTime 0
|
|
ToTime 5.75
|
|
AllSignals YES
|
|
CurrSelSigs NO
|
|
PrintTo 2
|
|
PrintFileName C:\DOCS\reset_gated.wmf
|
|
PreviewInterchange YES
|
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
|
PrintTimeLine NO
|
|
PrintBorderBox YES
|
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
|
AddPreviewToEPS NO
|
|
PreviewRes 150
|
|
MarginLR 1.25
|
|
MifImageWidth 6.00
|
|
MarginTB Auto
|
|
Header %d %t;%f;%p
|
|
Footer
|
|
ScaleHorz 100
|
|
ScaleVert 100
|
|
ScaleHPage 1
|
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
|
DefaultClock Unclocked
|
|
DefaultEdgeLevel neg
|
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
|
DefaultClockEnable Not Used
|
|
DefaultClockToOutLH 0
|
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
|
DefaultHold 0
|
|
DefaultRegStartupState unknown
|
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
|
DefaultAsyncSetClear True
|
|
DefaultActiveLowClockEnable True
|
|
SigLabelFontHeight 10
|
|
PROPS!
|
|
!
|
|
|
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
|
DrawWndFont DEFAULT
|
|
DrawWndColor DEFAULT
|
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
|
LabelWndColor DEFAULT
|
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
|
SignalColor 2
|
|
LabelOffset 4
|
|
BusDisplay 0
|
|
WaveFormWidth 0.500000
|
|
WaveFormColor 0
|
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
|
SlantAngle 75
|
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
|
!
|
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
|
FilesInsideDiagramModelDeclarationSection
|
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
|
VerboseSequenceVerification 0
|
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
|
DefaultCycleClock Unclocked
|
|
DefaultCycleEdge neg
|
|
!
|
|
|
|
MACROS
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CLOCK clk_risc
|
|
PERIODE 1
|
|
DUTY 50
|
|
OFFSETE 4.5
|
|
INITIAL HIGH
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 1 1 0 2 2 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION input
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E5 1 7000 7000 1 0 DR 0
|
|
E6 0 7500 7500 1 0 DR 0
|
|
E7 1 8000 8000 1 0 DR 0
|
|
E9 1 9000 9000 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL rst
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 1750 1750 1 0 DR 0
|
|
E1 1 3750 3750 1 0 DR 0
|
|
E2 0 5750 5750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_dat_o
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 X 1750 1750 1 0 DR 0
|
|
E1 V 4750 4750 0x0 1 0 DR 0
|
|
E2 V 5750 5750 0x4 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_op_i
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 3
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 V 5750 5750 READ PC 0x0 1 0 DR 0
|
|
!
|
|
|
|
MARKER MARK0
|
|
ATTACH rst NULL S1
|
|
TIME 2750.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
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|
|
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|
|
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|
|
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|
|
9Hem&I9[W033/L!k5
|
|
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|
|
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|
|
E\q(_> zH®"%maఘG9XRg0]G"%mQ("G?_}{Myלwm/uCo
|
|
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|
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|
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|
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t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!! !
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ V !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram O b j I n f o a C O N T E N T S ~7 _ 1 0 5 0 0 6 8 8 9 7 z d Q<= Kuy @9 O l e
|
|
Timing Diagram Editor v7.1g - Output File
|
|
|
|
PROJECT
|
|
BaseTimeUnit 1
|
|
DisplayTimeUnit 2
|
|
TextGridX 625.000000
|
|
TextGridY 6
|
|
EdgeGridX 625.000000
|
|
ImportStartTime 0.000000
|
|
ImportEndTime 281474976710656.000000
|
|
TimePerPixel 17.543860
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
|
ColWidths 144,216,288,423,488
|
|
ScrollPos 0.000000,0.000000,0.000000
|
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
|
SigLabelFontHeight 8
|
|
LabelHeight 10
|
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
|
LibPath
|
|
EntireTime YES
|
|
PrintTimeSpecified NO
|
|
FromTime 0
|
|
ToTime 15.625
|
|
AllSignals YES
|
|
CurrSelSigs NO
|
|
PrintTo 2
|
|
PrintFileName C:\DOCS\wb_writesingle.wmf
|
|
PreviewInterchange YES
|
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
|
PrintTimeLine NO
|
|
PrintBorderBox YES
|
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
|
AddPreviewToEPS NO
|
|
PreviewRes 150
|
|
MarginLR 1
|
|
MifImageWidth 6.00
|
|
MarginTB Auto
|
|
Header %d %t;%f;%p
|
|
Footer
|
|
ScaleHorz 100
|
|
ScaleVert 100
|
|
ScaleHPage 1
|
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
|
DefaultClock Unclocked
|
|
DefaultEdgeLevel neg
|
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
|
DefaultClockEnable Not Used
|
|
DefaultClockToOutLH 0
|
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
|
DefaultHold 0
|
|
DefaultRegStartupState unknown
|
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
|
DefaultAsyncSetClear True
|
|
DefaultActiveLowClockEnable True
|
|
SigLabelFontHeight 10
|
|
PROPS!
|
|
!
|
|
|
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
|
DrawWndFont DEFAULT
|
|
DrawWndColor DEFAULT
|
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
|
LabelWndColor DEFAULT
|
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
|
SignalColor 2
|
|
LabelOffset 2
|
|
BusDisplay 0
|
|
WaveFormWidth 0.500000
|
|
WaveFormColor 0
|
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
|
SlantAngle 75
|
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
|
!
|
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
|
FilesInsideDiagramModelDeclarationSection
|
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
|
VerboseSequenceVerification 0
|
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
|
DefaultCycleClock Unclocked
|
|
DefaultCycleEdge neg
|
|
!
|
|
|
|
MACROS
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CLOCK CLK_RISC
|
|
PERIODE 2.5
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL HIGH
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 0 1 0 2 0 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION internal
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
!
|
|
|
|
CLOCK dwb_CLK_I
|
|
PERIODE 5
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL LOW
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION input
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
!
|
|
|
|
SIGNAL dwb_ADR_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 V -1 -1 1 0 DR 0
|
|
E1 X 3125 3125 1 0 DR 0
|
|
E2 V 13125 13125 Valid 1 0 DR 0
|
|
E3 X 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_DAT_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 X 13125 13125 1 0 DR 0
|
|
E1 V 13126 13126 Valid 1 0 DR 0
|
|
E2 X 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_DAT_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 3125 3125 1 0 DR 0
|
|
E1 V 13125 13125 Valid 1 0 DR 0
|
|
E2 X 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_WE_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 3125 3125 1 0 DR 0
|
|
E1 0 3467 3467 1 0 DR 0
|
|
E2 1 13125 13125 1 0 DR 0
|
|
E3 0 13126 13126 1 0 DR 0
|
|
E4 X 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_SEL_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 3
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 3125 3125 1 0 DR 0
|
|
E1 V 13125 13125 Valid 1 0 DR 0
|
|
E2 X 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_STB_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 3125 3125 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_ACK_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 11250 11250 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_CYC_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 3125 3125 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_ERR_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_RTY_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 15625 15625 1 0 DR 0
|
|
!
|
|
|
|
MARKER MARK0
|
|
ATTACH dwb_DAT_O NULL S4
|
|
TIME 7500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
C o m p O b j c e i O b j I n f o f C O N T E N T S K _ 1 0 5 0 0 6 8 8 1 9 ] b i Q<= Kuy Timing Diagram Editor v7.1g - Output File
|
|
|
|
PROJECT
|
|
BaseTimeUnit 1
|
|
DisplayTimeUnit 2
|
|
TextGridX 625.000000
|
|
TextGridY 6
|
|
EdgeGridX 625.000000
|
|
ImportStartTime 0.000000
|
|
ImportEndTime 281474976710656.000000
|
|
TimePerPixel 50.000000
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
|
ColWidths 144,216,288,423,488
|
|
ScrollPos 0.000000,0.000000,0.000000
|
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
|
SigLabelFontHeight 10
|
|
LabelHeight 12
|
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
|
LibPath
|
|
EntireTime YES
|
|
PrintTimeSpecified NO
|
|
FromTime 0
|
|
ToTime 43.75
|
|
AllSignals YES
|
|
CurrSelSigs NO
|
|
PrintTo 2
|
|
PrintFileName C:\DOCS\wb_readblock_typ.wmf
|
|
PreviewInterchange YES
|
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
|
PrintTimeLine NO
|
|
PrintBorderBox YES
|
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
|
AddPreviewToEPS NO
|
|
PreviewRes 150
|
|
MarginLR 1.25
|
|
MifImageWidth 6.00
|
|
MarginTB Auto
|
|
Header %d %t;%f;%p
|
|
Footer
|
|
ScaleHorz 100
|
|
ScaleVert 100
|
|
ScaleHPage 1
|
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
|
DefaultClock Unclocked
|
|
DefaultEdgeLevel neg
|
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
|
DefaultClockEnable Not Used
|
|
DefaultClockToOutLH 0
|
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
|
DefaultHold 0
|
|
DefaultRegStartupState unknown
|
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
|
DefaultAsyncSetClear True
|
|
DefaultActiveLowClockEnable True
|
|
SigLabelFontHeight 10
|
|
PROPS!
|
|
!
|
|
|
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
|
DrawWndFont DEFAULT
|
|
DrawWndColor DEFAULT
|
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
|
LabelWndColor DEFAULT
|
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
|
SignalColor 2
|
|
LabelOffset 2
|
|
BusDisplay 0
|
|
WaveFormWidth 0.500000
|
|
WaveFormColor 0
|
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
|
SlantAngle 75
|
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
|
!
|
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
|
FilesInsideDiagramModelDeclarationSection
|
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
|
VerboseSequenceVerification 0
|
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
|
DefaultCycleClock Unclocked
|
|
DefaultCycleEdge neg
|
|
!
|
|
|
|
MACROS
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CLOCK CLK_RISC
|
|
PERIODE 2.5
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL HIGH
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 0 1 0 2 0 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION internal
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
!
|
|
|
|
CLOCK dwb_CLK_I
|
|
PERIODE 5
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL LOW
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION input
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
!
|
|
|
|
SIGNAL dwb_ADR_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 V -1 -1 1 0 DR 0
|
|
E1 X 3125 3125 1 0 DR 0
|
|
E2 V 3126 3126 A0 1 0 DR 0
|
|
E3 X 3750 3750 1 0 DR 0
|
|
E4 V 13125 13125 A0 1 0 DR 0
|
|
E5 X 13625 13625 1 0 DR 0
|
|
E6 V 23125 23125 A4 1 0 DR 0
|
|
E7 X 23625 23625 1 0 DR 0
|
|
E8 V 33125 33125 A8 1 0 DR 0
|
|
E9 X 33625 33625 1 0 DR 0
|
|
E10 V 43125 43125 A12 1 0 DR 0
|
|
E11 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_DAT_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 X 11250 11250 1 0 DR 0
|
|
E1 V 13125 13125 D0 1 0 DR 0
|
|
E2 X 21250 21250 1 0 DR 0
|
|
E3 V 23125 23125 D4 1 0 DR 0
|
|
E4 X 31250 31250 1 0 DR 0
|
|
E5 V 33125 33125 D8 1 0 DR 0
|
|
E6 X 41250 41250 1 0 DR 0
|
|
E7 V 43125 43125 D12 1 0 DR 0
|
|
E8 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_DAT_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_WE_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 3125 3125 1 0 DR 0
|
|
E1 1 3126 3126 1 0 DR 0
|
|
E2 0 13125 13125 1 0 DR 0
|
|
E3 X 13625 13625 1 0 DR 0
|
|
E4 0 23125 23125 1 0 DR 0
|
|
E5 X 23625 23625 1 0 DR 0
|
|
E6 0 33125 33125 1 0 DR 0
|
|
E7 X 33625 33625 1 0 DR 0
|
|
E8 0 43125 43125 1 0 DR 0
|
|
E9 X 43625 43625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_SEL_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 3
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 V 0 0 Valid 1 0 DR 0
|
|
E1 X 3750 3750 1 0 DR 0
|
|
E2 V 13125 13125 Valid 1 0 DR 0
|
|
E3 X 13625 13625 1 0 DR 0
|
|
E4 V 23125 23125 Valid 1 0 DR 0
|
|
E5 X 23625 23625 1 0 DR 0
|
|
E6 V 33125 33125 Valid 1 0 DR 0
|
|
E7 X 33625 33625 1 0 DR 0
|
|
E8 V 43125 43125 Valid 1 0 DR 0
|
|
E9 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_STB_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 3750 3750 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 13625 13625 1 0 DR 0
|
|
E3 1 23125 23125 1 0 DR 0
|
|
E4 0 23625 23625 1 0 DR 0
|
|
E5 1 33125 33125 1 0 DR 0
|
|
E6 0 33625 33625 1 0 DR 0
|
|
E7 1 43125 43125 1 0 DR 0
|
|
E8 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_ACK_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 11250 11250 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 21250 21250 1 0 DR 0
|
|
E3 1 23125 23125 1 0 DR 0
|
|
E4 0 31250 31250 1 0 DR 0
|
|
E5 1 33125 33125 1 0 DR 0
|
|
E6 0 41250 41250 1 0 DR 0
|
|
E7 1 43125 43125 1 0 DR 0
|
|
E8 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_CYC_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 3125 3125 1 0 DR 0
|
|
E1 1 43125 43125 1 0 DR 0
|
|
E2 0 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_ERR_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 43125 43125 1 0 DR 0
|
|
E1 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_RTY_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 43125 43125 1 0 DR 0
|
|
E1 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
MARKER MARK1
|
|
ATTACH dwb_SEL_O NULL S6
|
|
TIME 17500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK2
|
|
ATTACH dwb_STB_O NULL S7
|
|
TIME 27500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK3
|
|
ATTACH dwb_STB_O NULL S7
|
|
TIME 37500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK0
|
|
ATTACH dwb_CLK_I NULL S1
|
|
TIME 7494.285714
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
O l e
|
|
C o m p O b j h j i O b j I n f o k C O N T E N T S AN
|
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
|
a " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` d e f g h i j k l m n o p q r s t u v w x y z { | } ~ Timing Diagram Editor v7.1g - Output File
|
|
|
|
PROJECT
|
|
BaseTimeUnit 1
|
|
DisplayTimeUnit 2
|
|
TextGridX 625.000000
|
|
TextGridY 6
|
|
EdgeGridX 625.000000
|
|
ImportStartTime 0.000000
|
|
ImportEndTime 281474976710656.000000
|
|
TimePerPixel 61.428571
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
|
ColWidths 144,216,288,423,488
|
|
ScrollPos 0.000000,0.000000,0.000000
|
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
|
SigLabelFontHeight 10
|
|
LabelHeight 12
|
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
|
LibPath
|
|
EntireTime YES
|
|
PrintTimeSpecified NO
|
|
FromTime 0
|
|
ToTime 53.75
|
|
AllSignals YES
|
|
CurrSelSigs NO
|
|
PrintTo 2
|
|
PrintFileName C:\DOCS\wb_writeblock_typ.wmf
|
|
PreviewInterchange YES
|
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
|
PrintTimeLine NO
|
|
PrintBorderBox YES
|
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
|
AddPreviewToEPS NO
|
|
PreviewRes 150
|
|
MarginLR 1.25
|
|
MifImageWidth 6.00
|
|
MarginTB Auto
|
|
Header %d %t;%f;%p
|
|
Footer
|
|
ScaleHorz 100
|
|
ScaleVert 100
|
|
ScaleHPage 1
|
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
|
DefaultClock Unclocked
|
|
DefaultEdgeLevel neg
|
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
|
DefaultClockEnable Not Used
|
|
DefaultClockToOutLH 0
|
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
|
DefaultHold 0
|
|
DefaultRegStartupState unknown
|
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
|
DefaultAsyncSetClear True
|
|
DefaultActiveLowClockEnable True
|
|
SigLabelFontHeight 10
|
|
PROPS!
|
|
!
|
|
|
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
|
DrawWndFont DEFAULT
|
|
DrawWndColor DEFAULT
|
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
|
LabelWndColor DEFAULT
|
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
|
SignalColor 2
|
|
LabelOffset 2
|
|
BusDisplay 0
|
|
WaveFormWidth 0.500000
|
|
WaveFormColor 0
|
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
|
SlantAngle 75
|
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
|
!
|
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
|
FilesInsideDiagramModelDeclarationSection
|
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
|
VerboseSequenceVerification 0
|
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
|
DefaultCycleClock Unclocked
|
|
DefaultCycleEdge neg
|
|
!
|
|
|
|
MACROS
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CLOCK CLK_RISC
|
|
PERIODE 2.5
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL HIGH
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 0 1 0 2 0 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION internal
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
!
|
|
|
|
CLOCK dwb_CLK_I
|
|
PERIODE 5
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL LOW
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION input
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
!
|
|
|
|
SIGNAL dwb_ADR_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 V -1 -1 1 0 DR 0
|
|
E1 X 3123 3123 1 0 DR 0
|
|
E2 V 13125 13125 A0 1 0 DR 0
|
|
E3 X 13625 13625 1 0 DR 0
|
|
E4 V 23125 23125 A4 1 0 DR 0
|
|
E5 X 23625 23625 1 0 DR 0
|
|
E6 V 33125 33125 A8 1 0 DR 0
|
|
E7 X 33625 33625 1 0 DR 0
|
|
E8 V 43125 43125 A12 1 0 DR 0
|
|
E9 X 43750 43750 1 0 DR 0
|
|
E10 V 53125 53125 A0 1 0 DR 0
|
|
E11 X 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_DAT_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 X 11250 11250 1 0 DR 0
|
|
E1 V 13125 13125 D0 1 0 DR 0
|
|
E2 X 21250 21250 1 0 DR 0
|
|
E3 V 23125 23125 D4 1 0 DR 0
|
|
E4 X 31250 31250 1 0 DR 0
|
|
E5 V 33125 33125 D8 1 0 DR 0
|
|
E6 X 41250 41250 1 0 DR 0
|
|
E7 V 43125 43125 D12 1 0 DR 0
|
|
E8 X 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_DAT_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 3125 3125 1 0 DR 0
|
|
E1 V 3126 3126 D0 1 0 DR 0
|
|
E2 X 43125 43125 1 0 DR 0
|
|
E3 V 53124 53124 D0 1 0 DR 0
|
|
E4 X 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_WE_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 3126 3126 1 0 DR 0
|
|
E1 0 13125 13125 1 0 DR 0
|
|
E2 X 13625 13625 1 0 DR 0
|
|
E3 0 23125 23125 1 0 DR 0
|
|
E4 X 23625 23625 1 0 DR 0
|
|
E5 0 33125 33125 1 0 DR 0
|
|
E6 X 33750 33750 1 0 DR 0
|
|
E7 0 43125 43125 1 0 DR 0
|
|
E8 1 53125 53125 1 0 DR 0
|
|
E9 0 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_SEL_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 3
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 3123 3123 1 0 DR 0
|
|
E1 V 13125 13125 Valid 1 0 DR 0
|
|
E2 X 13625 13625 1 0 DR 0
|
|
E3 V 23125 23125 Valid 1 0 DR 0
|
|
E4 X 23625 23625 1 0 DR 0
|
|
E5 V 33125 33125 Valid 1 0 DR 0
|
|
E6 X 33625 33625 1 0 DR 0
|
|
E7 V 43125 43125 Valid 1 0 DR 0
|
|
E8 X 43750 43750 1 0 DR 0
|
|
E9 V 53124 53124 Valid 1 0 DR 0
|
|
E10 X 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_STB_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 3750 3750 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 13625 13625 1 0 DR 0
|
|
E3 1 23125 23125 1 0 DR 0
|
|
E4 0 23625 23625 1 0 DR 0
|
|
E5 1 33125 33125 1 0 DR 0
|
|
E6 0 33625 33625 1 0 DR 0
|
|
E7 1 43124 43124 1 0 DR 0
|
|
E8 0 44466 44466 1 0 DR 0
|
|
E9 1 53124 53124 1 0 DR 0
|
|
E10 X 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_ACK_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 11250 11250 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 21250 21250 1 0 DR 0
|
|
E3 1 23125 23125 1 0 DR 0
|
|
E4 0 31250 31250 1 0 DR 0
|
|
E5 1 33125 33125 1 0 DR 0
|
|
E6 0 41250 41250 1 0 DR 0
|
|
E7 1 43124 43124 1 0 DR 0
|
|
E8 0 51875 51875 1 0 DR 0
|
|
E9 1 53124 53124 1 0 DR 0
|
|
E10 X 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_CYC_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 3125 3125 1 0 DR 0
|
|
E1 1 43125 43125 1 0 DR 0
|
|
E2 0 44375 44375 1 0 DR 0
|
|
E3 1 53125 53125 1 0 DR 0
|
|
E4 0 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_ERR_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 53125 53125 1 0 DR 0
|
|
E1 X 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dwb_RTY_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 53125 53125 1 0 DR 0
|
|
E1 X 53750 53750 1 0 DR 0
|
|
!
|
|
|
|
MARKER MARK1
|
|
ATTACH dwb_SEL_O NULL S6
|
|
TIME 17500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK2
|
|
ATTACH dwb_STB_O NULL S7
|
|
TIME 27500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK3
|
|
ATTACH dwb_STB_O NULL S7
|
|
TIME 37500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK0
|
|
ATTACH dwb_CLK_I NULL S1
|
|
TIME 7500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK4
|
|
ATTACH dwb_ADR_O NULL S2
|
|
TIME 47500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
_ 1 0 5 0 0 6 8 7 7 4 n Q<= Kuy O l e
|
|
C o m p O b j m o i O b j I n f o p
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ V !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ V !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
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|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a } D y K _ R e f 5 1 3 3 0 8 5 8 8 t D d t% 0
|
|
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|
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P R I N T r t Tp " # Timing Diagram Editor v7.1g - Output File
|
|
|
|
PROJECT
|
|
BaseTimeUnit 1
|
|
DisplayTimeUnit 2
|
|
TextGridX 625.000000
|
|
TextGridY 6
|
|
EdgeGridX 625.000000
|
|
ImportStartTime 0.000000
|
|
ImportEndTime 281474976710656.000000
|
|
TimePerPixel 50.000000
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
|
ColWidths 144,216,288,423,488
|
|
ScrollPos 0.000000,0.000000,0.000000
|
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
|
SigLabelFontHeight 10
|
|
LabelHeight 12
|
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
|
LibPath
|
|
EntireTime YES
|
|
PrintTimeSpecified NO
|
|
FromTime 0
|
|
ToTime 43.75
|
|
AllSignals YES
|
|
CurrSelSigs NO
|
|
PrintTo 2
|
|
PrintFileName C:\DOCS\wb_fetchblock_typ.wmf
|
|
PreviewInterchange YES
|
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
|
PrintTimeLine NO
|
|
PrintBorderBox YES
|
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
|
AddPreviewToEPS NO
|
|
PreviewRes 150
|
|
MarginLR 1.25
|
|
MifImageWidth 6.00
|
|
MarginTB Auto
|
|
Header %d %t;%f;%p
|
|
Footer
|
|
ScaleHorz 100
|
|
ScaleVert 100
|
|
ScaleHPage 1
|
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
|
DefaultClock Unclocked
|
|
DefaultEdgeLevel neg
|
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
|
DefaultClockEnable Not Used
|
|
DefaultClockToOutLH 0
|
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
|
DefaultHold 0
|
|
DefaultRegStartupState unknown
|
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
|
DefaultAsyncSetClear True
|
|
DefaultActiveLowClockEnable True
|
|
SigLabelFontHeight 10
|
|
PROPS!
|
|
!
|
|
|
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
|
DrawWndFont DEFAULT
|
|
DrawWndColor DEFAULT
|
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
|
LabelWndColor DEFAULT
|
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
|
SignalColor 2
|
|
LabelOffset 2
|
|
BusDisplay 0
|
|
WaveFormWidth 0.500000
|
|
WaveFormColor 0
|
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
|
SlantAngle 75
|
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
|
!
|
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
|
FilesInsideDiagramModelDeclarationSection
|
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
|
VerboseSequenceVerification 0
|
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
|
DefaultCycleClock Unclocked
|
|
DefaultCycleEdge neg
|
|
!
|
|
|
|
MACROS
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$iwb_CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$iwb_CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$iwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CLOCK CLK_RISC
|
|
PERIODE 2.5
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL HIGH
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 0 1 0 2 0 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION internal
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
!
|
|
|
|
CLOCK iwb_CLK_I
|
|
PERIODE 5
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL LOW
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION input
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
!
|
|
|
|
SIGNAL iwb_ADR_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 V -1 -1 1 0 DR 0
|
|
E1 X 3125 3125 1 0 DR 0
|
|
E2 V 3126 3126 A0 1 0 DR 0
|
|
E3 X 3750 3750 1 0 DR 0
|
|
E4 V 13125 13125 A0 1 0 DR 0
|
|
E5 X 13625 13625 1 0 DR 0
|
|
E6 V 23125 23125 A4 1 0 DR 0
|
|
E7 X 23625 23625 1 0 DR 0
|
|
E8 V 33125 33125 A8 1 0 DR 0
|
|
E9 X 33625 33625 1 0 DR 0
|
|
E10 V 43125 43125 A12 1 0 DR 0
|
|
E11 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL iwb_DAT_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 X 11250 11250 1 0 DR 0
|
|
E1 V 13125 13125 D0 1 0 DR 0
|
|
E2 X 21250 21250 1 0 DR 0
|
|
E3 V 23125 23125 D4 1 0 DR 0
|
|
E4 X 31250 31250 1 0 DR 0
|
|
E5 V 33125 33125 D8 1 0 DR 0
|
|
E6 X 41250 41250 1 0 DR 0
|
|
E7 V 43125 43125 D12 1 0 DR 0
|
|
E8 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL iwb_DAT_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL iwb_WE_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 3125 3125 1 0 DR 0
|
|
E1 1 3126 3126 1 0 DR 0
|
|
E2 0 13125 13125 1 0 DR 0
|
|
E3 X 13625 13625 1 0 DR 0
|
|
E4 0 23125 23125 1 0 DR 0
|
|
E5 X 23625 23625 1 0 DR 0
|
|
E6 0 33125 33125 1 0 DR 0
|
|
E7 X 33625 33625 1 0 DR 0
|
|
E8 0 43125 43125 1 0 DR 0
|
|
E9 X 43625 43625 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL iwb_SEL_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 3
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 V 0 0 Valid 1 0 DR 0
|
|
E1 X 3750 3750 1 0 DR 0
|
|
E2 V 13125 13125 Valid 1 0 DR 0
|
|
E3 X 13625 13625 1 0 DR 0
|
|
E4 V 23125 23125 Valid 1 0 DR 0
|
|
E5 X 23625 23625 1 0 DR 0
|
|
E6 V 33125 33125 Valid 1 0 DR 0
|
|
E7 X 33625 33625 1 0 DR 0
|
|
E8 V 43125 43125 Valid 1 0 DR 0
|
|
E9 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL iwb_STB_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 3750 3750 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 13625 13625 1 0 DR 0
|
|
E3 1 23125 23125 1 0 DR 0
|
|
E4 0 23625 23625 1 0 DR 0
|
|
E5 1 33125 33125 1 0 DR 0
|
|
E6 0 33625 33625 1 0 DR 0
|
|
E7 1 43125 43125 1 0 DR 0
|
|
E8 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL iwb_ACK_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 11250 11250 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 21250 21250 1 0 DR 0
|
|
E3 1 23125 23125 1 0 DR 0
|
|
E4 0 31250 31250 1 0 DR 0
|
|
E5 1 33125 33125 1 0 DR 0
|
|
E6 0 41250 41250 1 0 DR 0
|
|
E7 1 43125 43125 1 0 DR 0
|
|
E8 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL iwb_CYC_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 3125 3125 1 0 DR 0
|
|
E1 1 43125 43125 1 0 DR 0
|
|
E2 0 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL iwb_ERR_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 43125 43125 1 0 DR 0
|
|
E1 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL iwb_RTY_I
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 43125 43125 1 0 DR 0
|
|
E1 X 43750 43750 1 0 DR 0
|
|
!
|
|
|
|
MARKER MARK1
|
|
ATTACH iwb_SEL_O NULL S6
|
|
TIME 17500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK2
|
|
ATTACH iwb_STB_O NULL S7
|
|
TIME 27500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK3
|
|
ATTACH iwb_STB_O NULL S7
|
|
TIME 37500.000000
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
MARKER MARK0
|
|
ATTACH iwb_CLK_I NULL S1
|
|
TIME 7494.285714
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
FQ/ %8 & " WMFC cR P3 PS x U > F Q/ EMF PS X V I S I O D r a w i n g
|
|
Y = & % % V 0 J J J J % ( % R L A r i a l d x _VarMemberFlags VB_Var@ ? > = < ; : 9 8 % T + . g = *A*A+ .
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|
L ` C o n t e x t I D T | 5 > \ M *A*A5 > L \ ( 4 b i t s ) & % % V 0 } J J }J } J % ( % R L A r i a l % T . < = *A*A . L p P a g e I n d e x L e v e l 1 T | > M *A*A > L \ ( 8 b i t s ) & % % V 0 } i J }J iJ i } }J % ( % R L A r i a l % T . ( = *A*A . L p P a g e I n d e x L e v e l 2 T > M *A*A > L ` ( 1 1 b i t s ) & % % V 0 i U J iJ UJ U i iJ % ( % R L A r i a l % T . = *A*A . L d P a g e O f f s e t
|
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T > M *A*A > L ` ( 1 3 b i t s ) R L A r i a l % T X " *A*A L P 3 5 R L A r i a l % ( % T X " *A*A L P 3 1 %
( R L A r i a l % T X b o " *A*Ab L P 2 4 %
( R L A r i a l ' x x
' #
|
|
P # Arial Arial % T X " *A*A L P 2 3 R L A r i a l P # Ari rial c,,y MMHM,,, % T X Q ^ " *A*AQ L P 1 3 %
( R L A r i a l r,HM(%MMM@MMm,BBBc
|
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H
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' #
|
|
P # Arial Arial & " WMFC P PS % ( % % T . *A*A L d P a g e O f f s e t
|
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T / > *A*A / L ` ( 1 3 b i t s ) %
( R L A r i a l rial Arial G@ G % T X *A*A L P 3 4 R L A r i a l % ( % T X O \ *A*AO L P 1 3 %
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( R L A r i a l % T T F L *A*AF L P 0 & % W $ J J % ( % % V , & % % V & M & ( - 5 @ L Z h v ! . : Cv Jh MZ ML J@ C5 :- .( !& % ( R L A r i a l % ( % R L A r i a l % T A *A*AA
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( % R L A r i a l % T T *A*A L P + & % W ( a a a % ( % % V , & % % V 0 M M M M % ( & % % V 0 M M M M% ( %
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%
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W , I J I I J I [ I [ I % (
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% % V , E N N I E N &
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%
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% W , a i y a y iy ia % (
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( %
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|
|
. +
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Context ID 2
|
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> 5 (4 bits) - - $ J }J } J - -
Arial ????????????????????????? - " 2
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. Page Index Level 1 2
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Arial ????????????????????????? - " 2
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35
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Page Offset
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/ (13 bits) -
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34
Arial ????????????????????????? - -
|
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Arial ???????????? ???????????? -
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2
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F 0 - % J - - - $ -
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Page Table 2
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; depending on 2
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- - - Arial ?? ???????? ????? - 2
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+ -
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Arial &???l ?? ? -
2
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l PTE1 - - $ MMM -
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255
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|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
|
LabelWndColor DEFAULT
|
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
|
SignalColor 2
|
|
LabelOffset 4
|
|
BusDisplay 0
|
|
WaveFormWidth 0.500000
|
|
WaveFormColor 0
|
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
|
SlantAngle 75
|
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
|
!
|
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
|
FilesInsideDiagramModelDeclarationSection
|
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
|
VerboseSequenceVerification 0
|
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
|
DefaultCycleClock Unclocked
|
|
DefaultCycleEdge neg
|
|
!
|
|
|
|
MACROS
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CLOCK clk_risc
|
|
PERIODE 1
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL LOW
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION input
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E5 1 2500 2500 1 0 DR 0
|
|
E6 0 3000 3000 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_adr_i
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 X 750 750 1 0 DR 0
|
|
E1 V 1750 1750 A20 1 0 DR 0
|
|
E2 V 3750 3750 A100 1 0 DR 0
|
|
E3 X 5750 5750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_dat_i
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 X 750 750 1 0 DR 0
|
|
E1 V 1750 1750 D20 1 0 DR 0
|
|
E2 X 5750 5750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_dat_o
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
LSB 0
|
|
MSB 31
|
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
|
E0 V -1 -1 1 0 DR 0
|
|
E1 V 750 750 PC 1 0 DR 0
|
|
E2 X 2750 2750 1 0 DR 0
|
|
E3 V 3750 3750 D100 1 0 DR 0
|
|
E4 V 4750 4750 L/S EA 1 0 DR 0
|
|
E5 V 5750 5750 LOAD DATA 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_op_i
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 3
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 V 750 750 READ PC 0x0 1 0 DR 0
|
|
E1 V 1750 1750 WRITE SPR 0x5 1 0 DR 0
|
|
E2 V 3750 3750 READ SPR == 0x4 1 0 DR 0
|
|
E3 V 4750 4750 READ LSEA 0x1 1 0 DR 0
|
|
E4 V 5750 5750 READ LDAT 0x2 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_stall_i
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 5750 5750 1 0 DR 0
|
|
!
|
|
|
|
O l e
|
|
C o m p O b j i O b j I n f o C O N T E N T S < % Timing Diagram Editor v7.1g - Output File
|
|
|
|
PROJECT
|
|
BaseTimeUnit 1
|
|
DisplayTimeUnit 2
|
|
TextGridX 250.000000
|
|
TextGridY 6
|
|
EdgeGridX 250.000000
|
|
ImportStartTime 0.000000
|
|
ImportEndTime 281474976710656.000000
|
|
TimePerPixel 5.428571
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
|
ColWidths 144,216,288,423,488
|
|
ScrollPos 0.000000,0.000000,0.000000
|
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
|
SigLabelFontHeight 10
|
|
LabelHeight 12
|
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
|
LibPath
|
|
EntireTime YES
|
|
PrintTimeSpecified NO
|
|
FromTime 0
|
|
ToTime 4.75
|
|
AllSignals YES
|
|
CurrSelSigs NO
|
|
PrintTo 2
|
|
PrintFileName C:\DOCS\untitled1.wmf
|
|
PreviewInterchange YES
|
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
|
PrintTimeLine NO
|
|
PrintBorderBox YES
|
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
|
AddPreviewToEPS NO
|
|
PreviewRes 150
|
|
MarginLR 1.25
|
|
MifImageWidth 6.00
|
|
MarginTB Auto
|
|
Header %d %t;%f;%p
|
|
Footer
|
|
ScaleHorz 100
|
|
ScaleVert 100
|
|
ScaleHPage 1
|
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
|
DefaultClock Unclocked
|
|
DefaultEdgeLevel neg
|
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
|
DefaultClockEnable Not Used
|
|
DefaultClockToOutLH 0
|
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
|
DefaultHold 0
|
|
DefaultRegStartupState unknown
|
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
|
DefaultAsyncSetClear True
|
|
DefaultActiveLowClockEnable True
|
|
SigLabelFontHeight 10
|
|
PROPS!
|
|
!
|
|
|
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
|
DrawWndFont DEFAULT
|
|
DrawWndColor DEFAULT
|
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
|
LabelWndColor DEFAULT
|
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
|
SignalColor 2
|
|
LabelOffset 2
|
|
BusDisplay 0
|
|
WaveFormWidth 1.000000
|
|
WaveFormColor 0
|
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
|
SlantAngle 75
|
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
|
!
|
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
|
FilesInsideDiagramModelDeclarationSection
|
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
|
VerboseSequenceVerification 0
|
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
|
DefaultCycleClock Unclocked
|
|
DefaultCycleEdge neg
|
|
!
|
|
|
|
MACROS
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
|
CLOCK clk_risc
|
|
PERIODE 1
|
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL LOW
|
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
|
JFALLE 0
|
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
|
DIRECTION input
|
|
MASTERCLOCK None
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
!
|
|
|
|
SIGNAL dbg_wp_o[11]
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 1750 1750 1 0 DR 0
|
|
E1 1 3750 3750 1 0 DR 0
|
|
E2 0 4750 4750 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_bp_o
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 2750 2750 1 0 DR 0
|
|
E1 1 4750 4750 If Enabled 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL dbg_ewt_i
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
|
VHDLCode
|
|
PROPS!
|
|
E0 0 1250 1250 1 0 DR 0
|
|
E1 1 3750 3750 1 0 DR 0
|
|
E2 0 4750 4750 1 0 DR 0
|
|
!
|
|
|
|
MARKER MARK10
|
|
ATTACH dbg_wp_o[11] NULL S1
|
|
TIME 1610.903040
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT aaa
|
|
!
|
|
|
|
MARKER MARK20
|
|
ATTACH dbg_bp_o NULL S2
|
|
TIME 2644.928640
|
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
|
REPEATNUMBER
|
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
|
|
|
_ 1 0 4 7 9 8 3 6 8 0 F @ N O l e
|
|
P R I N T P L C o m p O b j q 1 h& & " WMFC C 8 x Z j 1 EMF 8 ~ X V I S I O D r a w i n g
|
|
\ l & % '
|
|
% V 0 Z j jZjZ j% ( % ( % R L A r i a l d x % T 8 *A*A
L h O p e n R I S C 1 2 0 0
& % ' B
|
|
% V 0 r r T TrTrr r T% ( % ( % R L A r i a l X<( % T x ` *A*A L \ C P U / D S P & % ' B
|
|
% V 0 5 55 % ( % ( % R L A r i a l % T p *A*A L X D C a c h e
T ` *A*A L T 8 K B
& % ' B
|
|
% V 0 5 T T5T5T% ( % ( % R L A r i a l CA CA ! CA CA 0 ! @CA CA% T d = W *A*A = L T D M M U & % ' B
|
|
% V 0 ' T ' T T ' ' T% ( % ( % R L A r i a l ?f b`CAfc`;@AA a`b`CAfc`<PA b`CAgc`=@AA a`b`CAgc`>@A a` b`CAec`RAA lCA2A % T ` e = W *A*Ae = L T P I C & % ' B
|
|
% V 0 ' ' ' ' % ( % ( % R L A r i a l b` CAfc`;@AA a`b` CAfc`<PA b` CAgc`=@AA a`b` CAgc`>@AA a` b` CAec`RAA P 2A2A ! CA CA CA 0 ! CA@CAdCA P ! CA CA % T 5 *A*A5
|
|
L ` T I C K T I M E R & % ' B
|
|
% V 0 ' r ' r ' r ' % ( % ( % R L A r i a l b`PCAec`RAA A pb`0b` A ! CA CACA CA ! @ 2A CATCA ! CA@CACA& CA ! CA CA ! @CA@CA % T l L *A*AL L X D E B U G & % ' B
|
|
% V 0 ' \ ' \ \ ' ' \ % ( % ( %
( % R L A r i a l ? ? b`CAfc`CAA CACA$pCACAdCA 1 CA2AdCA ! vCAvCAČCA @ ! vCA0CA CA% CA ` ! CA CA % T p A E _ *A*AA E L X P O W E R M & % ' B
|
|
% V 0 r 5 5 5r r % ( % ( R L A r i a l
|
|
|
|
b`CAec`RAA @ 2A2A ! CAvCACA @ ! vCA0CA CA$ CA ` ! @CA@CA ! `CA`CA ! CACA b`b` % ( % R L A r i a l f b`CAfc`;@AA a`b`CAfc`<PA b`CAgc`=@AA a`b`CAgc`>@A a` b`CAec`RAA ! CA CA CA% T p
|
|
*A*A L X I C a c h e
T ` *A*A L T 8 K B
& % '
|
|
B
|
|
%
|
|
V 0 5 \ \ 5\ 5 \ % ( % (
|
|
R L
|
|
A r i a l v ' h x @ @ @ @ @ @ ( x @ @ ? x(L @ v % %
|
|
( % R L A r i a l PX 0 X @
|
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l * 0 k k 0 0 0 * 0 k k 0 0 0 0 0 * 0 k k 0 t 0 t 0 t 0 t 0 t 0 t 0 t * 0 k k 0 = 0 = ( 0 = ( 0 = ( 0 = ( 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = '0 = 0 = 0 = 0 = * 0 k k 0 0 0 * 0 k k 0 f 0 f 0 f * 0 k k 0 0 & 0 & 0 & 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 '0 0 0 0 0 g g * 0 * 0 * 0 0 # 0 # 0 # 0 # 0 # 0 # 0 # '0 # 0 # 0 # 0 # 0 # * 0 0 0 0 0 '0 0 0 0 0 0 0 0 '0 0 0 0 0 * 0 0 ˜ 0 ˜ 0 ˜ * 0 0 0 0 * 0 0 0 0 * 0 0 0 0 * 0 0 0 * 0 * 0
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|
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k k 0 0 0 * 0 k k 0 > 0 > 0 > 0 g g 0 * 0 0 0 0 * 0 0 0 0 0 '0 0 0 0 * 0 0 0 0 * 0 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ 0 ͱ '0 ͱ 0 ͱ 0 ͱ 0 ͱ * 0 0 0 0 0 0 0 0 * 0 0 Ƹ 0 Ƹ 0 Ƹ * 0 0 p 0 p 0 p * 0 0 S 0 S 0 S * 0 0 0 0 * 0 0 ƻ 0 ƻ 0 ƻ * 0 0 0 0 * 0
|
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0 Z 0 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z '0 Z 0 Z 0 Z 0 Z * 0 0 0 0 0 g g 0 * 0 0 0 0 * 0 0 0 0 0 '0 0 0 0 * 0 0 0 0 * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 '0 0 0 0 0 * 0 0 m 0 m 0 m 0 m 0 m 0 m 0 m * 0 0 0 0 * 0 0 0 0 0 0 0 * 0 0 0 0 * 0 0 0 0 * 0 0 0 0 * 0 0 0 0 * 0
|
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0 0 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 '0 0 * 0 Q Q 0 0 0 0 i i 0 0 0 0 0 0 i i 0 0 0 0 0 0 i i 0 * 0 0 0 0 * 0 0 0 0 0 0 0 0 * 0 0 0 0 0 0 * 0 0 0 0 0 0 0 0 * 0 0 + 0 0 + * 0 0 ~ 0 ~ 0 ~ 0 i i 0 0 0 * 0 0 ( 0 0 ( * 0 0 \ 0 0 \ 0 \ 0 \ 0
|
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i i 0 C 0 C 0 C * 0 C C 0 0 0 0 0 0 * 0 * 0 C C 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' '0 ' 0 ' 0 ' 0 ' * 0 C * 0 C C 0 ~ 0 ~ 0 ~ '0 ~ 0 ~ 0 ~ 0 ~ 0 ~ 0 ~ * 0 C C 0 j 0 j 0 j 0 j 0 j 0 j
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OpenRISC 1200 IP Core Title 8 @ _PID_HLINKS A 4 7 $ _ T o c 5 1 1 1 6 1 5 6 4 7 _ T o c 5 1 1 1 6 1 5 6 3 7 _ T o c 5 1 1 1 6 1 5 6 2 7 _ T o c 5 1 1 1 6 1 5 6 1 7 _ T o c 5 1 1 1 6 1 5 6 0 7 _ T o c 5 1 1 1 6 1 5 5 9 7 _ T o c 5 1 1 1 6 1 5 5 8 7 _ T o c 5 1 1 1 6 1 5 5 7 7 _ T o c 5 1 1 1 6 1 5 5 6 7 _ T o c 5 1 1 1 6 1 5 5 5 7 _ T o c 5 1 1 1 6 1 5 5 4 7 _ T o c 5 1 1 1 6 1 5 5 3 7 _ T o c 5 1 1 1 6 1 5 5 2 7 _ T o c 5 1 1 1 6 1 5 5 1 7 _ T o c 5 1 1 1 6 1 5 5 0 7 _ T o c 5 1 1 1 6 1 5 4 9 7 _ T o c 5 1 1 1 6 1 5 4 8 7 _ T o c 5 1 1 1 6 1 5 4 7 7 _ T o c 5 1 1 1 6 1 5 4 6 7 _ T o c 5 1 1 1 6 1 5 4 5 7 _ T o c 5 1 1 1 6 1 5 4 4 7 _ T o c 5 1 1 1 6 1 5 4 3 7 _ T o c 5 1 1 1 6 1 5 4 2 7 _ T o c 5 1 1 1 6 1 5 4 1 7 _ T o c 5 1 1 1 6 1 5 4 0 7 _ T o c 5 1 1 1 6 1 5 3 9 7 _ T o c 5 1 1 1 6 1 5 3 8 7 _ T o c 5 1 1 1 6 1 5 3 7 7 | _ T o c 5 1 1 1 6 1 5 3 6 7 v _ T o c 5 1 1 1 6 1 5 3 5 7 p _ T o c 5 1 1 1 6 1 5 3 4 7 g _ T o c 5 1 1 1 6 1 5 3 3 7 a _ T o c 5 1 1 1 6 1 5 3 2 7 [ _ T o c 5 1 1 1 6 1 5 3 1 7 U _ T o c 5 1 1 1 6 1 5 3 0 7 O _ T o c 5 1 1 1 6 1 5 2 9 7 I _ T o c 5 1 1 1 6 1 5 2 8 7 C _ T o c 5 1 1 1 6 1 5 2 7 7 = _ T o c 5 1 1 1 6 1 5 2 6 7 7 _ T o c 5 1 1 1 6 1 5 2 5 7 1 _ T o c 5 1 1 1 6 1 5 2 4 7 + _ T o c 5 1 1 1 6 1 5 2 3 7 % _ T o c 5 1 1 1 6 1 5 2 2 7 _ T o c 5 1 1 1 6 1 5 2 1 7 _ T o c 5 1 1 1 6 1 5 2 0 7 _ T o c 5 1 1 1 6 1 5 1 9 7
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