//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's CPU ////
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//// OR1200's CPU ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, ////
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//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, ////
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//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. ////
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//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2004/05/09 19:49:04 lampret
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// Revision 1.15 2004/05/09 19:49:04 lampret
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// Added some l.cust5 custom instructions as example
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// Added some l.cust5 custom instructions as example
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//
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//
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// Revision 1.14 2004/04/05 08:29:57 lampret
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// Revision 1.14 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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//
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//
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// Revision 1.12.4.2 2004/02/11 01:40:11 lampret
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// Revision 1.12.4.2 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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//
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// Revision 1.12.4.1 2003/12/09 11:46:48 simons
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// Revision 1.12.4.1 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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//
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// Revision 1.12 2002/09/07 05:42:02 lampret
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// Revision 1.12 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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//
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// Revision 1.11 2002/08/28 01:44:25 lampret
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// Revision 1.11 2002/08/28 01:44:25 lampret
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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//
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//
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// Revision 1.10 2002/07/14 22:17:17 lampret
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// Revision 1.10 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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//
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// Revision 1.9 2002/03/29 16:29:37 lampret
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// Revision 1.9 2002/03/29 16:29:37 lampret
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// Fixed some ports in instnatiations that were removed from the modules
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// Fixed some ports in instnatiations that were removed from the modules
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//
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//
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// Revision 1.8 2002/03/29 15:16:54 lampret
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// Revision 1.8 2002/03/29 15:16:54 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.7 2002/02/11 04:33:17 lampret
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// Revision 1.7 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.6 2002/02/01 19:56:54 lampret
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// Revision 1.6 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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//
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//
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// Revision 1.5 2002/01/28 01:15:59 lampret
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// Revision 1.5 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.4 2002/01/18 14:21:43 lampret
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// Revision 1.4 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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// Fixed 'the NPC single-step fix'.
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//
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//
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.19 2001/11/30 18:59:47 simons
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// Revision 1.19 2001/11/30 18:59:47 simons
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// *** empty log message ***
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// *** empty log message ***
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//
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//
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// Revision 1.18 2001/11/23 21:42:31 simons
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// Revision 1.18 2001/11/23 21:42:31 simons
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// Program counter divided to PPC and NPC.
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// Program counter divided to PPC and NPC.
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//
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//
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// Revision 1.17 2001/11/23 08:38:51 lampret
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// Revision 1.17 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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// Changed DSR/DRR behavior and exception detection.
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//
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//
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// Revision 1.16 2001/11/20 00:57:22 lampret
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// Revision 1.16 2001/11/20 00:57:22 lampret
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// Fixed width of du_except.
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// Fixed width of du_except.
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//
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//
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// Revision 1.15 2001/11/18 09:58:28 lampret
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// Revision 1.15 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
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// Fixed some l.trap typos.
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//
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//
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// Revision 1.14 2001/11/18 08:36:28 lampret
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// Revision 1.14 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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// For GDB changed single stepping and disabled trap exception.
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//
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//
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// Revision 1.13 2001/11/13 10:02:21 lampret
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// Revision 1.13 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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//
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// Revision 1.12 2001/11/12 01:45:40 lampret
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// Revision 1.12 2001/11/12 01:45:40 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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//
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// Revision 1.11 2001/11/10 03:43:57 lampret
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// Revision 1.11 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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// Fixed exceptions.
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//
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.9 2001/10/14 13:12:09 lampret
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// Revision 1.9 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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// no message
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//
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//
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// Revision 1.4 2001/08/17 08:01:19 lampret
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// Revision 1.4 2001/08/17 08:01:19 lampret
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// IC enable/disable.
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// IC enable/disable.
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//
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//
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// Revision 1.3 2001/08/13 03:36:20 lampret
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// Revision 1.3 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_cpu(
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module or1200_cpu(
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// Clk & Rst
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// Clk & Rst
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clk, rst,
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clk, rst,
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// Insn interface
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// Insn interface
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ic_en,
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ic_en,
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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immu_en,
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immu_en,
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// Debug unit
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// Debug unit
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ex_insn, ex_freeze, id_pc, branch_op,
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ex_insn, ex_freeze, id_pc, branch_op,
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spr_dat_npc, rf_dataw,
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spr_dat_npc, rf_dataw,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt,
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du_except, du_dat_cpu,
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du_except, du_dat_cpu,
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|
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// Data interface
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// Data interface
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dc_en,
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dc_en,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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dmmu_en,
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dmmu_en,
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// Interrupt & tick exceptions
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// Interrupt & tick exceptions
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sig_int, sig_tick,
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sig_int, sig_tick,
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|
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// SPR interface
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// SPR interface
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supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
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supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
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spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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//
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//
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// I/O ports
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// I/O ports
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//
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//
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//
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//
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// Clk & Rst
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// Clk & Rst
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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//
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//
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// Insn (IC) interface
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// Insn (IC) interface
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//
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//
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output ic_en;
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output ic_en;
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output [31:0] icpu_adr_o;
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output [31:0] icpu_adr_o;
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output icpu_cycstb_o;
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output icpu_cycstb_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_tag_o;
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output [3:0] icpu_tag_o;
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input [31:0] icpu_dat_i;
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input [31:0] icpu_dat_i;
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input icpu_ack_i;
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input icpu_ack_i;
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input icpu_rty_i;
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input icpu_rty_i;
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input icpu_err_i;
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input icpu_err_i;
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input [31:0] icpu_adr_i;
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input [31:0] icpu_adr_i;
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input [3:0] icpu_tag_i;
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input [3:0] icpu_tag_i;
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|
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//
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//
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// Insn (IMMU) interface
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// Insn (IMMU) interface
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//
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//
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output immu_en;
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output immu_en;
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//
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//
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// Debug interface
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// Debug interface
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//
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//
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output [31:0] ex_insn;
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output [31:0] ex_insn;
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output ex_freeze;
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output ex_freeze;
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output [31:0] id_pc;
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output [31:0] id_pc;
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output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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|
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input du_stall;
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input du_stall;
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input [dw-1:0] du_addr;
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input [dw-1:0] du_addr;
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input [dw-1:0] du_dat_du;
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input [dw-1:0] du_dat_du;
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input du_read;
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input du_read;
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input du_write;
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input du_write;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input du_hwbkpt;
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input du_hwbkpt;
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output [12:0] du_except;
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output [12:0] du_except;
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output [dw-1:0] du_dat_cpu;
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output [dw-1:0] du_dat_cpu;
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output [dw-1:0] rf_dataw;
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output [dw-1:0] rf_dataw;
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|
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//
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//
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// Data (DC) interface
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// Data (DC) interface
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//
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//
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output [31:0] dcpu_adr_o;
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output [31:0] dcpu_adr_o;
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output dcpu_cycstb_o;
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output dcpu_cycstb_o;
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output dcpu_we_o;
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output dcpu_we_o;
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output [3:0] dcpu_sel_o;
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output [3:0] dcpu_sel_o;
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output [3:0] dcpu_tag_o;
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output [3:0] dcpu_tag_o;
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output [31:0] dcpu_dat_o;
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output [31:0] dcpu_dat_o;
|
input [31:0] dcpu_dat_i;
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input [31:0] dcpu_dat_i;
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input dcpu_ack_i;
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input dcpu_ack_i;
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input dcpu_rty_i;
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input dcpu_rty_i;
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input dcpu_err_i;
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input dcpu_err_i;
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input [3:0] dcpu_tag_i;
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input [3:0] dcpu_tag_i;
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output dc_en;
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output dc_en;
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|
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//
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//
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// Data (DMMU) interface
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// Data (DMMU) interface
|
//
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//
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output dmmu_en;
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output dmmu_en;
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|
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//
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//
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// SPR interface
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// SPR interface
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//
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//
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output supv;
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output supv;
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input [dw-1:0] spr_dat_pic;
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input [dw-1:0] spr_dat_pic;
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input [dw-1:0] spr_dat_tt;
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input [dw-1:0] spr_dat_tt;
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input [dw-1:0] spr_dat_pm;
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input [dw-1:0] spr_dat_pm;
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input [dw-1:0] spr_dat_dmmu;
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input [dw-1:0] spr_dat_dmmu;
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input [dw-1:0] spr_dat_immu;
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input [dw-1:0] spr_dat_immu;
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input [dw-1:0] spr_dat_du;
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input [dw-1:0] spr_dat_du;
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output [dw-1:0] spr_addr;
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output [dw-1:0] spr_addr;
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output [dw-1:0] spr_dat_cpu;
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output [dw-1:0] spr_dat_cpu;
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output [dw-1:0] spr_dat_npc;
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output [dw-1:0] spr_dat_npc;
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output [31:0] spr_cs;
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output [31:0] spr_cs;
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output spr_we;
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output spr_we;
|
|
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//
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//
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// Interrupt exceptions
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// Interrupt exceptions
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//
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//
|
input sig_int;
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input sig_int;
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input sig_tick;
|
input sig_tick;
|
|
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//
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//
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// Internal wires
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// Internal wires
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//
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//
|
wire [31:0] if_insn;
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wire [31:0] if_insn;
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wire [31:0] if_pc;
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wire [31:0] if_pc;
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wire [31:2] lr_sav;
|
wire [31:2] lr_sav;
|
wire [aw-1:0] rf_addrw;
|
wire [aw-1:0] rf_addrw;
|
wire [aw-1:0] rf_addra;
|
wire [aw-1:0] rf_addra;
|
wire [aw-1:0] rf_addrb;
|
wire [aw-1:0] rf_addrb;
|
wire rf_rda;
|
wire rf_rda;
|
wire rf_rdb;
|
wire rf_rdb;
|
wire [dw-1:0] simm;
|
wire [dw-1:0] simm;
|
wire [dw-1:2] branch_addrofs;
|
wire [dw-1:2] branch_addrofs;
|
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op;
|
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op;
|
wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
|
wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
|
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
|
wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
|
wire genpc_freeze;
|
wire genpc_freeze;
|
wire if_freeze;
|
wire if_freeze;
|
wire id_freeze;
|
wire id_freeze;
|
wire ex_freeze;
|
wire ex_freeze;
|
wire wb_freeze;
|
wire wb_freeze;
|
wire [`OR1200_SEL_WIDTH-1:0] sel_a;
|
wire [`OR1200_SEL_WIDTH-1:0] sel_a;
|
wire [`OR1200_SEL_WIDTH-1:0] sel_b;
|
wire [`OR1200_SEL_WIDTH-1:0] sel_b;
|
wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
|
wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
|
wire [dw-1:0] rf_dataw;
|
wire [dw-1:0] rf_dataw;
|
wire [dw-1:0] rf_dataa;
|
wire [dw-1:0] rf_dataa;
|
wire [dw-1:0] rf_datab;
|
wire [dw-1:0] rf_datab;
|
wire [dw-1:0] muxed_b;
|
wire [dw-1:0] muxed_b;
|
wire [dw-1:0] wb_forw;
|
wire [dw-1:0] wb_forw;
|
wire wbforw_valid;
|
wire wbforw_valid;
|
wire [dw-1:0] operand_a;
|
wire [dw-1:0] operand_a;
|
wire [dw-1:0] operand_b;
|
wire [dw-1:0] operand_b;
|
wire [dw-1:0] alu_dataout;
|
wire [dw-1:0] alu_dataout;
|
wire [dw-1:0] lsu_dataout;
|
wire [dw-1:0] lsu_dataout;
|
wire [dw-1:0] sprs_dataout;
|
wire [dw-1:0] sprs_dataout;
|
wire [31:0] lsu_addrofs;
|
wire [31:0] lsu_addrofs;
|
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
|
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
|
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
wire [4:0] cust5_op;
|
wire [4:0] cust5_op;
|
wire [5:0] cust5_limm;
|
wire [5:0] cust5_limm;
|
wire flushpipe;
|
wire flushpipe;
|
wire extend_flush;
|
wire extend_flush;
|
wire branch_taken;
|
wire branch_taken;
|
wire flag;
|
wire flag;
|
wire flagforw;
|
wire flagforw;
|
wire flag_we;
|
wire flag_we;
|
wire carry;
|
wire carry;
|
wire cyforw;
|
wire cyforw;
|
wire cy_we;
|
wire cy_we;
|
wire lsu_stall;
|
wire lsu_stall;
|
wire epcr_we;
|
wire epcr_we;
|
wire eear_we;
|
wire eear_we;
|
wire esr_we;
|
wire esr_we;
|
wire pc_we;
|
wire pc_we;
|
wire [31:0] epcr;
|
wire [31:0] epcr;
|
wire [31:0] eear;
|
wire [31:0] eear;
|
wire [`OR1200_SR_WIDTH-1:0] esr;
|
wire [`OR1200_SR_WIDTH-1:0] esr;
|
wire sr_we;
|
wire sr_we;
|
wire [`OR1200_SR_WIDTH-1:0] to_sr;
|
wire [`OR1200_SR_WIDTH-1:0] to_sr;
|
wire [`OR1200_SR_WIDTH-1:0] sr;
|
wire [`OR1200_SR_WIDTH-1:0] sr;
|
wire except_start;
|
wire except_start;
|
wire except_started;
|
wire except_started;
|
wire [31:0] wb_insn;
|
wire [31:0] wb_insn;
|
wire [15:0] spr_addrimm;
|
wire [15:0] spr_addrimm;
|
wire sig_syscall;
|
wire sig_syscall;
|
wire sig_trap;
|
wire sig_trap;
|
wire [31:0] spr_dat_cfgr;
|
wire [31:0] spr_dat_cfgr;
|
wire [31:0] spr_dat_rf;
|
wire [31:0] spr_dat_rf;
|
wire [31:0] spr_dat_npc;
|
wire [31:0] spr_dat_npc;
|
wire [31:0] spr_dat_ppc;
|
wire [31:0] spr_dat_ppc;
|
wire [31:0] spr_dat_mac;
|
wire [31:0] spr_dat_mac;
|
wire force_dslot_fetch;
|
wire force_dslot_fetch;
|
wire no_more_dslot;
|
wire no_more_dslot;
|
wire ex_void;
|
wire ex_void;
|
wire if_stall;
|
wire if_stall;
|
wire id_macrc_op;
|
wire id_macrc_op;
|
wire ex_macrc_op;
|
wire ex_macrc_op;
|
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
wire [31:0] mult_mac_result;
|
wire [31:0] mult_mac_result;
|
wire mac_stall;
|
wire mac_stall;
|
wire [12:0] except_stop;
|
wire [12:0] except_stop;
|
wire genpc_refetch;
|
wire genpc_refetch;
|
wire rfe;
|
wire rfe;
|
wire lsu_unstall;
|
wire lsu_unstall;
|
wire except_align;
|
wire except_align;
|
wire except_dtlbmiss;
|
wire except_dtlbmiss;
|
wire except_dmmufault;
|
wire except_dmmufault;
|
wire except_illegal;
|
wire except_illegal;
|
wire except_itlbmiss;
|
wire except_itlbmiss;
|
wire except_immufault;
|
wire except_immufault;
|
wire except_ibuserr;
|
wire except_ibuserr;
|
wire except_dbuserr;
|
wire except_dbuserr;
|
wire abort_ex;
|
wire abort_ex;
|
|
|
//
|
//
|
// Send exceptions to Debug Unit
|
// Send exceptions to Debug Unit
|
//
|
//
|
assign du_except = except_stop;
|
assign du_except = except_stop;
|
|
|
//
|
//
|
// Data cache enable
|
// Data cache enable
|
//
|
//
|
assign dc_en = sr[`OR1200_SR_DCE];
|
assign dc_en = sr[`OR1200_SR_DCE];
|
|
|
//
|
//
|
// Instruction cache enable
|
// Instruction cache enable
|
//
|
//
|
assign ic_en = sr[`OR1200_SR_ICE];
|
assign ic_en = sr[`OR1200_SR_ICE];
|
|
|
//
|
//
|
// DMMU enable
|
// DMMU enable
|
//
|
//
|
assign dmmu_en = sr[`OR1200_SR_DME];
|
assign dmmu_en = sr[`OR1200_SR_DME];
|
|
|
//
|
//
|
// IMMU enable
|
// IMMU enable
|
//
|
//
|
assign immu_en = sr[`OR1200_SR_IME];
|
assign immu_en = sr[`OR1200_SR_IME];
|
|
|
//
|
//
|
// SUPV bit
|
// SUPV bit
|
//
|
//
|
assign supv = sr[`OR1200_SR_SM];
|
assign supv = sr[`OR1200_SR_SM];
|
|
|
//
|
//
|
// Instantiation of instruction fetch block
|
// Instantiation of instruction fetch block
|
//
|
//
|
or1200_genpc or1200_genpc(
|
or1200_genpc or1200_genpc(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.icpu_adr_o(icpu_adr_o),
|
.icpu_adr_o(icpu_adr_o),
|
.icpu_cycstb_o(icpu_cycstb_o),
|
.icpu_cycstb_o(icpu_cycstb_o),
|
.icpu_sel_o(icpu_sel_o),
|
.icpu_sel_o(icpu_sel_o),
|
.icpu_tag_o(icpu_tag_o),
|
.icpu_tag_o(icpu_tag_o),
|
.icpu_rty_i(icpu_rty_i),
|
.icpu_rty_i(icpu_rty_i),
|
.icpu_adr_i(icpu_adr_i),
|
.icpu_adr_i(icpu_adr_i),
|
|
|
.branch_op(branch_op),
|
.branch_op(branch_op),
|
.except_type(except_type),
|
.except_type(except_type),
|
.except_start(except_start),
|
.except_start(except_start),
|
.except_prefix(sr[`OR1200_SR_EPH]),
|
.except_prefix(sr[`OR1200_SR_EPH]),
|
.branch_addrofs(branch_addrofs),
|
.branch_addrofs(branch_addrofs),
|
.lr_restor(operand_b),
|
.lr_restor(operand_b),
|
.flag(flag),
|
.flag(flag),
|
.taken(branch_taken),
|
.taken(branch_taken),
|
.binsn_addr(lr_sav),
|
.binsn_addr(lr_sav),
|
.epcr(epcr),
|
.epcr(epcr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_pc_we(pc_we),
|
.spr_pc_we(pc_we),
|
.genpc_refetch(genpc_refetch),
|
.genpc_refetch(genpc_refetch),
|
.genpc_freeze(genpc_freeze),
|
.genpc_freeze(genpc_freeze),
|
.genpc_stop_prefetch(1'b0),
|
.genpc_stop_prefetch(1'b0),
|
.no_more_dslot(no_more_dslot)
|
.no_more_dslot(no_more_dslot)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of instruction fetch block
|
// Instantiation of instruction fetch block
|
//
|
//
|
or1200_if or1200_if(
|
or1200_if or1200_if(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.icpu_dat_i(icpu_dat_i),
|
.icpu_dat_i(icpu_dat_i),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_err_i(icpu_err_i),
|
.icpu_err_i(icpu_err_i),
|
.icpu_adr_i(icpu_adr_i),
|
.icpu_adr_i(icpu_adr_i),
|
.icpu_tag_i(icpu_tag_i),
|
.icpu_tag_i(icpu_tag_i),
|
|
|
.if_freeze(if_freeze),
|
.if_freeze(if_freeze),
|
.if_insn(if_insn),
|
.if_insn(if_insn),
|
.if_pc(if_pc),
|
.if_pc(if_pc),
|
.flushpipe(flushpipe),
|
.flushpipe(flushpipe),
|
.if_stall(if_stall),
|
.if_stall(if_stall),
|
.no_more_dslot(no_more_dslot),
|
.no_more_dslot(no_more_dslot),
|
.genpc_refetch(genpc_refetch),
|
.genpc_refetch(genpc_refetch),
|
.rfe(rfe),
|
.rfe(rfe),
|
.except_itlbmiss(except_itlbmiss),
|
.except_itlbmiss(except_itlbmiss),
|
.except_immufault(except_immufault),
|
.except_immufault(except_immufault),
|
.except_ibuserr(except_ibuserr)
|
.except_ibuserr(except_ibuserr)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of instruction decode/control logic
|
// Instantiation of instruction decode/control logic
|
//
|
//
|
or1200_ctrl or1200_ctrl(
|
or1200_ctrl or1200_ctrl(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.flushpipe(flushpipe),
|
.flushpipe(flushpipe),
|
.if_insn(if_insn),
|
.if_insn(if_insn),
|
.ex_insn(ex_insn),
|
.ex_insn(ex_insn),
|
.branch_op(branch_op),
|
.branch_op(branch_op),
|
.branch_taken(branch_taken),
|
.branch_taken(branch_taken),
|
.rf_addra(rf_addra),
|
.rf_addra(rf_addra),
|
.rf_addrb(rf_addrb),
|
.rf_addrb(rf_addrb),
|
.rf_rda(rf_rda),
|
.rf_rda(rf_rda),
|
.rf_rdb(rf_rdb),
|
.rf_rdb(rf_rdb),
|
.alu_op(alu_op),
|
.alu_op(alu_op),
|
.mac_op(mac_op),
|
.mac_op(mac_op),
|
.shrot_op(shrot_op),
|
.shrot_op(shrot_op),
|
.comp_op(comp_op),
|
.comp_op(comp_op),
|
.rf_addrw(rf_addrw),
|
.rf_addrw(rf_addrw),
|
.rfwb_op(rfwb_op),
|
.rfwb_op(rfwb_op),
|
.wb_insn(wb_insn),
|
.wb_insn(wb_insn),
|
.simm(simm),
|
.simm(simm),
|
.branch_addrofs(branch_addrofs),
|
.branch_addrofs(branch_addrofs),
|
.lsu_addrofs(lsu_addrofs),
|
.lsu_addrofs(lsu_addrofs),
|
.sel_a(sel_a),
|
.sel_a(sel_a),
|
.sel_b(sel_b),
|
.sel_b(sel_b),
|
.lsu_op(lsu_op),
|
.lsu_op(lsu_op),
|
.cust5_op(cust5_op),
|
.cust5_op(cust5_op),
|
.cust5_limm(cust5_limm),
|
.cust5_limm(cust5_limm),
|
.multicycle(multicycle),
|
.multicycle(multicycle),
|
.spr_addrimm(spr_addrimm),
|
.spr_addrimm(spr_addrimm),
|
.wbforw_valid(wbforw_valid),
|
.wbforw_valid(wbforw_valid),
|
.sig_syscall(sig_syscall),
|
.sig_syscall(sig_syscall),
|
.sig_trap(sig_trap),
|
.sig_trap(sig_trap),
|
.force_dslot_fetch(force_dslot_fetch),
|
.force_dslot_fetch(force_dslot_fetch),
|
.no_more_dslot(no_more_dslot),
|
.no_more_dslot(no_more_dslot),
|
.ex_void(ex_void),
|
.ex_void(ex_void),
|
.id_macrc_op(id_macrc_op),
|
.id_macrc_op(id_macrc_op),
|
.ex_macrc_op(ex_macrc_op),
|
.ex_macrc_op(ex_macrc_op),
|
.rfe(rfe),
|
.rfe(rfe),
|
.du_hwbkpt(du_hwbkpt),
|
.du_hwbkpt(du_hwbkpt),
|
.except_illegal(except_illegal)
|
.except_illegal(except_illegal)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of register file
|
// Instantiation of register file
|
//
|
//
|
or1200_rf or1200_rf(
|
or1200_rf or1200_rf(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.supv(sr[`OR1200_SR_SM]),
|
.supv(sr[`OR1200_SR_SM]),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.addrw(rf_addrw),
|
.addrw(rf_addrw),
|
.dataw(rf_dataw),
|
.dataw(rf_dataw),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.we(rfwb_op[0]),
|
.we(rfwb_op[0]),
|
.flushpipe(flushpipe),
|
.flushpipe(flushpipe),
|
.addra(rf_addra),
|
.addra(rf_addra),
|
.rda(rf_rda),
|
.rda(rf_rda),
|
.dataa(rf_dataa),
|
.dataa(rf_dataa),
|
.addrb(rf_addrb),
|
.addrb(rf_addrb),
|
.rdb(rf_rdb),
|
.rdb(rf_rdb),
|
.datab(rf_datab),
|
.datab(rf_datab),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_rf)
|
.spr_dat_o(spr_dat_rf)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of operand muxes
|
// Instantiation of operand muxes
|
//
|
//
|
or1200_operandmuxes or1200_operandmuxes(
|
or1200_operandmuxes or1200_operandmuxes(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.rf_dataa(rf_dataa),
|
.rf_dataa(rf_dataa),
|
.rf_datab(rf_datab),
|
.rf_datab(rf_datab),
|
.ex_forw(rf_dataw),
|
.ex_forw(rf_dataw),
|
.wb_forw(wb_forw),
|
.wb_forw(wb_forw),
|
.simm(simm),
|
.simm(simm),
|
.sel_a(sel_a),
|
.sel_a(sel_a),
|
.sel_b(sel_b),
|
.sel_b(sel_b),
|
.operand_a(operand_a),
|
.operand_a(operand_a),
|
.operand_b(operand_b),
|
.operand_b(operand_b),
|
.muxed_b(muxed_b)
|
.muxed_b(muxed_b)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of CPU's ALU
|
// Instantiation of CPU's ALU
|
//
|
//
|
or1200_alu or1200_alu(
|
or1200_alu or1200_alu(
|
.a(operand_a),
|
.a(operand_a),
|
.b(operand_b),
|
.b(operand_b),
|
.mult_mac_result(mult_mac_result),
|
.mult_mac_result(mult_mac_result),
|
.macrc_op(ex_macrc_op),
|
.macrc_op(ex_macrc_op),
|
.alu_op(alu_op),
|
.alu_op(alu_op),
|
.shrot_op(shrot_op),
|
.shrot_op(shrot_op),
|
.comp_op(comp_op),
|
.comp_op(comp_op),
|
.cust5_op(cust5_op),
|
.cust5_op(cust5_op),
|
.cust5_limm(cust5_limm),
|
.cust5_limm(cust5_limm),
|
.result(alu_dataout),
|
.result(alu_dataout),
|
.flagforw(flagforw),
|
.flagforw(flagforw),
|
.flag_we(flag_we),
|
.flag_we(flag_we),
|
.cyforw(cyforw),
|
.cyforw(cyforw),
|
.cy_we(cy_we),
|
.cy_we(cy_we),
|
.flag(flag),
|
.flag(flag),
|
.carry(carry)
|
.carry(carry)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of CPU's ALU
|
// Instantiation of CPU's ALU
|
//
|
//
|
or1200_mult_mac or1200_mult_mac(
|
or1200_mult_mac or1200_mult_mac(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.id_macrc_op(id_macrc_op),
|
.id_macrc_op(id_macrc_op),
|
.macrc_op(ex_macrc_op),
|
.macrc_op(ex_macrc_op),
|
.a(operand_a),
|
.a(operand_a),
|
.b(operand_b),
|
.b(operand_b),
|
.mac_op(mac_op),
|
.mac_op(mac_op),
|
.alu_op(alu_op),
|
.alu_op(alu_op),
|
.result(mult_mac_result),
|
.result(mult_mac_result),
|
.mac_stall_r(mac_stall),
|
.mac_stall_r(mac_stall),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_mac)
|
.spr_dat_o(spr_dat_mac)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of CPU's SPRS block
|
// Instantiation of CPU's SPRS block
|
//
|
//
|
or1200_sprs or1200_sprs(
|
or1200_sprs or1200_sprs(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.addrbase(operand_a),
|
.addrbase(operand_a),
|
.addrofs(spr_addrimm),
|
.addrofs(spr_addrimm),
|
.dat_i(operand_b),
|
.dat_i(operand_b),
|
.alu_op(alu_op),
|
.alu_op(alu_op),
|
.flagforw(flagforw),
|
.flagforw(flagforw),
|
.flag_we(flag_we),
|
.flag_we(flag_we),
|
.flag(flag),
|
.flag(flag),
|
.cyforw(cyforw),
|
.cyforw(cyforw),
|
.cy_we(cy_we),
|
.cy_we(cy_we),
|
.carry(carry),
|
.carry(carry),
|
.to_wbmux(sprs_dataout),
|
.to_wbmux(sprs_dataout),
|
|
|
.du_addr(du_addr),
|
.du_addr(du_addr),
|
.du_dat_du(du_dat_du),
|
.du_dat_du(du_dat_du),
|
.du_read(du_read),
|
.du_read(du_read),
|
.du_write(du_write),
|
.du_write(du_write),
|
.du_dat_cpu(du_dat_cpu),
|
.du_dat_cpu(du_dat_cpu),
|
|
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_pic(spr_dat_pic),
|
.spr_dat_pic(spr_dat_pic),
|
.spr_dat_tt(spr_dat_tt),
|
.spr_dat_tt(spr_dat_tt),
|
.spr_dat_pm(spr_dat_pm),
|
.spr_dat_pm(spr_dat_pm),
|
.spr_dat_cfgr(spr_dat_cfgr),
|
.spr_dat_cfgr(spr_dat_cfgr),
|
.spr_dat_rf(spr_dat_rf),
|
.spr_dat_rf(spr_dat_rf),
|
.spr_dat_npc(spr_dat_npc),
|
.spr_dat_npc(spr_dat_npc),
|
.spr_dat_ppc(spr_dat_ppc),
|
.spr_dat_ppc(spr_dat_ppc),
|
.spr_dat_mac(spr_dat_mac),
|
.spr_dat_mac(spr_dat_mac),
|
.spr_dat_dmmu(spr_dat_dmmu),
|
.spr_dat_dmmu(spr_dat_dmmu),
|
.spr_dat_immu(spr_dat_immu),
|
.spr_dat_immu(spr_dat_immu),
|
.spr_dat_du(spr_dat_du),
|
.spr_dat_du(spr_dat_du),
|
.spr_dat_o(spr_dat_cpu),
|
.spr_dat_o(spr_dat_cpu),
|
.spr_cs(spr_cs),
|
.spr_cs(spr_cs),
|
.spr_we(spr_we),
|
.spr_we(spr_we),
|
|
|
.epcr_we(epcr_we),
|
.epcr_we(epcr_we),
|
.eear_we(eear_we),
|
.eear_we(eear_we),
|
.esr_we(esr_we),
|
.esr_we(esr_we),
|
.pc_we(pc_we),
|
.pc_we(pc_we),
|
.epcr(epcr),
|
.epcr(epcr),
|
.eear(eear),
|
.eear(eear),
|
.esr(esr),
|
.esr(esr),
|
.except_started(except_started),
|
.except_started(except_started),
|
|
|
.sr_we(sr_we),
|
.sr_we(sr_we),
|
.to_sr(to_sr),
|
.to_sr(to_sr),
|
.sr(sr),
|
.sr(sr),
|
.branch_op(branch_op)
|
.branch_op(branch_op)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of load/store unit
|
// Instantiation of load/store unit
|
//
|
//
|
or1200_lsu or1200_lsu(
|
or1200_lsu or1200_lsu(
|
.addrbase(operand_a),
|
.addrbase(operand_a),
|
.addrofs(lsu_addrofs),
|
.addrofs(lsu_addrofs),
|
.lsu_op(lsu_op),
|
.lsu_op(lsu_op),
|
.lsu_datain(operand_b),
|
.lsu_datain(operand_b),
|
.lsu_dataout(lsu_dataout),
|
.lsu_dataout(lsu_dataout),
|
.lsu_stall(lsu_stall),
|
.lsu_stall(lsu_stall),
|
.lsu_unstall(lsu_unstall),
|
.lsu_unstall(lsu_unstall),
|
.du_stall(du_stall),
|
.du_stall(du_stall),
|
.except_align(except_align),
|
.except_align(except_align),
|
.except_dtlbmiss(except_dtlbmiss),
|
.except_dtlbmiss(except_dtlbmiss),
|
.except_dmmufault(except_dmmufault),
|
.except_dmmufault(except_dmmufault),
|
.except_dbuserr(except_dbuserr),
|
.except_dbuserr(except_dbuserr),
|
|
|
.dcpu_adr_o(dcpu_adr_o),
|
.dcpu_adr_o(dcpu_adr_o),
|
.dcpu_cycstb_o(dcpu_cycstb_o),
|
.dcpu_cycstb_o(dcpu_cycstb_o),
|
.dcpu_we_o(dcpu_we_o),
|
.dcpu_we_o(dcpu_we_o),
|
.dcpu_sel_o(dcpu_sel_o),
|
.dcpu_sel_o(dcpu_sel_o),
|
.dcpu_tag_o(dcpu_tag_o),
|
.dcpu_tag_o(dcpu_tag_o),
|
.dcpu_dat_o(dcpu_dat_o),
|
.dcpu_dat_o(dcpu_dat_o),
|
.dcpu_dat_i(dcpu_dat_i),
|
.dcpu_dat_i(dcpu_dat_i),
|
.dcpu_ack_i(dcpu_ack_i),
|
.dcpu_ack_i(dcpu_ack_i),
|
.dcpu_rty_i(dcpu_rty_i),
|
.dcpu_rty_i(dcpu_rty_i),
|
.dcpu_err_i(dcpu_err_i),
|
.dcpu_err_i(dcpu_err_i),
|
.dcpu_tag_i(dcpu_tag_i)
|
.dcpu_tag_i(dcpu_tag_i)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of write-back muxes
|
// Instantiation of write-back muxes
|
//
|
//
|
or1200_wbmux or1200_wbmux(
|
or1200_wbmux or1200_wbmux(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.rfwb_op(rfwb_op),
|
.rfwb_op(rfwb_op),
|
.muxin_a(alu_dataout),
|
.muxin_a(alu_dataout),
|
.muxin_b(lsu_dataout),
|
.muxin_b(lsu_dataout),
|
.muxin_c(sprs_dataout),
|
.muxin_c(sprs_dataout),
|
.muxin_d({lr_sav, 2'b0}),
|
.muxin_d({lr_sav, 2'b0}),
|
.muxout(rf_dataw),
|
.muxout(rf_dataw),
|
.muxreg(wb_forw),
|
.muxreg(wb_forw),
|
.muxreg_valid(wbforw_valid)
|
.muxreg_valid(wbforw_valid)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of freeze logic
|
// Instantiation of freeze logic
|
//
|
//
|
or1200_freeze or1200_freeze(
|
or1200_freeze or1200_freeze(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.multicycle(multicycle),
|
.multicycle(multicycle),
|
.flushpipe(flushpipe),
|
.flushpipe(flushpipe),
|
.extend_flush(extend_flush),
|
.extend_flush(extend_flush),
|
.lsu_stall(lsu_stall),
|
.lsu_stall(lsu_stall),
|
.if_stall(if_stall),
|
.if_stall(if_stall),
|
.lsu_unstall(lsu_unstall),
|
.lsu_unstall(lsu_unstall),
|
.force_dslot_fetch(force_dslot_fetch),
|
.force_dslot_fetch(force_dslot_fetch),
|
.abort_ex(abort_ex),
|
.abort_ex(abort_ex),
|
.du_stall(du_stall),
|
.du_stall(du_stall),
|
.mac_stall(mac_stall),
|
.mac_stall(mac_stall),
|
.genpc_freeze(genpc_freeze),
|
.genpc_freeze(genpc_freeze),
|
.if_freeze(if_freeze),
|
.if_freeze(if_freeze),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_err_i(icpu_err_i)
|
.icpu_err_i(icpu_err_i)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of exception block
|
// Instantiation of exception block
|
//
|
//
|
or1200_except or1200_except(
|
or1200_except or1200_except(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.sig_ibuserr(except_ibuserr),
|
.sig_ibuserr(except_ibuserr),
|
.sig_dbuserr(except_dbuserr),
|
.sig_dbuserr(except_dbuserr),
|
.sig_illegal(except_illegal),
|
.sig_illegal(except_illegal),
|
.sig_align(except_align),
|
.sig_align(except_align),
|
.sig_range(1'b0),
|
.sig_range(1'b0),
|
.sig_dtlbmiss(except_dtlbmiss),
|
.sig_dtlbmiss(except_dtlbmiss),
|
.sig_dmmufault(except_dmmufault),
|
.sig_dmmufault(except_dmmufault),
|
.sig_int(sig_int),
|
.sig_int(sig_int),
|
.sig_syscall(sig_syscall),
|
.sig_syscall(sig_syscall),
|
.sig_trap(sig_trap),
|
.sig_trap(sig_trap),
|
.sig_itlbmiss(except_itlbmiss),
|
.sig_itlbmiss(except_itlbmiss),
|
.sig_immufault(except_immufault),
|
.sig_immufault(except_immufault),
|
.sig_tick(sig_tick),
|
.sig_tick(sig_tick),
|
.branch_taken(branch_taken),
|
.branch_taken(branch_taken),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_err_i(icpu_err_i),
|
.icpu_err_i(icpu_err_i),
|
.dcpu_ack_i(dcpu_ack_i),
|
.dcpu_ack_i(dcpu_ack_i),
|
.dcpu_err_i(dcpu_err_i),
|
.dcpu_err_i(dcpu_err_i),
|
.genpc_freeze(genpc_freeze),
|
.genpc_freeze(genpc_freeze),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.if_stall(if_stall),
|
.if_stall(if_stall),
|
.if_pc(if_pc),
|
.if_pc(if_pc),
|
.id_pc(id_pc),
|
.id_pc(id_pc),
|
.lr_sav(lr_sav),
|
.lr_sav(lr_sav),
|
.flushpipe(flushpipe),
|
.flushpipe(flushpipe),
|
.extend_flush(extend_flush),
|
.extend_flush(extend_flush),
|
.except_type(except_type),
|
.except_type(except_type),
|
.except_start(except_start),
|
.except_start(except_start),
|
.except_started(except_started),
|
.except_started(except_started),
|
.except_stop(except_stop),
|
.except_stop(except_stop),
|
.ex_void(ex_void),
|
.ex_void(ex_void),
|
.spr_dat_ppc(spr_dat_ppc),
|
.spr_dat_ppc(spr_dat_ppc),
|
.spr_dat_npc(spr_dat_npc),
|
.spr_dat_npc(spr_dat_npc),
|
|
|
.datain(operand_b),
|
.datain(operand_b),
|
.du_dsr(du_dsr),
|
.du_dsr(du_dsr),
|
.epcr_we(epcr_we),
|
.epcr_we(epcr_we),
|
.eear_we(eear_we),
|
.eear_we(eear_we),
|
.esr_we(esr_we),
|
.esr_we(esr_we),
|
.pc_we(pc_we),
|
.pc_we(pc_we),
|
.epcr(epcr),
|
.epcr(epcr),
|
.eear(eear),
|
.eear(eear),
|
.esr(esr),
|
.esr(esr),
|
|
|
.lsu_addr(dcpu_adr_o),
|
.lsu_addr(dcpu_adr_o),
|
.sr_we(sr_we),
|
.sr_we(sr_we),
|
.to_sr(to_sr),
|
.to_sr(to_sr),
|
.sr(sr),
|
.sr(sr),
|
.abort_ex(abort_ex)
|
.abort_ex(abort_ex)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of configuration registers
|
// Instantiation of configuration registers
|
//
|
//
|
or1200_cfgr or1200_cfgr(
|
or1200_cfgr or1200_cfgr(
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_o(spr_dat_cfgr)
|
.spr_dat_o(spr_dat_cfgr)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|