/*
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/*
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* Examples of Synopsys Design Compiler
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* Examples of Synopsys Design Compiler
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* synthesis script for OR1200 IP core
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* synthesis script for OR1200 IP core
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*
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*
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*/
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*/
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TOPLEVEL = or1200_top
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TOPLEVEL = or1200_top
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TECH = vs_umc18 /* vs_umc18, art_umc18 */
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TECH = vs_umc18 /* vs_umc18, art_umc18 */
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CLK = clk_i
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CLK = clk_i
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RST = rst_i
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RST = rst_i
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CLK_PERIOD = 5 /* 200 MHz */
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CLK_PERIOD = 5 /* 200 MHz */
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MAX_AREA = 0 /* Push hard */
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MAX_AREA = 0 /* Push hard */
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DO_UNGROUP = no /* yes, no */
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DO_UNGROUP = no /* yes, no */
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DO_VERIFY = no /* yes, no */
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DO_VERIFY = no /* yes, no */
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CLK_UNCERTAINTY = 0.1 /* 100 ps */
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CLK_UNCERTAINTY = 0.1 /* 100 ps */
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DFF_CKQ = 0.2 /* Clk to Q in technology time units */
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DFF_CKQ = 0.2 /* Clk to Q in technology time units */
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DFF_SETUP = 0.1 /* Setup time in technology time units */
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DFF_SETUP = 0.1 /* Setup time in technology time units */
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/* Starting timestamp */
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/* Starting timestamp */
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sh date
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sh date
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/*
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/*
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* Set some basic variables related to environment
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* Set some basic variables related to environment
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*
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*
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*/
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*/
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/* Enable Verilog HDL preprocessor */
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/* Enable Verilog HDL preprocessor */
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hdlin_enable_vpp = true
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hdlin_enable_vpp = true
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/* Set log path */
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/* Set log path */
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LOG_PATH = "../log/"
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LOG_PATH = "../log/"
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/* Set gate-level netlist path */
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/* Set gate-level netlist path */
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GATE_PATH = "../out/"
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GATE_PATH = "../out/"
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/* Set RAMS_PATH */
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/* Set RAMS_PATH */
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RAMS_PATH = "../../../lib/"
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RAMS_PATH = "../../../lib/"
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/* Set RTL source path */
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/* Set RTL source path */
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RTL_PATH = { "../../../rtl/verilog/" }
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RTL_PATH = { "../../../rtl/verilog/" }
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/* Optimize adders */
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/* Optimize adders */
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synlib_model_map_effort = high
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synlib_model_map_effort = high
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hlo_share_effort = low
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hlo_share_effort = low
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STAGE = final
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STAGE = final
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/*
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/*
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* Load libraries
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* Load libraries
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*
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*
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*/
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*/
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/* Search paths */
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/* Search paths */
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search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \
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search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \
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{ /libs/Artisan/aci/sc-x/symbols/synopsys/ } + \
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{ /libs/Artisan/aci/sc-x/symbols/synopsys/ } + \
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{ /libs/art_rams/ } + \
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{ /libs/art_rams/ } + \
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{ /libs/vs_rams/ /usr/dc/libraries/syn/ } + \
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{ /libs/vs_rams/ /usr/dc/libraries/syn/ } + \
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{ /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ }
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{ /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ }
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/* Synthetic libraries */
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/* Synthetic libraries */
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snps = get_unix_variable("SYNOPSYS")
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snps = get_unix_variable("SYNOPSYS")
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synthetic_library = { \
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synthetic_library = { \
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snps + "/libraries/syn/dw01.sldb" \
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snps + "/libraries/syn/dw01.sldb" \
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snps + "/libraries/syn/dw02.sldb" \
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snps + "/libraries/syn/dw02.sldb" \
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snps + "/libraries/syn/dw03.sldb" \
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snps + "/libraries/syn/dw03.sldb" \
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snps + "/libraries/syn/dw04.sldb" \
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snps + "/libraries/syn/dw04.sldb" \
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snps + "/libraries/syn/dw05.sldb" \
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snps + "/libraries/syn/dw05.sldb" \
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snps + "/libraries/syn/dw06.sldb" \
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snps + "/libraries/syn/dw06.sldb" \
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snps + "/libraries/syn/dw07.sldb" }
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snps + "/libraries/syn/dw07.sldb" }
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/* Set Artisan Sage-X UMC 0.18u standard cell library */
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/* Set Artisan Sage-X UMC 0.18u standard cell library */
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if (TECH == "art_umc18") {
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if (TECH == "art_umc18") {
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target_library = { slow.db \
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target_library = { slow.db \
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vs_hdsp_2048x32_wc_1.08V_125C.db \
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vs_hdsp_2048x32_wc_1.08V_125C.db \
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vs_hdsp_2048x8_tc_1.2V_25C.db \
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vs_hdsp_2048x8_tc_1.2V_25C.db \
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vs_hdsp_512x20_wc_1.08V_125C.db \
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vs_hdsp_512x20_wc_1.08V_125C.db \
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vs_hdsp_64x14_wc_1.08V_125C.db \
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vs_hdsp_64x14_wc_1.08V_125C.db \
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vs_hdsp_64x22_wc_1.08V_125C.db \
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vs_hdsp_64x22_wc_1.08V_125C.db \
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vs_hdsp_64x24_wc_1.08V_125C.db \
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vs_hdsp_64x24_wc_1.08V_125C.db \
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vs_hdtp_64x32_wc_1.08V_125C.db \
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vs_hdtp_64x32_wc_1.08V_125C.db \
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}
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}
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symbol_library = { umc18.sdb }
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symbol_library = { umc18.sdb }
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}
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}
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/* Set Virtual Silicon UMC 0.18u standard cell library */
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/* Set Virtual Silicon UMC 0.18u standard cell library */
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if (TECH == "vs_umc18") {
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if (TECH == "vs_umc18") {
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target_library = { umcl18u250t2_wc.db \
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target_library = { umcl18u250t2_wc.db \
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vs_hdsp_2048x32_wc_1.08V_125C.db \
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vs_hdsp_2048x32_wc_1.08V_125C.db \
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vs_hdsp_2048x8_wc_1.08V_125C.db \
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vs_hdsp_2048x8_wc_1.08V_125C.db \
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vs_hdsp_512x20_wc_1.08V_125C.db \
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vs_hdsp_512x20_wc_1.08V_125C.db \
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vs_hdsp_64x14_wc_1.08V_125C.db \
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vs_hdsp_64x14_wc_1.08V_125C.db \
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vs_hdsp_64x22_wc_1.08V_125C.db \
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vs_hdsp_64x22_wc_1.08V_125C.db \
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vs_hdsp_64x24_wc_1.08V_125C.db \
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vs_hdsp_64x24_wc_1.08V_125C.db \
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vs_hdtp_64x32_wc_1.08V_125C.db \
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vs_hdtp_64x32_wc_1.08V_125C.db \
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}
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}
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symbol_library = { umcl18u250t2.sdb }
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symbol_library = { umcl18u250t2.sdb }
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}
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}
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link_library = target_library + synthetic_library
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link_library = target_library + synthetic_library
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/*
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/*
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* Load HDL source files
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* Load HDL source files
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*
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*
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*/
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*/
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include ../bin/read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log
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include ../bin/read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log
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/* Set design top */
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/* Set design top */
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current_design TOPLEVEL
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current_design TOPLEVEL
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/* Link all blocks and uniquify them */
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/* Link all blocks and uniquify them */
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link
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link
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uniquify
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uniquify
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check_design > LOG_PATH + check_design_ + TOPLEVEL + .log
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check_design > LOG_PATH + check_design_ + TOPLEVEL + .log
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/*
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/*
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* Apply constraints
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* Apply constraints
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*
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*
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*/
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*/
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if (TECH == "vs_umc18") {
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if (TECH == "vs_umc18") {
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DFF_CELL = DFFPQ2
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DFF_CELL = DFFPQ2
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LIB_DFF_D = umcl18u250t2_wc/DFFPQ2/D
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LIB_DFF_D = umcl18u250t2_wc/DFFPQ2/D
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OPER_COND = WORST
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OPER_COND = WORST
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} else if (TECH == "art_umc18") {
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} else if (TECH == "art_umc18") {
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DFF_CELL = DFFHQX2
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DFF_CELL = DFFHQX2
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LIB_DFF_D = slow/DFFHQX2/D
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LIB_DFF_D = slow/DFFHQX2/D
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OPER_COND = slow
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OPER_COND = slow
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} else {
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} else {
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echo "Error: Unsupported technology"
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echo "Error: Unsupported technology"
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exit
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exit
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}
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}
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/* Clocks constraints */
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/* Clocks constraints */
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create_clock dwb_clk_i -period CLK_PERIOD
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create_clock dwb_clk_i -period CLK_PERIOD
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create_clock iwb_clk_i -period CLK_PERIOD
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create_clock iwb_clk_i -period CLK_PERIOD
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create_clock CLK -period CLK_PERIOD
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create_clock CLK -period CLK_PERIOD
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set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
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set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
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set_dont_touch_network all_clocks()
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set_dont_touch_network all_clocks()
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/* Reset constraints */
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/* Reset constraints */
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set_driving_cell -none RST
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set_driving_cell -none RST
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set_drive 0 RST
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set_drive 0 RST
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set_dont_touch_network RST
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set_dont_touch_network RST
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/* All inputs except reset and clock */
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/* All inputs except reset and clock */
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all_inputs_wo_rst_clk = all_inputs() - CLK - RST
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all_inputs_wo_rst_clk = all_inputs() - CLK - RST
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/* Set output delays and load for output signals
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/* Set output delays and load for output signals
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*
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*
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* All outputs are assumed to go directly into
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* All outputs are assumed to go directly into
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* external flip-flops for the purpose of this
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* external flip-flops for the purpose of this
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* synthesis
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* synthesis
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*/
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*/
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set_output_delay DFF_SETUP -clock CLK all_outputs()
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set_output_delay DFF_SETUP -clock CLK all_outputs()
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set_load load_of(LIB_DFF_D) * 4 all_outputs()
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set_load load_of(LIB_DFF_D) * 4 all_outputs()
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/* Input delay and driving cell of all inputs
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/* Input delay and driving cell of all inputs
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*
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*
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* All these signals are assumed to come directly from
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* All these signals are assumed to come directly from
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* flip-flops for the purpose of this synthesis
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* flip-flops for the purpose of this synthesis
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*
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*
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*/
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*/
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set_input_delay DFF_CKQ -clock CLK all_inputs_wo_rst_clk
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set_input_delay DFF_CKQ -clock CLK all_inputs_wo_rst_clk
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set_driving_cell -cell DFF_CELL -pin Q all_inputs_wo_rst_clk
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set_driving_cell -cell DFF_CELL -pin Q all_inputs_wo_rst_clk
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/* Set design fanout */
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/* Set design fanout */
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/*
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/*
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set_max_fanout 10 TOPLEVEL
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set_max_fanout 10 TOPLEVEL
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*/
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*/
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/* Optimize all near-critical paths to give extra slack for layout */
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/* Optimize all near-critical paths to give extra slack for layout */
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c_range = CLK_PERIOD * 0.10
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c_range = CLK_PERIOD * 0.10
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group_path -critical_range c_range -name CLK -to CLK
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group_path -critical_range c_range -name CLK -to CLK
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/* Operating conditions */
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/* Operating conditions */
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set_operating_conditions OPER_COND
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set_operating_conditions OPER_COND
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/* Lets do basic synthesis */
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/* Lets do basic synthesis */
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if (DO_UNGROUP == "yes") {
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if (DO_UNGROUP == "yes") {
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ungroup -all
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ungroup -all
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}
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}
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set_ultra_optimization -f
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set_ultra_optimization -f
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compile_new_optimization = true
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compile_new_optimization = true
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/*
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/*
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set_structure -boolean false -timing true
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set_structure -boolean false -timing true
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set_flatten -effort medium -minimize single_output
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set_flatten -effort medium -minimize single_output
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*/
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*/
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/*
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/*
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set_flatten false
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set_flatten false
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*/
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*/
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/*
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/*
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compile -boundary_optimization -map_effort medium -ungroup_all
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compile -boundary_optimization -map_effort medium -ungroup_all
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*/
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*/
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compile -boundary_optimization -map_effort high -auto_ungroup
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compile -boundary_optimization -map_effort high -auto_ungroup
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/*
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/*
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compile -map_effort low
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compile -map_effort low
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*/
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*/
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/* Save current design using synopsys format */
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/* Save current design using synopsys format */
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write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db
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write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db
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/* Save current design using verilog format */
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/* Save current design using verilog format */
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write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v
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write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v
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/* Basic reports */
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/* Basic reports */
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report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log
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report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log
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report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log
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report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log
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report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log
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report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log
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report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log
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report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log
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report_references > LOG_PATH + STAGE + _ + TOPLEVEL + _references.log
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report_references > LOG_PATH + STAGE + _ + TOPLEVEL + _references.log
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report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log
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report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log
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report_ultra_optimizations > LOG_PATH + STAGE + _ + TOPLEVEL + _ultra_optimizations.log
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report_ultra_optimizations > LOG_PATH + STAGE + _ + TOPLEVEL + _ultra_optimizations.log
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/*
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/*
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report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log
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report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log
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*/
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*/
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/* Verify design */
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/* Verify design */
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if (DO_VERIFY == "yes") {
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if (DO_VERIFY == "yes") {
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compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log
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compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log
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}
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}
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/* Finish */
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/* Finish */
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sh date
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sh date
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exit
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exit
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