/* Basic instruction set test */
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/* Basic instruction set test */
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "board.h"
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#include "board.h"
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#define MEM_RAM 0x00000000
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#define MEM_RAM 0x00000000
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#define MC_CSR (0x00)
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#define MC_CSR (0x00)
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#define MC_POC (0x04)
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#define MC_POC (0x04)
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#define MC_BA_MASK (0x08)
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#define MC_BA_MASK (0x08)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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.section .except, "ax"
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.section .except, "ax"
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l.addi r1,r0,0
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l.addi r1,r0,0
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.section .text
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.section .text
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.org 0x100
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.org 0x100
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_reset:
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_reset:
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l.movhi r1,hi(_init_mc)
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l.movhi r1,hi(_init_mc)
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l.ori r1,r1,lo(_init_mc)
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l.ori r1,r1,lo(_init_mc)
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l.jr r1
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l.jr r1
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l.nop
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l.nop
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_init_mc:
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_init_mc:
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l.movhi r3,hi(MC_BASE_ADDR)
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l.movhi r3,hi(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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l.addi r4,r3,MC_CSC(0)
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l.addi r4,r3,MC_CSC(0)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.srai r5,r5,6
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l.srai r5,r5,6
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l.ori r5,r5,0x0025
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l.ori r5,r5,0x0025
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(0)
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l.addi r4,r3,MC_TMS(0)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_BA_MASK
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l.addi r4,r3,MC_BA_MASK
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l.addi r5,r0,MC_MASK_VAL
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l.addi r5,r0,MC_MASK_VAL
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSR
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l.addi r4,r3,MC_CSR
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l.movhi r5,hi(MC_CSR_VAL)
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l.movhi r5,hi(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(1)
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l.addi r4,r3,MC_TMS(1)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSC(1)
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l.addi r4,r3,MC_CSC(1)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.srai r5,r5,6
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l.srai r5,r5,6
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l.ori r5,r5,0x0411
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l.ori r5,r5,0x0411
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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_regs:
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_regs:
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l.addi r1,r0,0x1
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l.addi r1,r0,0x1
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l.addi r2,r1,0x2
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l.addi r2,r1,0x2
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l.addi r3,r2,0x4
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l.addi r3,r2,0x4
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l.addi r4,r3,0x8
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l.addi r4,r3,0x8
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l.addi r5,r4,0x10
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l.addi r5,r4,0x10
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l.addi r6,r5,0x20
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l.addi r6,r5,0x20
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l.addi r7,r6,0x40
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l.addi r7,r6,0x40
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l.addi r8,r7,0x80
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l.addi r8,r7,0x80
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l.addi r9,r8,0x100
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l.addi r9,r8,0x100
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l.addi r10,r9,0x200
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l.addi r10,r9,0x200
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l.addi r11,r10,0x400
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l.addi r11,r10,0x400
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l.addi r12,r11,0x800
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l.addi r12,r11,0x800
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l.addi r13,r12,0x1000
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l.addi r13,r12,0x1000
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l.addi r14,r13,0x2000
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l.addi r14,r13,0x2000
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l.addi r15,r14,0x4000
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l.addi r15,r14,0x4000
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l.addi r16,r15,0x8000
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l.addi r16,r15,0x8000
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l.sub r31,r0,r1
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l.sub r31,r0,r1
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l.sub r30,r31,r2
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l.sub r30,r31,r2
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l.sub r29,r30,r3
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l.sub r29,r30,r3
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l.sub r28,r29,r4
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l.sub r28,r29,r4
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l.sub r27,r28,r5
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l.sub r27,r28,r5
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l.sub r26,r27,r6
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l.sub r26,r27,r6
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l.sub r25,r26,r7
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l.sub r25,r26,r7
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l.sub r24,r25,r8
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l.sub r24,r25,r8
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l.sub r23,r24,r9
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l.sub r23,r24,r9
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l.sub r22,r23,r10
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l.sub r22,r23,r10
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l.sub r21,r22,r11
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l.sub r21,r22,r11
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l.sub r20,r21,r12
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l.sub r20,r21,r12
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l.sub r19,r20,r13
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l.sub r19,r20,r13
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l.sub r18,r19,r14
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l.sub r18,r19,r14
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l.sub r17,r18,r15
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l.sub r17,r18,r15
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l.sub r16,r17,r16
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l.sub r16,r17,r16
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l.or r3,r0,r16
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l.or r3,r0,r16
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l.nop NOP_REPORT /* Should be 0xffff0012 */
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l.nop NOP_REPORT /* Should be 0xffff0012 */
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l.movhi r31, hi(MEM_RAM)
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l.movhi r31, hi(MEM_RAM)
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l.ori r31,r31, lo(MEM_RAM)
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l.ori r31,r31, lo(MEM_RAM)
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l.sw 0(r31),r16
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l.sw 0(r31),r16
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_mem: l.movhi r3,0x1234
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_mem: l.movhi r3,0x1234
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l.ori r3,r3,0x5678
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l.ori r3,r3,0x5678
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l.sw 4(r31),r3
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l.sw 4(r31),r3
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l.lbz r4,4(r31)
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l.lbz r4,4(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sb 11(r31),r4
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l.sb 11(r31),r4
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l.lbz r4,5(r31)
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l.lbz r4,5(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sb 10(r31),r4
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l.sb 10(r31),r4
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l.lbz r4,6(r31)
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l.lbz r4,6(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sb 9(r31),r4
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l.sb 9(r31),r4
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l.lbz r4,7(r31)
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l.lbz r4,7(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sb 8(r31),r4
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l.sb 8(r31),r4
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l.lbs r4,8(r31)
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l.lbs r4,8(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sb 7(r31),r4
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l.sb 7(r31),r4
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l.lbs r4,9(r31)
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l.lbs r4,9(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sb 6(r31),r4
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l.sb 6(r31),r4
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l.lbs r4,10(r31)
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l.lbs r4,10(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sb 5(r31),r4
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l.sb 5(r31),r4
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l.lbs r4,11(r31)
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l.lbs r4,11(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sb 4(r31),r4
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l.sb 4(r31),r4
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l.lhz r4,4(r31)
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l.lhz r4,4(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sh 10(r31),r4
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l.sh 10(r31),r4
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l.lhz r4,6(r31)
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l.lhz r4,6(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sh 8(r31),r4
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l.sh 8(r31),r4
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l.lhs r4,8(r31)
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l.lhs r4,8(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sh 6(r31),r4
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l.sh 6(r31),r4
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l.lhs r4,10(r31)
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l.lhs r4,10(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sh 4(r31),r4
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l.sh 4(r31),r4
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l.lwz r4,4(r31)
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l.lwz r4,4(r31)
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.or r3,r0,r8
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l.or r3,r0,r8
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l.nop NOP_REPORT /* Should be 0x12352af7 */
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l.nop NOP_REPORT /* Should be 0x12352af7 */
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l.lwz r9,0(r31)
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.add r8,r9,r8
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l.sw 0(r31),r8
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l.sw 0(r31),r8
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_arith:
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_arith:
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l.addi r3,r0,1
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l.addi r3,r0,1
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l.addi r4,r0,2
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l.addi r4,r0,2
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.addi r6,r0,-1
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l.addi r6,r0,-1
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l.addi r8,r0,0
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l.addi r8,r0,0
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l.sub r7,r5,r3
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l.sub r7,r5,r3
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l.sub r8,r3,r5
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l.sub r8,r3,r5
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l.add r8,r8,r7
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l.add r8,r8,r7
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l.div r7,r7,r4
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l.div r7,r7,r4
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l.add r9,r3,r4
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l.add r9,r3,r4
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l.mul r7,r9,r7
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l.mul r7,r9,r7
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l.divu r7,r7,r4
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l.divu r7,r7,r4
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l.add r8,r8,r7
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l.add r8,r8,r7
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l.or r3,r0,r8
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l.or r3,r0,r8
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l.nop NOP_REPORT /* Should be 0x7ffffffe */
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l.nop NOP_REPORT /* Should be 0x7ffffffe */
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l.lwz r9,0(r31)
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.add r8,r9,r8
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l.sw 0(r31),r8
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l.sw 0(r31),r8
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_log:
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_log:
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l.addi r3,r0,1
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l.addi r3,r0,1
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l.addi r4,r0,2
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l.addi r4,r0,2
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.addi r6,r0,-1
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l.addi r6,r0,-1
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l.addi r8,r0,0
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l.addi r8,r0,0
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l.andi r8,r8,1
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l.andi r8,r8,1
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l.and r8,r8,r3
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l.and r8,r8,r3
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l.xori r8,r5,0xa5a5
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l.xori r8,r5,0xa5a5
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l.xor r8,r8,r5
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l.xor r8,r8,r5
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l.ori r8,r8,2
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l.ori r8,r8,2
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l.or r8,r8,r4
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l.or r8,r8,r4
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l.or r3,r0,r8
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l.or r3,r0,r8
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l.nop NOP_REPORT /* Should be 0xffffa5a7 */
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l.nop NOP_REPORT /* Should be 0xffffa5a7 */
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l.lwz r9,0(r31)
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.add r8,r9,r8
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l.sw 0(r31),r8
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l.sw 0(r31),r8
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_shift:
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_shift:
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l.addi r3,r0,1
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l.addi r3,r0,1
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l.addi r4,r0,2
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l.addi r4,r0,2
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.addi r6,r0,-1
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l.addi r6,r0,-1
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l.addi r8,r0,0
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l.addi r8,r0,0
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l.slli r8,r5,6
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l.slli r8,r5,6
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l.sll r8,r8,r4
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l.sll r8,r8,r4
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l.srli r8,r8,6
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l.srli r8,r8,6
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l.srl r8,r8,r4
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l.srl r8,r8,r4
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l.srai r8,r8,2
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l.srai r8,r8,2
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l.sra r8,r8,r4
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l.sra r8,r8,r4
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l.or r3,r0,r8
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l.or r3,r0,r8
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l.nop NOP_REPORT /* Should be 0x000fffff */
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l.nop NOP_REPORT /* Should be 0x000fffff */
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l.lwz r9,0(r31)
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.add r8,r9,r8
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l.sw 0(r31),r8
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l.sw 0(r31),r8
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_flag:
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_flag:
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l.addi r3,r0,1
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l.addi r3,r0,1
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l.addi r4,r0,-2
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l.addi r4,r0,-2
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l.addi r8,r0,0
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l.addi r8,r0,0
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l.sfeq r3,r3
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l.sfeq r3,r3
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfeq r3,r4
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l.sfeq r3,r4
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfeqi r3,1
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l.sfeqi r3,1
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfeqi r3,-2
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l.sfeqi r3,-2
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfne r3,r3
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l.sfne r3,r3
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfne r3,r4
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l.sfne r3,r4
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfnei r3,1
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l.sfnei r3,1
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfnei r3,-2
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l.sfnei r3,-2
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfgtu r3,r3
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l.sfgtu r3,r3
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfgtu r3,r4
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l.sfgtu r3,r4
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfgtui r3,1
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l.sfgtui r3,1
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfgtui r3,-2
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l.sfgtui r3,-2
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.add r8,r8,r4
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l.sfgeu r3,r3
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l.sfgeu r3,r3
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l.mfspr r5,r0,17
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.andi r4,r5,0x200
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l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfgeu r3,r4
|
l.sfgeu r3,r4
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfgeui r3,1
|
l.sfgeui r3,1
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfgeui r3,-2
|
l.sfgeui r3,-2
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfltu r3,r3
|
l.sfltu r3,r3
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfltu r3,r4
|
l.sfltu r3,r4
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfltui r3,1
|
l.sfltui r3,1
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfltui r3,-2
|
l.sfltui r3,-2
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfleu r3,r3
|
l.sfleu r3,r3
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfleu r3,r4
|
l.sfleu r3,r4
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfleui r3,1
|
l.sfleui r3,1
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfleui r3,-2
|
l.sfleui r3,-2
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfgts r3,r3
|
l.sfgts r3,r3
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfgts r3,r4
|
l.sfgts r3,r4
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfgtsi r3,1
|
l.sfgtsi r3,1
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfgtsi r3,-2
|
l.sfgtsi r3,-2
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfges r3,r3
|
l.sfges r3,r3
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfges r3,r4
|
l.sfges r3,r4
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfgesi r3,1
|
l.sfgesi r3,1
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfgesi r3,-2
|
l.sfgesi r3,-2
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sflts r3,r3
|
l.sflts r3,r3
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sflts r3,r4
|
l.sflts r3,r4
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfltsi r3,1
|
l.sfltsi r3,1
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfltsi r3,-2
|
l.sfltsi r3,-2
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfles r3,r3
|
l.sfles r3,r3
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sfles r3,r4
|
l.sfles r3,r4
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sflesi r3,1
|
l.sflesi r3,1
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.sflesi r3,-2
|
l.sflesi r3,-2
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.andi r4,r5,0x200
|
l.andi r4,r5,0x200
|
l.add r8,r8,r4
|
l.add r8,r8,r4
|
|
|
l.or r3,r0,r8
|
l.or r3,r0,r8
|
l.nop NOP_REPORT /* Should be 0x00002800 */
|
l.nop NOP_REPORT /* Should be 0x00002800 */
|
|
|
l.lwz r9,0(r31)
|
l.lwz r9,0(r31)
|
l.add r8,r9,r8
|
l.add r8,r9,r8
|
l.sw 0(r31),r8
|
l.sw 0(r31),r8
|
|
|
_jump:
|
_jump:
|
l.addi r8,r0,0
|
l.addi r8,r0,0
|
|
|
l.j _T1
|
l.j _T1
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
_T2: l.jr r9
|
_T2: l.jr r9
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
_T1: l.jal _T2
|
_T1: l.jal _T2
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
l.sfeqi r0,0
|
l.sfeqi r0,0
|
l.bf _T3
|
l.bf _T3
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
_T3: l.sfeqi r0,1
|
_T3: l.sfeqi r0,1
|
l.bf _T4
|
l.bf _T4
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
_T4: l.sfeqi r0,0
|
_T4: l.sfeqi r0,0
|
l.bnf _T5
|
l.bnf _T5
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
_T5: l.sfeqi r0,1
|
_T5: l.sfeqi r0,1
|
l.bnf _T6
|
l.bnf _T6
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
_T6: l.movhi r3,hi(_T7)
|
_T6: l.movhi r3,hi(_T7)
|
l.ori r3,r3,lo(_T7)
|
l.ori r3,r3,lo(_T7)
|
l.mtspr r0,r3,32
|
l.mtspr r0,r3,32
|
l.mfspr r5,r0,17
|
l.mfspr r5,r0,17
|
l.mtspr r0,r5,64
|
l.mtspr r0,r5,64
|
l.rfe
|
l.rfe
|
l.addi r8,r8,1 /* l.rfe should not have a delay slot */
|
l.addi r8,r8,1 /* l.rfe should not have a delay slot */
|
|
|
l.addi r8,r8,1
|
l.addi r8,r8,1
|
|
|
_T7: l.or r3,r0,r8
|
_T7: l.or r3,r0,r8
|
l.nop NOP_REPORT /* Should be 0x000000009 */
|
l.nop NOP_REPORT /* Should be 0x000000009 */
|
|
|
l.lwz r9,0(r31)
|
l.lwz r9,0(r31)
|
l.add r8,r9,r8
|
l.add r8,r9,r8
|
l.sw 0(r31),r8
|
l.sw 0(r31),r8
|
|
|
l.lwz r9,0(r31)
|
l.lwz r9,0(r31)
|
l.movhi r3,0x4c69
|
l.movhi r3,0x4c69
|
l.ori r3,r3,0xe5f7
|
l.ori r3,r3,0xe5f7
|
l.add r8,r8,r3
|
l.add r8,r8,r3
|
|
|
l.or r3,r0,r8
|
l.or r3,r0,r8
|
l.nop NOP_REPORT /* Should be 0xdeaddead */
|
l.nop NOP_REPORT /* Should be 0xdeaddead */
|
|
|
l.addi r3,r0,0
|
l.addi r3,r0,0
|
l.nop NOP_EXIT
|
l.nop NOP_EXIT
|
|
|
|
|