/* mc_common.h - Memory Controller testbench common routines defines
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/* mc_common.h - Memory Controller testbench common routines defines
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Copyright (C) 2001 by Ivan Guzvinec, ivang@opencores.org
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Copyright (C) 2001 by Ivan Guzvinec, ivang@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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#ifndef __MC_COMMON_H
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#ifndef __MC_COMMON_H
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#define __MC_COMMON_H
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#define __MC_COMMON_H
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#define GPIO_BASE 0xA0000000LU
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#define GPIO_BASE 0xA0000000LU
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#define MC_BASE 0x60000000LU
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#define MC_BASE 0x60000000LU
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#define MC_MEM_BASE 0x04000000LU
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#define MC_MEM_BASE 0x04000000LU
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/* Row Test flags */
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/* Row Test flags */
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#define MC_TEST_RUN0 0x00000001LU
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#define MC_TEST_RUN0 0x00000001LU
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#define MC_TEST_RUN1 0x00000002LU
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#define MC_TEST_RUN1 0x00000002LU
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#define MC_TEST_RUN01 0x00000004LU
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#define MC_TEST_RUN01 0x00000004LU
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#define MC_TEST_RUN10 0x00000008LU
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#define MC_TEST_RUN10 0x00000008LU
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#define MC_TEST_RUNINC 0x00000010LU
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#define MC_TEST_RUNINC 0x00000010LU
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#define MC_TEST_8 0x00000020LU
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#define MC_TEST_8 0x00000020LU
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#define MC_TEST_16 0x00000040LU
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#define MC_TEST_16 0x00000040LU
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#define MC_TEST_32 0x00000080LU
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#define MC_TEST_32 0x00000080LU
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#define MC_TEST_SEQ 0x00000100LU
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#define MC_TEST_SEQ 0x00000100LU
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#define MC_TEST_SEQ1 0x00000200LU
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#define MC_TEST_SEQ1 0x00000200LU
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#define MC_TEST_RAND 0x00000400LU
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#define MC_TEST_RAND 0x00000400LU
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/* test pattern defines */
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/* test pattern defines */
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#define MC_TEST_PAT1_8 0x00U
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#define MC_TEST_PAT1_8 0x00U
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#define MC_TEST_PAT2_8 0xFFU
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#define MC_TEST_PAT2_8 0xFFU
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#define MC_TEST_PAT3_8 0x55U
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#define MC_TEST_PAT3_8 0x55U
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#define MC_TEST_PAT4_8 0xAAU
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#define MC_TEST_PAT4_8 0xAAU
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#define MC_TEST_PAT1_16 0x0000U
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#define MC_TEST_PAT1_16 0x0000U
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#define MC_TEST_PAT2_16 0xFFFFU
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#define MC_TEST_PAT2_16 0xFFFFU
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#define MC_TEST_PAT3_16 0x5555U
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#define MC_TEST_PAT3_16 0x5555U
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#define MC_TEST_PAT4_16 0xAAAAU
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#define MC_TEST_PAT4_16 0xAAAAU
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#define MC_TEST_PAT1_32 0x00000000LU
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#define MC_TEST_PAT1_32 0x00000000LU
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#define MC_TEST_PAT2_32 0xFFFFFFFFLU
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#define MC_TEST_PAT2_32 0xFFFFFFFFLU
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#define MC_TEST_PAT3_32 0x55555555LU
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#define MC_TEST_PAT3_32 0x55555555LU
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#define MC_TEST_PAT4_32 0xAAAAAAAALU
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#define MC_TEST_PAT4_32 0xAAAAAAAALU
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/* test device defines */
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/* test device defines */
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#define MC_TEST_DEV_SDRAM 0
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#define MC_TEST_DEV_SDRAM 0
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#define MC_TEST_DEV_SSRAM 1
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#define MC_TEST_DEV_SSRAM 1
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#define MC_TEST_DEV_ASYNC 2
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#define MC_TEST_DEV_ASYNC 2
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#define MC_TEST_DEV_SYNC 3
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#define MC_TEST_DEV_SYNC 3
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typedef volatile unsigned char *MEMLOC8;
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typedef volatile unsigned char *MEMLOC8;
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typedef volatile unsigned short *MEMLOC16;
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typedef volatile unsigned short *MEMLOC16;
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typedef volatile unsigned long *MEMLOC32;
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typedef volatile unsigned long *MEMLOC32;
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/* Prototypes */
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/* Prototypes */
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unsigned long mc_test_row(unsigned long nFrom, unsigned long nTo, unsigned long flags);
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unsigned long mc_test_row(unsigned long nFrom, unsigned long nTo, unsigned long flags);
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void randomin(unsigned long seed);
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void randomin(unsigned long seed);
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unsigned long random(unsigned long max);
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unsigned long random(unsigned long max);
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#endif
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#endif
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