URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
| Rev 19 |
Rev 21 |
section memory
|
section memory
|
/*random_seed = 12345
|
/*random_seed = 12345
|
type = random*/
|
type = random*/
|
pattern = 0x00
|
pattern = 0x00
|
type = unknown /* Fastest */
|
type = unknown /* Fastest */
|
|
|
name = "RAM"
|
name = "RAM"
|
ce = 1
|
ce = 1
|
baseaddr = 0x00000000
|
baseaddr = 0x00000000
|
size = 0x00200000
|
size = 0x00200000
|
delayr = 1
|
delayr = 1
|
delayw = 2
|
delayw = 2
|
end
|
end
|
|
|
section memory
|
section memory
|
/*random_seed = 12345
|
/*random_seed = 12345
|
type = random*/
|
type = random*/
|
pattern = 0x00
|
pattern = 0x00
|
type = unknown /* Fastest */
|
type = unknown /* Fastest */
|
|
|
name = "FLASH"
|
name = "FLASH"
|
ce = 0
|
ce = 0
|
baseaddr = 0xf0000000
|
baseaddr = 0xf0000000
|
size = 0x00200000
|
size = 0x00200000
|
delayr = 10
|
delayr = 10
|
delayw = -1
|
delayw = -1
|
end
|
end
|
|
|
section immu
|
section immu
|
enabled = 1
|
enabled = 1
|
nsets = 64
|
nsets = 64
|
nways = 1
|
nways = 1
|
ustates = 2
|
ustates = 2
|
pagesize = 8192
|
pagesize = 8192
|
end
|
end
|
|
|
section dmmu
|
section dmmu
|
enabled = 1
|
enabled = 1
|
nsets = 64
|
nsets = 64
|
nways = 1
|
nways = 1
|
ustates = 2
|
ustates = 2
|
pagesize = 8192
|
pagesize = 8192
|
end
|
end
|
|
|
section ic
|
section ic
|
enabled = 1
|
enabled = 1
|
nsets = 256
|
nsets = 256
|
nways = 1
|
nways = 1
|
ustates = 2
|
ustates = 2
|
blocksize = 16
|
blocksize = 16
|
end
|
end
|
|
|
section dc
|
section dc
|
enabled = 1
|
enabled = 1
|
nsets = 256
|
nsets = 256
|
nways = 1
|
nways = 1
|
ustates = 2
|
ustates = 2
|
blocksize = 16
|
blocksize = 16
|
end
|
end
|
|
|
section sim
|
section sim
|
/* verbose = 1 */
|
/* verbose = 1 */
|
debug = 0
|
debug = 0
|
profile = 0
|
profile = 0
|
prof_fn = "sim.profile"
|
prof_fn = "sim.profile"
|
|
|
history = 1
|
history = 1
|
/* iprompt = 0 */
|
/* iprompt = 0 */
|
exe_log = 0
|
exe_log = 0
|
exe_log_fn = "executed.log"
|
exe_log_fn = "executed.log"
|
end
|
end
|
|
|
section mc
|
section mc
|
enabled = 1
|
enabled = 1
|
baseaddr = 0x93000000
|
baseaddr = 0x93000000
|
POC = 0x00000008 /* Power on configuration register */
|
POC = 0x00000008 /* Power on configuration register */
|
end
|
end
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.