/* is-div-test.S. l.div and l.divu instruction test of Or1ksim
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/* is-div-test.S. l.div and l.divu instruction test of Or1ksim
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*
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*
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* Copyright (C) 1999-2006 OpenCores
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* Copyright (C) 1999-2006 OpenCores
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* Copyright (C) 2010 Embecosm Limited
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* Copyright (C) 2010 Embecosm Limited
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*
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*
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* Contributors various OpenCores participants
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* Contributors various OpenCores participants
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* Contributor Jeremy Bennett
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* Contributor Jeremy Bennett
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*
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*
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* This file is part of OpenRISC 1000 Architectural Simulator.
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* This file is part of OpenRISC 1000 Architectural Simulator.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 3 of the License, or (at your option)
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* Software Foundation; either version 3 of the License, or (at your option)
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* any later version.
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* any later version.
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*
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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* more details.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see .
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* with this program. If not, see .
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*/
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*/
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Coding conventions are described in inst-set-test.S
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* Coding conventions are described in inst-set-test.S
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Test coverage
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* Test coverage
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*
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*
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* The l.ror and l.rori instructions were missing from Or1ksim.
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* The l.ror and l.rori instructions were missing from Or1ksim.
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*
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*
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* Having fixed the problem, this is (in good software engineering style), a
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* Having fixed the problem, this is (in good software engineering style), a
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* regresison test to go with the fix.
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* regresison test to go with the fix.
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*
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*
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* This is not a comprehensive test of either instruction (yet).
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* This is not a comprehensive test of either instruction (yet).
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*
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*
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* Of course what is really needed is a comprehensive instruction test...
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* Of course what is really needed is a comprehensive instruction test...
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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#include "inst-set-test.h"
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#include "inst-set-test.h"
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* A macro to carry out a test of rotate right
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* A macro to carry out a test of rotate right
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*
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*
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* Arguments
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* Arguments
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* op1: First operand value
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* op1: First operand value
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* op2: Second operand value
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* op2: Second operand value
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* res: Expected result
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* res: Expected result
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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#define TEST_ROR(op1, op2, res) \
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#define TEST_ROR(op1, op2, res) \
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LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\
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LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\
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LOAD_CONST (r6,op2) ;\
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LOAD_CONST (r6,op2) ;\
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l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
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l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
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50: l.ror r4,r5,r6 ;\
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50: l.ror r4,r5,r6 ;\
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l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
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l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
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PUSH (r5) /* Save EPCR for later */ ;\
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PUSH (r5) /* Save EPCR for later */ ;\
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PUSH (r4) /* Save result for later */ ;\
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PUSH (r4) /* Save result for later */ ;\
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;\
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;\
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PUTS (" 0x") ;\
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PUTS (" 0x") ;\
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PUTH (op1) ;\
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PUTH (op1) ;\
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PUTS (" ROR 0x") ;\
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PUTS (" ROR 0x") ;\
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PUTH (op2) ;\
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PUTH (op2) ;\
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PUTS (" = 0x") ;\
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PUTS (" = 0x") ;\
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PUTH (res) ;\
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PUTH (res) ;\
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PUTS (": ") ;\
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PUTS (": ") ;\
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POP (r4) ;\
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POP (r4) ;\
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CHECK_RES1 (r4, res) ;\
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CHECK_RES1 (r4, res) ;\
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;\
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;\
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POP (r2) /* Retrieve EPCR */ ;\
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POP (r2) /* Retrieve EPCR */ ;\
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LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
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LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
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l.and r2,r2,r4 ;\
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l.and r2,r2,r4 ;\
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l.sfeq r2,r4 ;\
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l.sfeq r2,r4 ;\
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l.bnf 51f ;\
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l.bnf 51f ;\
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;\
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;\
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PUTS (" - exception triggered: TRUE\n") ;\
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PUTS (" - exception triggered: TRUE\n") ;\
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l.j 52f ;\
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l.j 52f ;\
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l.nop ;\
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l.nop ;\
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;\
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;\
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51: PUTS (" - exception triggered: FALSE\n") ;\
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51: PUTS (" - exception triggered: FALSE\n") ;\
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52:
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52:
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* A macro to carry out a test of rotate right immediate
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* A macro to carry out a test of rotate right immediate
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*
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*
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* Arguments
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* Arguments
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* op1: First operand value
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* op1: First operand value
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* op2: Second operand value
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* op2: Second operand value
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* res: Expected result
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* res: Expected result
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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#define TEST_RORI(op1, op2, res) \
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#define TEST_RORI(op1, op2, res) \
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LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\
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LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\
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l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
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l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
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53: l.rori r4,r5,op2 ;\
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53: l.rori r4,r5,op2 ;\
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l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
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l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
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PUSH (r5) /* Save EPCR for later */ ;\
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PUSH (r5) /* Save EPCR for later */ ;\
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PUSH (r4) /* Save result for later */ ;\
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PUSH (r4) /* Save result for later */ ;\
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;\
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;\
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PUTS (" 0x") ;\
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PUTS (" 0x") ;\
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PUTH (op1) ;\
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PUTH (op1) ;\
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PUTS (" RORI 0x") ;\
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PUTS (" RORI 0x") ;\
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PUTHQ (op2) ;\
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PUTHQ (op2) ;\
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PUTS (" = 0x") ;\
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PUTS (" = 0x") ;\
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PUTH (res) ;\
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PUTH (res) ;\
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PUTS (": ") ;\
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PUTS (": ") ;\
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POP (r4) ;\
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POP (r4) ;\
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CHECK_RES1 (r4, res) ;\
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CHECK_RES1 (r4, res) ;\
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;\
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;\
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POP (r2) /* Retrieve EPCR */ ;\
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POP (r2) /* Retrieve EPCR */ ;\
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LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\
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LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\
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l.and r2,r2,r4 ;\
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l.and r2,r2,r4 ;\
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l.sfeq r2,r4 ;\
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l.sfeq r2,r4 ;\
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l.bnf 54f ;\
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l.bnf 54f ;\
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;\
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;\
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PUTS (" - exception triggered: TRUE\n") ;\
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PUTS (" - exception triggered: TRUE\n") ;\
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l.j 55f ;\
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l.j 55f ;\
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l.nop ;\
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l.nop ;\
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;\
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;\
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54: PUTS (" - exception triggered: FALSE\n") ;\
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54: PUTS (" - exception triggered: FALSE\n") ;\
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55:
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55:
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Start of code
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* Start of code
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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.section .text
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.section .text
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.global _start
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.global _start
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_start:
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_start:
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Test of rotate right, l.ror
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* Test of rotate right, l.ror
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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_ror:
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_ror:
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LOAD_STR (r3, "l.ror\n")
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LOAD_STR (r3, "l.ror\n")
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l.jal _puts
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l.jal _puts
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l.nop
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l.nop
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/* Rotate by zero */
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/* Rotate by zero */
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TEST_ROR (0xb38f0f83, 0x00000000, 0xb38f0f83)
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TEST_ROR (0xb38f0f83, 0x00000000, 0xb38f0f83)
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/* Rotate by amounts in the 1 - 31 range. */
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/* Rotate by amounts in the 1 - 31 range. */
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TEST_ROR (0xb38f0f83, 0x00000001, 0xd9c787c1)
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TEST_ROR (0xb38f0f83, 0x00000001, 0xd9c787c1)
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TEST_ROR (0xb38f0f83, 0x00000004, 0x3b38f0f8)
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TEST_ROR (0xb38f0f83, 0x00000004, 0x3b38f0f8)
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TEST_ROR (0xb38f0f83, 0x00000010, 0x0f83b38f)
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TEST_ROR (0xb38f0f83, 0x00000010, 0x0f83b38f)
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TEST_ROR (0xb38f0f83, 0x0000001f, 0x671e1f07)
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TEST_ROR (0xb38f0f83, 0x0000001f, 0x671e1f07)
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/* Rotate by larger amounts - should be masked. */
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/* Rotate by larger amounts - should be masked. */
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TEST_ROR (0xb38f0f83, 0x00000021, 0xd9c787c1)
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TEST_ROR (0xb38f0f83, 0x00000021, 0xd9c787c1)
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TEST_ROR (0xb38f0f83, 0x00002224, 0x3b38f0f8)
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TEST_ROR (0xb38f0f83, 0x00002224, 0x3b38f0f8)
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TEST_ROR (0xb38f0f83, 0x00f789f0, 0x0f83b38f)
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TEST_ROR (0xb38f0f83, 0x00f789f0, 0x0f83b38f)
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TEST_ROR (0xb38f0f83, 0xffffffff, 0x671e1f07)
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TEST_ROR (0xb38f0f83, 0xffffffff, 0x671e1f07)
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Test of rotate right immediate, l.rori
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* Test of rotate right immediate, l.rori
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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_rori:
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_rori:
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LOAD_STR (r3, "l.rori\n")
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LOAD_STR (r3, "l.rori\n")
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l.jal _puts
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l.jal _puts
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l.nop
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l.nop
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/* Rotate by zero */
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/* Rotate by zero */
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TEST_RORI (0xb38f0f83, 0x00000000, 0xb38f0f83)
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TEST_RORI (0xb38f0f83, 0x00000000, 0xb38f0f83)
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/* Rotate by amounts in the 1 - 31 range. */
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/* Rotate by amounts in the 1 - 31 range. */
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TEST_RORI (0xb38f0f83, 0x01, 0xd9c787c1)
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TEST_RORI (0xb38f0f83, 0x01, 0xd9c787c1)
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TEST_RORI (0xb38f0f83, 0x04, 0x3b38f0f8)
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TEST_RORI (0xb38f0f83, 0x04, 0x3b38f0f8)
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TEST_RORI (0xb38f0f83, 0x10, 0x0f83b38f)
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TEST_RORI (0xb38f0f83, 0x10, 0x0f83b38f)
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TEST_RORI (0xb38f0f83, 0x1f, 0x671e1f07)
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TEST_RORI (0xb38f0f83, 0x1f, 0x671e1f07)
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/* Rotate by larger amounts (32 - 63) - should be masked. */
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/* Rotate by larger amounts (32 - 63) - should be masked. */
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TEST_RORI (0xb38f0f83, 0x21, 0xd9c787c1)
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TEST_RORI (0xb38f0f83, 0x21, 0xd9c787c1)
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TEST_RORI (0xb38f0f83, 0x24, 0x3b38f0f8)
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TEST_RORI (0xb38f0f83, 0x24, 0x3b38f0f8)
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TEST_RORI (0xb38f0f83, 0x30, 0x0f83b38f)
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TEST_RORI (0xb38f0f83, 0x30, 0x0f83b38f)
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TEST_RORI (0xb38f0f83, 0x3f, 0x671e1f07)
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TEST_RORI (0xb38f0f83, 0x3f, 0x671e1f07)
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* All done
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* All done
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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_exit:
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_exit:
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LOAD_STR (r3, "Test completed\n")
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LOAD_STR (r3, "Test completed\n")
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l.jal _puts
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l.jal _puts
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l.nop
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l.nop
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TEST_EXIT
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TEST_EXIT
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