/* int.c -- Interrupt handling for Or1ksim tests.
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/* int.c -- Interrupt handling for Or1ksim tests.
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Copyright (C) 2001 Simon Srot, srot@opencores.org
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Copyright (C) 2001 Simon Srot, srot@opencores.org
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Copyright (C) 2008, 2010 Embecosm Limited
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Copyright (C) 2008, 2010 Embecosm Limited
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Contributor Simon Srot <srot@opencores.org>
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Contributor Simon Srot <srot@opencores.org>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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/* This file is part of test microkernel for OpenRISC 1000. */
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/* This file is part of test microkernel for OpenRISC 1000. */
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#include "support.h"
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#include "support.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "int.h"
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#include "int.h"
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/* Interrupt handlers table */
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/* Interrupt handlers table */
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struct ihnd int_handlers[MAX_INT_HANDLERS];
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struct ihnd int_handlers[MAX_INT_HANDLERS];
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/* Initialize routine */
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/* Initialize routine */
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int int_init()
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int int_init()
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{
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{
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int i;
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int i;
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for(i = 0; i < MAX_INT_HANDLERS; i++) {
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for(i = 0; i < MAX_INT_HANDLERS; i++) {
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int_handlers[i].handler = 0;
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int_handlers[i].handler = 0;
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int_handlers[i].arg = 0;
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int_handlers[i].arg = 0;
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}
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}
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return 0;
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return 0;
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}
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}
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/* Add interrupt handler */
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/* Add interrupt handler */
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int int_add(unsigned long vect, void (* handler)(void *), void *arg)
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int int_add(unsigned long vect, void (* handler)(void *), void *arg)
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{
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{
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if(vect >= MAX_INT_HANDLERS)
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if(vect >= MAX_INT_HANDLERS)
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return -1;
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return -1;
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int_handlers[vect].handler = handler;
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int_handlers[vect].handler = handler;
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int_handlers[vect].arg = arg;
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int_handlers[vect].arg = arg;
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
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return 0;
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return 0;
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}
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}
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/* Disable interrupt */
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/* Disable interrupt */
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int int_disable(unsigned long vect)
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int int_disable(unsigned long vect)
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{
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{
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if(vect >= MAX_INT_HANDLERS)
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if(vect >= MAX_INT_HANDLERS)
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return -1;
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return -1;
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
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return 0;
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return 0;
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}
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}
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/* Enable interrupt */
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/* Enable interrupt */
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int int_enable(unsigned long vect)
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int int_enable(unsigned long vect)
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{
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{
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if(vect >= MAX_INT_HANDLERS)
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if(vect >= MAX_INT_HANDLERS)
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return -1;
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return -1;
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
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return 0;
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return 0;
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}
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}
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/* Main interrupt handler */
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/* Main interrupt handler */
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void int_main()
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void int_main()
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{
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{
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unsigned long picsr = mfspr(SPR_PICSR);
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unsigned long picsr = mfspr(SPR_PICSR);
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unsigned long i = 0;
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unsigned long i = 0;
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mtspr(SPR_PICSR, 0);
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mtspr(SPR_PICSR, 0);
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while(i < 32) {
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while(i < 32) {
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if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
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if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
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(*int_handlers[i].handler)(int_handlers[i].arg);
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(*int_handlers[i].handler)(int_handlers[i].arg);
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i));
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i));
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}
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}
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i++;
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i++;
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}
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}
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}
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}
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