/* dmatest.c. Test of Or1ksim DMA
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/* dmatest.c. Test of Or1ksim DMA
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 2010 Embecosm Limited
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Copyright (C) 2010 Embecosm Limited
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Contributors various OpenCores participants
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Contributors various OpenCores participants
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http: www.gnu.org/licenses/>. */
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with this program. If not, see <http: www.gnu.org/licenses/>. */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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#include "support.h"
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#include "support.h"
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#include "board.h"
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#include "board.h"
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/* Includes from main peripheral directory */
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/* Includes from main peripheral directory */
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#include "fields.h"
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#include "fields.h"
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#include "dma-defs.h"
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#include "dma-defs.h"
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typedef volatile unsigned long *DMA_REG;
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typedef volatile unsigned long *DMA_REG;
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DMA_REG csr = (unsigned long *)(DMA_BASE + DMA_CSR),
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DMA_REG csr = (unsigned long *)(DMA_BASE + DMA_CSR),
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int_msk_a = (unsigned long *)(DMA_BASE + DMA_INT_MSK_A),
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int_msk_a = (unsigned long *)(DMA_BASE + DMA_INT_MSK_A),
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int_msk_b = (unsigned long *)(DMA_BASE + DMA_INT_MSK_B),
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int_msk_b = (unsigned long *)(DMA_BASE + DMA_INT_MSK_B),
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int_src_a = (unsigned long *)(DMA_BASE + DMA_INT_SRC_A),
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int_src_a = (unsigned long *)(DMA_BASE + DMA_INT_SRC_A),
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int_src_b = (unsigned long *)(DMA_BASE + DMA_INT_SRC_B),
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int_src_b = (unsigned long *)(DMA_BASE + DMA_INT_SRC_B),
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ch0_csr = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_CSR),
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ch0_csr = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_CSR),
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ch0_sz = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_SZ),
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ch0_sz = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_SZ),
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ch0_a0 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_A0),
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ch0_a0 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_A0),
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ch0_am0 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_AM0),
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ch0_am0 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_AM0),
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ch0_a1 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_A1),
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ch0_a1 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_A1),
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ch0_am1 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_AM1),
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ch0_am1 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_AM1),
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ch0_desc = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_DESC);
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ch0_desc = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_DESC);
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struct DMA_DESCRIPTOR
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struct DMA_DESCRIPTOR
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{
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{
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unsigned long csr;
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unsigned long csr;
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unsigned long adr0;
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unsigned long adr0;
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unsigned long adr1;
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unsigned long adr1;
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unsigned long next;
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unsigned long next;
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};
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};
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/* Test simplest DMA operation */
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/* Test simplest DMA operation */
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int simple( void )
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int simple( void )
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{
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{
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int ok;
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int ok;
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unsigned long src[2], dst[2];
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unsigned long src[2], dst[2];
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/* Set transfer Size */
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/* Set transfer Size */
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*ch0_sz = 0x00000002;
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*ch0_sz = 0x00000002;
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/* Set addresses */
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/* Set addresses */
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*ch0_a0 = (unsigned long)src;
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*ch0_a0 = (unsigned long)src;
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*ch0_a1 = (unsigned long)dst;
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*ch0_a1 = (unsigned long)dst;
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/* Fill source */
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/* Fill source */
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src[0] = 0x01234567LU;
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src[0] = 0x01234567LU;
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src[1] = 0x89ABCDEFLU;
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src[1] = 0x89ABCDEFLU;
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/* Now set channel CSR */
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/* Now set channel CSR */
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*ch0_csr = FLAG_MASK( DMA_CH_CSR, CH_EN ) | FLAG_MASK( DMA_CH_CSR, INC_SRC ) | FLAG_MASK( DMA_CH_CSR, INC_DST );
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*ch0_csr = FLAG_MASK( DMA_CH_CSR, CH_EN ) | FLAG_MASK( DMA_CH_CSR, INC_SRC ) | FLAG_MASK( DMA_CH_CSR, INC_DST );
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/* Wait till the channel finishes */
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/* Wait till the channel finishes */
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while ( TEST_FLAG( *ch0_csr, DMA_CH_CSR, BUSY ) )
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while ( TEST_FLAG( *ch0_csr, DMA_CH_CSR, BUSY ) )
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;
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;
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/* Dump contents of memory */
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/* Dump contents of memory */
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ok = (dst[0] == src[0] && dst[1] == src[1]);
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ok = (dst[0] == src[0] && dst[1] == src[1]);
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report( ok );
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report( ok );
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return ok;
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return ok;
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}
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}
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/* Test simple transfer with chunks */
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/* Test simple transfer with chunks */
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int chunks( void )
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int chunks( void )
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{
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{
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unsigned i, ok;
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unsigned i, ok;
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unsigned long src[6], dst[6];
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unsigned long src[6], dst[6];
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/* Set transfer size */
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/* Set transfer size */
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*ch0_sz = 6LU | (3LU << DMA_CH_SZ_CHK_SZ_OFFSET);
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*ch0_sz = 6LU | (3LU << DMA_CH_SZ_CHK_SZ_OFFSET);
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/* Set addresses */
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/* Set addresses */
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*ch0_a0 = (unsigned long)src;
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*ch0_a0 = (unsigned long)src;
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*ch0_a1 = (unsigned long)dst;
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*ch0_a1 = (unsigned long)dst;
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/* Fill source */
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/* Fill source */
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for ( i = 0; i < 6; ++ i )
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for ( i = 0; i < 6; ++ i )
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src[i] = 0xA63F879CLU + i;
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src[i] = 0xA63F879CLU + i;
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/* Now set channel CSR */
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/* Now set channel CSR */
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*ch0_csr = FLAG_MASK( DMA_CH_CSR, CH_EN ) | FLAG_MASK( DMA_CH_CSR, INC_SRC ) | FLAG_MASK( DMA_CH_CSR, INC_DST );
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*ch0_csr = FLAG_MASK( DMA_CH_CSR, CH_EN ) | FLAG_MASK( DMA_CH_CSR, INC_SRC ) | FLAG_MASK( DMA_CH_CSR, INC_DST );
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/* Wait till the channel finishes */
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/* Wait till the channel finishes */
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while ( TEST_FLAG( *ch0_csr, DMA_CH_CSR, BUSY ) )
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while ( TEST_FLAG( *ch0_csr, DMA_CH_CSR, BUSY ) )
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;
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;
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/* Dump contents of memory */
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/* Dump contents of memory */
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ok = 1;
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ok = 1;
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for ( i = 0; i < 6 && ok; ++ i )
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for ( i = 0; i < 6 && ok; ++ i )
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if ( dst[i] != src[i] )
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if ( dst[i] != src[i] )
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ok = 0;
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ok = 0;
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report( i );
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report( i );
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return ok;
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return ok;
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}
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}
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/* Test transfer using linked list */
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/* Test transfer using linked list */
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int list( void )
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int list( void )
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{
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{
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struct DMA_DESCRIPTOR desc[2];
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struct DMA_DESCRIPTOR desc[2];
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unsigned long src[10], dst[10];
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unsigned long src[10], dst[10];
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unsigned i, ok;
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unsigned i, ok;
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/* Set transfer size for each list element */
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/* Set transfer size for each list element */
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desc[0].csr = 6;
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desc[0].csr = 6;
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desc[1].csr = 4;
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desc[1].csr = 4;
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/* Set chunk size */
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/* Set chunk size */
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*ch0_sz = 2UL << DMA_CH_SZ_CHK_SZ_OFFSET;
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*ch0_sz = 2UL << DMA_CH_SZ_CHK_SZ_OFFSET;
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/* Set addresses */
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/* Set addresses */
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desc[0].adr0 = (unsigned long)src;
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desc[0].adr0 = (unsigned long)src;
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desc[0].adr1 = (unsigned long)dst;
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desc[0].adr1 = (unsigned long)dst;
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desc[1].adr0 = (unsigned long)(src + 6);
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desc[1].adr0 = (unsigned long)(src + 6);
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desc[1].adr1 = (unsigned long)(dst + 6);
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desc[1].adr1 = (unsigned long)(dst + 6);
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/* Fill source (original code had 0x110bd540fUL as the constant, but that
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/* Fill source (original code had 0x110bd540fUL as the constant, but that
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is more than 32-bits. */
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is more than 32-bits. */
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for ( i = 0; i < 10; ++ i )
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for ( i = 0; i < 10; ++ i )
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src[i] = 0x10bd540fUL + i;
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src[i] = 0x10bd540fUL + i;
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/* Set descriptor CSR */
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/* Set descriptor CSR */
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desc[0].csr |= FLAG_MASK( DMA_DESC_CSR, INC_SRC ) | FLAG_MASK( DMA_DESC_CSR, INC_DST );
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desc[0].csr |= FLAG_MASK( DMA_DESC_CSR, INC_SRC ) | FLAG_MASK( DMA_DESC_CSR, INC_DST );
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desc[1].csr |= FLAG_MASK( DMA_DESC_CSR, EOL ) | FLAG_MASK( DMA_DESC_CSR, INC_SRC ) | FLAG_MASK( DMA_DESC_CSR, INC_DST );
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desc[1].csr |= FLAG_MASK( DMA_DESC_CSR, EOL ) | FLAG_MASK( DMA_DESC_CSR, INC_SRC ) | FLAG_MASK( DMA_DESC_CSR, INC_DST );
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/* Point channel to descriptor */
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/* Point channel to descriptor */
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*ch0_desc = (unsigned)desc;
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*ch0_desc = (unsigned)desc;
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/* Link the list */
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/* Link the list */
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desc[0].next = (unsigned)&(desc[1]);
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desc[0].next = (unsigned)&(desc[1]);
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desc[1].next = 0xDEADDEADUL;
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desc[1].next = 0xDEADDEADUL;
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/* Set channel CSR */
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/* Set channel CSR */
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*ch0_csr = FLAG_MASK( DMA_CH_CSR, CH_EN ) | FLAG_MASK( DMA_CH_CSR, USE_ED );
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*ch0_csr = FLAG_MASK( DMA_CH_CSR, CH_EN ) | FLAG_MASK( DMA_CH_CSR, USE_ED );
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/* Wait till the channel finishes */
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/* Wait till the channel finishes */
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while ( TEST_FLAG( *ch0_csr, DMA_CH_CSR, BUSY ) )
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while ( TEST_FLAG( *ch0_csr, DMA_CH_CSR, BUSY ) )
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;
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;
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ok = TEST_FLAG( *ch0_csr, DMA_CH_CSR, DONE );
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ok = TEST_FLAG( *ch0_csr, DMA_CH_CSR, DONE );
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/* Dump contents of memory */
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/* Dump contents of memory */
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for ( i = 0; i < 10 && ok; ++ i )
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for ( i = 0; i < 10 && ok; ++ i )
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if ( dst[i] != src[i] )
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if ( dst[i] != src[i] )
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ok = 0;
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ok = 0;
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report( i );
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report( i );
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return ok;
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return ok;
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}
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}
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int main()
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int main()
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{
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{
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int pass_simple, pass_chunks, pass_list;
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int pass_simple, pass_chunks, pass_list;
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printf( "Starting DMA test\n" );
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printf( "Starting DMA test\n" );
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printf( " Simple DMA: " );
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printf( " Simple DMA: " );
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printf( (pass_simple = simple()) ? "Passed\n" : "Failed\n" );
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printf( (pass_simple = simple()) ? "Passed\n" : "Failed\n" );
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printf( " Chunks DMA: " );
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printf( " Chunks DMA: " );
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printf( (pass_chunks = chunks()) ? "Passed\n" : "Failed\n" );
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printf( (pass_chunks = chunks()) ? "Passed\n" : "Failed\n" );
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printf( " List DMA: " );
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printf( " List DMA: " );
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printf( (pass_list = list()) ? "Passed\n" : "Failed\n" );
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printf( (pass_list = list()) ? "Passed\n" : "Failed\n" );
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printf( "Ending DMA test\n" );
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printf( "Ending DMA test\n" );
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if (pass_simple && pass_chunks && pass_list) {
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if (pass_simple && pass_chunks && pass_list) {
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report (0xdeaddead);
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report (0xdeaddead);
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return 0;
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return 0;
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} else
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} else
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return 3 - pass_simple - pass_chunks - pass_list;
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return 3 - pass_simple - pass_chunks - pass_list;
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}
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}
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