/* op-support.c -- Support routines for micro operations
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/* op-support.c -- Support routines for micro operations
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "except.h"
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#include "except.h"
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#include "immu.h"
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#include "immu.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "execute.h"
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#include "execute.h"
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#include "sched.h"
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#include "sched.h"
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#include "i386-regs.h"
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#include "i386-regs.h"
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#include "dyn-rec.h"
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#include "dyn-rec.h"
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#include "op-support.h"
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#include "op-support.h"
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#include "simprintf.h"
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#include "simprintf.h"
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/* Stuff that is really a `micro' operation but is rather big (or for some other
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/* Stuff that is really a `micro' operation but is rather big (or for some other
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* reason like calling exit()) */
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* reason like calling exit()) */
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void op_support_nop_exit(void)
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void op_support_nop_exit(void)
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{
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{
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PRINTF("exit(%"PRIdREG")\n", cpu_state.reg[3]);
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PRINTF("exit(%"PRIdREG")\n", cpu_state.reg[3]);
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fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
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fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
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runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
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runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
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fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles,
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fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles,
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runtime.cpu.instructions);
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runtime.cpu.instructions);
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fprintf(stderr, " diff : cycles %lld, insn #%lld\n",
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fprintf(stderr, " diff : cycles %lld, insn #%lld\n",
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runtime.sim.cycles - runtime.sim.reset_cycles,
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runtime.sim.cycles - runtime.sim.reset_cycles,
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runtime.cpu.instructions - runtime.cpu.reset_instructions);
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runtime.cpu.instructions - runtime.cpu.reset_instructions);
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/* FIXME: Implement emulation of a stalled cpu
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/* FIXME: Implement emulation of a stalled cpu
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if (config.debug.gdb_enabled)
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if (config.debug.gdb_enabled)
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set_stall_state (1);
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set_stall_state (1);
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else {
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else {
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handle_sim_command();
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handle_sim_command();
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sim_done();
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sim_done();
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}
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}
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*/
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*/
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exit(0);
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exit(0);
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}
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}
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void op_support_nop_reset(void)
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void op_support_nop_reset(void)
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{
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{
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PRINTF("****************** counters reset ******************\n");
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PRINTF("****************** counters reset ******************\n");
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PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
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PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
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PRINTF("****************** counters reset ******************\n");
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PRINTF("****************** counters reset ******************\n");
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runtime.sim.reset_cycles = runtime.sim.cycles;
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runtime.sim.reset_cycles = runtime.sim.cycles;
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runtime.cpu.reset_instructions = runtime.cpu.instructions;
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runtime.cpu.reset_instructions = runtime.cpu.instructions;
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}
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}
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void op_support_nop_printf(void)
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void op_support_nop_printf(void)
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{
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{
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simprintf(cpu_state.reg[4], cpu_state.reg[3]);
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simprintf(cpu_state.reg[4], cpu_state.reg[3]);
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}
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}
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void op_support_nop_report(void)
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void op_support_nop_report(void)
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{
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{
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PRINTF("report(0x%"PRIxREG");\n", cpu_state.reg[3]);
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PRINTF("report(0x%"PRIxREG");\n", cpu_state.reg[3]);
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}
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}
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void op_support_nop_report_imm(int imm)
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void op_support_nop_report_imm(int imm)
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{
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{
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PRINTF("report %i (0x%"PRIxREG");\n", imm, cpu_state.reg[3]);
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PRINTF("report %i (0x%"PRIxREG");\n", imm, cpu_state.reg[3]);
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}
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}
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/* Handles a jump */
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/* Handles a jump */
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/* addr is a VIRTUAL address */
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/* addr is a VIRTUAL address */
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/* NOTE: We can't use env since this code is compiled like the rest of the
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/* NOTE: We can't use env since this code is compiled like the rest of the
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* simulator (most likely without -fomit-frame-pointer) and thus env will point
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* simulator (most likely without -fomit-frame-pointer) and thus env will point
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* to some bogus value. */
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* to some bogus value. */
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void do_jump(oraddr_t addr)
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void do_jump(oraddr_t addr)
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{
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{
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cpu_state.pc = addr;
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cpu_state.pc = addr;
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longjmp(cpu_state.excpt_loc, 0);
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longjmp(cpu_state.excpt_loc, 0);
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}
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}
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/* Wrapper around analysis() that contains all the recompiler specific stuff */
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/* Wrapper around analysis() that contains all the recompiler specific stuff */
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void op_support_analysis(void)
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void op_support_analysis(void)
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{
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{
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oraddr_t off = (cpu_state.pc & immu_state->page_offset_mask) >> 2;
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oraddr_t off = (cpu_state.pc & immu_state->page_offset_mask) >> 2;
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runtime.cpu.instructions++;
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runtime.cpu.instructions++;
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cpu_state.iqueue.insn_index = cpu_state.curr_page->insn_indexs[off];
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cpu_state.iqueue.insn_index = cpu_state.curr_page->insn_indexs[off];
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cpu_state.iqueue.insn = cpu_state.curr_page->insns[off];
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cpu_state.iqueue.insn = cpu_state.curr_page->insns[off];
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cpu_state.iqueue.insn_addr = cpu_state.pc;
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cpu_state.iqueue.insn_addr = cpu_state.pc;
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analysis(&cpu_state.iqueue);
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analysis(&cpu_state.iqueue);
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}
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}
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