/* acv-uart.c. UART test for Or1ksim
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/* acv-uart.c. UART test for Or1ksim
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 2010 Embecosm Limited
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Copyright (C) 2010 Embecosm Limited
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Contributors various OpenCores participants
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Contributors various OpenCores participants
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http: www.gnu.org/licenses/>. */
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with this program. If not, see <http: www.gnu.org/licenses/>. */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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/* UART test using ACV */
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/* UART test using ACV */
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "support.h"
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#include "support.h"
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/* use this macro to comment out nonworking parts */
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/* use this macro to comment out nonworking parts */
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#define COMPLETE 0
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#define COMPLETE 0
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/* Whether to do test in more detail */
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/* Whether to do test in more detail */
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#define DETAILED 0
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#define DETAILED 0
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#define UART_ADDR (0x9c000000)
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#define UART_ADDR (0x9c000000)
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#define UART_RBR (UART_ADDR + 0)
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#define UART_RBR (UART_ADDR + 0)
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#define UART_THR (UART_ADDR + 0)
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#define UART_THR (UART_ADDR + 0)
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#define UART_IER (UART_ADDR + 1)
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#define UART_IER (UART_ADDR + 1)
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#define UART_IIR (UART_ADDR + 2)
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#define UART_IIR (UART_ADDR + 2)
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#define UART_FCR (UART_ADDR + 2)
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#define UART_FCR (UART_ADDR + 2)
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#define UART_LCR (UART_ADDR + 3)
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#define UART_LCR (UART_ADDR + 3)
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#define UART_MCR (UART_ADDR + 4)
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#define UART_MCR (UART_ADDR + 4)
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#define UART_LSR (UART_ADDR + 5)
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#define UART_LSR (UART_ADDR + 5)
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#define UART_MSR (UART_ADDR + 6)
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#define UART_MSR (UART_ADDR + 6)
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#define UART_SCR (UART_ADDR + 7)
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#define UART_SCR (UART_ADDR + 7)
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#define UART_DLL (UART_ADDR + 0)
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#define UART_DLL (UART_ADDR + 0)
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#define UART_DLH (UART_ADDR + 1)
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#define UART_DLH (UART_ADDR + 1)
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#define LCR_DIVL (0x80)
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#define LCR_DIVL (0x80)
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#define LCR_BREAK (0x40)
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#define LCR_BREAK (0x40)
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#define LCR_STICK (0x20)
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#define LCR_STICK (0x20)
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#define LCR_EVENP (0x10)
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#define LCR_EVENP (0x10)
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#define LCR_PAREN (0x08)
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#define LCR_PAREN (0x08)
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#define LCR_NSTOP (0x04)
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#define LCR_NSTOP (0x04)
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#define LCR_NBITS (0x03)
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#define LCR_NBITS (0x03)
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#define LSR_DR (0x01)
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#define LSR_DR (0x01)
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#define LSR_OE (0x02)
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#define LSR_OE (0x02)
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#define LSR_PE (0x04)
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#define LSR_PE (0x04)
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#define LSR_FE (0x08)
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#define LSR_FE (0x08)
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#define LSR_BREAK (0x10)
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#define LSR_BREAK (0x10)
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#define LSR_TXFE (0x20)
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#define LSR_TXFE (0x20)
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#define LSR_TXE (0x40)
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#define LSR_TXE (0x40)
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#define LSR_ERR (0x80)
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#define LSR_ERR (0x80)
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#define UART_INT_LINE 19 /* To which interrupt is uart connected */
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#define UART_INT_LINE 19 /* To which interrupt is uart connected */
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/* fails if x is false */
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/* fails if x is false */
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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/* Waits a few cycles that uart can prepare its data */
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/* Waits a few cycles that uart can prepare its data */
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#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
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#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
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/* fails if there is an error */
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/* fails if there is an error */
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#define NO_ERROR() { unsigned x = getreg (UART_LSR); if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) \
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#define NO_ERROR() { unsigned x = getreg (UART_LSR); if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) \
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printf ("LSR7 (0x%02x) ERR @ %i\n", x, __LINE__); ASSERT(!(x & LSR_ERR) && ((x & 0x60) != 0x40));}
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printf ("LSR7 (0x%02x) ERR @ %i\n", x, __LINE__); ASSERT(!(x & LSR_ERR) && ((x & 0x60) != 0x40));}
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#define MARK() printf ("Passed line %i\n", __LINE__)
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#define MARK() printf ("Passed line %i\n", __LINE__)
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#ifndef __LINE__
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#ifndef __LINE__
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#define __LINE__ 0
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#define __LINE__ 0
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#endif
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#endif
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void fail (char *func, int line)
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void fail (char *func, int line)
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{
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{
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#ifndef __FUNCTION__
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#ifndef __FUNCTION__
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#define __FUNCTION__ "?"
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#define __FUNCTION__ "?"
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#endif
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#endif
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printf ("Test failed in %s:%i\n", func, line);
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printf ("Test failed in %s:%i\n", func, line);
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report(0xeeeeeeee);
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report(0xeeeeeeee);
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exit (1);
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exit (1);
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}
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}
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inline void setreg (unsigned long addr, unsigned char value)
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inline void setreg (unsigned long addr, unsigned char value)
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{
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{
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*((volatile unsigned char *)addr) = value;
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*((volatile unsigned char *)addr) = value;
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}
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}
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inline unsigned long getreg (unsigned long addr)
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inline unsigned long getreg (unsigned long addr)
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{
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{
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return *((volatile unsigned char *)addr);
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return *((volatile unsigned char *)addr);
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}
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}
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static volatile int int_cnt;
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static volatile int int_cnt;
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static volatile unsigned int_iir;
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static volatile unsigned int_iir;
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static volatile unsigned int_lsr;
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static volatile unsigned int_lsr;
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static int int_rbr;
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static int int_rbr;
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void interrupt_handler ()
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void interrupt_handler ()
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{
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{
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unsigned x;
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unsigned x;
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printf ("Int\n");
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printf ("Int\n");
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report(0xdeaddead);
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report(0xdeaddead);
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report(int_iir = getreg (UART_IIR));
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report(int_iir = getreg (UART_IIR));
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report(int_lsr = getreg (UART_LSR));
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report(int_lsr = getreg (UART_LSR));
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int_cnt++;
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int_cnt++;
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ASSERT (int_iir != 1);
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ASSERT (int_iir != 1);
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switch (int_iir & 0xf) {
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switch (int_iir & 0xf) {
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case 0x6: printf ("Receiver LS int.\n"); break;
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case 0x6: printf ("Receiver LS int.\n"); break;
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case 0x4: printf ("Received Data available. Expecting %02x, received %02x\n",
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case 0x4: printf ("Received Data available. Expecting %02x, received %02x\n",
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int_rbr, x = getreg(UART_RBR));
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int_rbr, x = getreg(UART_RBR));
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ASSERT (x == int_rbr);
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ASSERT (x == int_rbr);
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report (x);
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report (x);
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report (int_rbr);
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report (int_rbr);
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break;
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break;
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case 0xc: printf ("Character timeout. Expecting %02x, received %02x\n",
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case 0xc: printf ("Character timeout. Expecting %02x, received %02x\n",
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int_rbr, x = getreg(UART_RBR));
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int_rbr, x = getreg(UART_RBR));
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ASSERT (x == int_rbr);
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ASSERT (x == int_rbr);
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report (x);
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report (x);
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report (int_rbr);
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report (int_rbr);
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break;
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break;
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case 0x2: printf ("THR empty.\n"); break;
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case 0x2: printf ("THR empty.\n"); break;
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case 0x0: printf ("Modem Status.\n"); break;
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case 0x0: printf ("Modem Status.\n"); break;
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default:
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default:
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printf ("Invalid iir %x @ %i\n", int_iir, __LINE__);
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printf ("Invalid iir %x @ %i\n", int_iir, __LINE__);
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exit (1);
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exit (1);
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}
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}
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mtspr(SPR_PICSR, 0);
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mtspr(SPR_PICSR, 0);
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}
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}
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/* Receives a char and checks for errors */
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/* Receives a char and checks for errors */
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void recv_char (int ch)
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void recv_char (int ch)
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{
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{
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unsigned x;
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unsigned x;
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char r;
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char r;
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report (ch);
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report (ch);
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/* Wait for rx fifo to be */
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/* Wait for rx fifo to be */
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while (!((x = getreg (UART_LSR)) & LSR_DR));
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while (!((x = getreg (UART_LSR)) & LSR_DR));
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if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) printf ("LSR7 (0x%02x) ERR @ recv_char\n", x);
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if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) printf ("LSR7 (0x%02x) ERR @ recv_char\n", x);
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ASSERT(!(x & LSR_ERR));
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ASSERT(!(x & LSR_ERR));
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printf ("expected %02x, read %02x\n", ch, r = getreg (UART_RBR));
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printf ("expected %02x, read %02x\n", ch, r = getreg (UART_RBR));
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ASSERT (r == ch); /* compare character */
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ASSERT (r == ch); /* compare character */
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}
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}
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/* Sends a char and checks for errors */
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/* Sends a char and checks for errors */
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void send_char_no_wait (int ch)
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void send_char_no_wait (int ch)
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{
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{
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report (ch);
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report (ch);
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setreg (UART_THR, ch); /* send character */
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setreg (UART_THR, ch); /* send character */
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}
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}
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void send_char (int ch)
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void send_char (int ch)
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{
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{
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report (ch);
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report (ch);
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while (!(getreg (UART_LSR) & LSR_TXFE));
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while (!(getreg (UART_LSR) & LSR_TXFE));
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NO_ERROR();
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NO_ERROR();
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setreg (UART_THR, ch); /* send character */
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setreg (UART_THR, ch); /* send character */
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NO_ERROR();
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NO_ERROR();
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}
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}
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void init_8n1 ()
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void init_8n1 ()
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{
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{
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setreg (UART_IER, 0x00); /* disable interrupts */
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setreg (UART_IER, 0x00); /* disable interrupts */
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WAIT();
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WAIT();
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ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
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ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
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setreg (UART_FCR, 0x07); /* clear RX and TX FIFOs */
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setreg (UART_FCR, 0x07); /* clear RX and TX FIFOs */
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setreg (UART_LCR, LCR_DIVL);
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setreg (UART_LCR, LCR_DIVL);
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setreg (UART_DLH, 2 >> 8);
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setreg (UART_DLH, 2 >> 8);
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setreg (UART_DLL, 2 & 0xff);
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setreg (UART_DLL, 2 & 0xff);
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setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
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setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
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ASSERT(getreg (UART_LCR) == 0x03);
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ASSERT(getreg (UART_LCR) == 0x03);
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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}
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}
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/* Test reset values and r/w properties of some registers */
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/* Test reset values and r/w properties of some registers */
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void register_test ()
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void register_test ()
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{
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{
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printf ("register test\n");
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printf ("register test\n");
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MARK();
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MARK();
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{ /* test reset values */
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{ /* test reset values */
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ASSERT(getreg (UART_RBR) == 0x00); //0
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ASSERT(getreg (UART_RBR) == 0x00); //0
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ASSERT(getreg (UART_IER) == 0x00); //1
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ASSERT(getreg (UART_IER) == 0x00); //1
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ASSERT(getreg (UART_IIR) == 0xc1); //2
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ASSERT(getreg (UART_IIR) == 0xc1); //2
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ASSERT(getreg (UART_LCR) == 0x03); //3
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ASSERT(getreg (UART_LCR) == 0x03); //3
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ASSERT(getreg (UART_MCR) == 0x00); //4
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ASSERT(getreg (UART_MCR) == 0x00); //4
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ASSERT(getreg (UART_LSR) == 0x60); //5
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ASSERT(getreg (UART_LSR) == 0x60); //5
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ASSERT(getreg (UART_MSR) == 0x00); //6
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ASSERT(getreg (UART_MSR) == 0x00); //6
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ASSERT(getreg (UART_SCR) == 0x00); //7
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ASSERT(getreg (UART_SCR) == 0x00); //7
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setreg(UART_LCR, LCR_DIVL); //enable latches
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setreg(UART_LCR, LCR_DIVL); //enable latches
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLH) == 0x00); //1
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ASSERT(getreg (UART_DLH) == 0x00); //1
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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}
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}
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setreg(UART_LCR, 0x00); //disable latches igor
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setreg(UART_LCR, 0x00); //disable latches igor
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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MARK();
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MARK();
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{ /* test if status registers are read only */
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{ /* test if status registers are read only */
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unsigned long tmp;
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unsigned long tmp;
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int i;
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int i;
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tmp = getreg (UART_LSR);
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tmp = getreg (UART_LSR);
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setreg (UART_LSR, ~tmp);
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setreg (UART_LSR, ~tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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for (i = 0; i < 9; i++) {
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for (i = 0; i < 9; i++) {
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setreg (UART_LSR, 1 << i);
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setreg (UART_LSR, 1 << i);
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ASSERT(getreg (UART_LSR) == tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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}
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}
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tmp = getreg (UART_MSR);
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tmp = getreg (UART_MSR);
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setreg (UART_MSR, ~tmp);
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setreg (UART_MSR, ~tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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for (i = 0; i < 9; i++) {
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for (i = 0; i < 9; i++) {
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setreg (UART_MSR, 1 << i);
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setreg (UART_MSR, 1 << i);
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ASSERT(getreg (UART_MSR) == tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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}
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}
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}
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}
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MARK();
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MARK();
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{ /* test whether MCR is write only, be careful not to set the loopback bit */
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{ /* test whether MCR is write only, be careful not to set the loopback bit */
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ASSERT(getreg (UART_MCR) == 0x00);
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ASSERT(getreg (UART_MCR) == 0x00);
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setreg (UART_MCR, 0x45);
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setreg (UART_MCR, 0x45);
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ASSERT(getreg (UART_MCR) == 0x00);
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ASSERT(getreg (UART_MCR) == 0x00);
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setreg (UART_MCR, 0xaa);
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setreg (UART_MCR, 0xaa);
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ASSERT(getreg (UART_MCR) == 0x00);
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ASSERT(getreg (UART_MCR) == 0x00);
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}
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}
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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MARK();
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MARK();
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{ /* Test if Divisor latch byte holds the data */
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{ /* Test if Divisor latch byte holds the data */
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int i;
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int i;
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setreg(UART_LCR, LCR_DIVL); //enable latches
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setreg(UART_LCR, LCR_DIVL); //enable latches
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ASSERT(getreg (UART_LCR) == LCR_DIVL);
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ASSERT(getreg (UART_LCR) == LCR_DIVL);
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for (i = 0; i < 16; i++) {
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for (i = 0; i < 16; i++) {
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unsigned short tmp = 0xdead << i;
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unsigned short tmp = 0xdead << i;
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setreg (UART_DLH, tmp >> 8);
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setreg (UART_DLH, tmp >> 8);
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setreg (UART_DLL, tmp & 0xff);
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setreg (UART_DLL, tmp & 0xff);
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ASSERT(getreg (UART_DLL) == (tmp & 0xff)); //0
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ASSERT(getreg (UART_DLL) == (tmp & 0xff)); //0
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ASSERT(getreg (UART_DLH) == (tmp >> 8)); //1
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ASSERT(getreg (UART_DLH) == (tmp >> 8)); //1
|
}
|
}
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setreg (UART_DLH, 0xa1); //igor
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setreg (UART_DLH, 0xa1); //igor
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setreg (UART_DLH, 0xa1); //igor
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setreg (UART_DLH, 0xa1); //igor
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setreg (UART_DLH, 0xa1); //igor
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setreg (UART_DLH, 0xa1); //igor
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setreg (UART_DLH, 0xa1); //igor
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setreg (UART_DLH, 0xa1); //igor
|
setreg (UART_DLH, 0xa1); //igor
|
setreg (UART_DLH, 0xa1); //igor
|
|
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
for (i = 0; i < 16; i++) {
|
for (i = 0; i < 16; i++) {
|
unsigned short tmp = 0xdead << i;
|
unsigned short tmp = 0xdead << i;
|
setreg (UART_DLL, tmp >> 8);
|
setreg (UART_DLL, tmp >> 8);
|
setreg (UART_DLH, tmp & 0xff);
|
setreg (UART_DLH, tmp & 0xff);
|
ASSERT(getreg (UART_DLL) == (tmp >> 8)); //1
|
ASSERT(getreg (UART_DLL) == (tmp >> 8)); //1
|
ASSERT(getreg (UART_DLH) == (tmp & 0xff)); //0
|
ASSERT(getreg (UART_DLH) == (tmp & 0xff)); //0
|
}
|
}
|
setreg (UART_DLH, 0xa2); //igor
|
setreg (UART_DLH, 0xa2); //igor
|
setreg (UART_DLH, 0xa2); //igor
|
setreg (UART_DLH, 0xa2); //igor
|
setreg (UART_DLH, 0xa2); //igor
|
setreg (UART_DLH, 0xa2); //igor
|
setreg (UART_DLH, 0xa2); //igor
|
setreg (UART_DLH, 0xa2); //igor
|
setreg (UART_DLH, 0xa2); //igor
|
setreg (UART_DLH, 0xa2); //igor
|
|
|
setreg(UART_LCR, 0x00); //disable latches
|
setreg(UART_LCR, 0x00); //disable latches
|
ASSERT(getreg (UART_LCR) == 0x00);
|
ASSERT(getreg (UART_LCR) == 0x00);
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
}
|
}
|
MARK();
|
MARK();
|
{ /* Test LCR, if it holds our data */
|
{ /* Test LCR, if it holds our data */
|
int i;
|
int i;
|
for (i = 0; i < 6; i++) {
|
for (i = 0; i < 6; i++) {
|
unsigned short tmp = (0xde << i) & 0x3f;
|
unsigned short tmp = (0xde << i) & 0x3f;
|
setreg (UART_LCR, tmp);
|
setreg (UART_LCR, tmp);
|
ASSERT(getreg (UART_LCR) == tmp);
|
ASSERT(getreg (UART_LCR) == tmp);
|
}
|
}
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
}
|
}
|
setreg (UART_LCR, 0xa3); //igor
|
setreg (UART_LCR, 0xa3); //igor
|
setreg (UART_LCR, 0xa3); //igor
|
setreg (UART_LCR, 0xa3); //igor
|
setreg (UART_LCR, 0xa3); //igor
|
setreg (UART_LCR, 0xa3); //igor
|
setreg (UART_LCR, 0xa3); //igor
|
setreg (UART_LCR, 0xa3); //igor
|
setreg (UART_LCR, 0xa3); //igor
|
setreg (UART_LCR, 0xa3); //igor
|
|
|
MARK ();
|
MARK ();
|
|
|
{ /* SCR Test :))) */
|
{ /* SCR Test :))) */
|
int i;
|
int i;
|
setreg (UART_SCR, 0);
|
setreg (UART_SCR, 0);
|
ASSERT (getreg (UART_SCR) == 0);
|
ASSERT (getreg (UART_SCR) == 0);
|
setreg (UART_SCR, 0xff);
|
setreg (UART_SCR, 0xff);
|
ASSERT (getreg (UART_SCR) == 0xff);
|
ASSERT (getreg (UART_SCR) == 0xff);
|
for (i = 0; i < 16; i++) {
|
for (i = 0; i < 16; i++) {
|
unsigned char tmp = 0xdead << i;
|
unsigned char tmp = 0xdead << i;
|
setreg (UART_SCR, tmp);
|
setreg (UART_SCR, tmp);
|
ASSERT (getreg (UART_SCR) == tmp);
|
ASSERT (getreg (UART_SCR) == tmp);
|
}
|
}
|
}
|
}
|
setreg (UART_SCR, 0xa5);//igor
|
setreg (UART_SCR, 0xa5);//igor
|
setreg (UART_SCR, 0xa5);//igor
|
setreg (UART_SCR, 0xa5);//igor
|
setreg (UART_SCR, 0xa5);//igor
|
setreg (UART_SCR, 0xa5);//igor
|
setreg (UART_SCR, 0xa5);//igor
|
setreg (UART_SCR, 0xa5);//igor
|
setreg (UART_SCR, 0xa5);//igor
|
setreg (UART_SCR, 0xa5);//igor
|
|
|
MARK();
|
MARK();
|
/* Other registers will be tested later, if they function correctly,
|
/* Other registers will be tested later, if they function correctly,
|
since we cannot test them now, without destroying anything. */
|
since we cannot test them now, without destroying anything. */
|
}
|
}
|
|
|
/* Initializes uart and sends a few bytes to VAPI. It is then activated and send something back. */
|
/* Initializes uart and sends a few bytes to VAPI. It is then activated and send something back. */
|
|
|
void send_recv_test ()
|
void send_recv_test ()
|
{
|
{
|
char *s;
|
char *s;
|
printf ("send_recv_test\n");
|
printf ("send_recv_test\n");
|
/* Init */
|
/* Init */
|
MARK();
|
MARK();
|
|
|
//printf ("basic\n");
|
//printf ("basic\n");
|
ASSERT (!(getreg (UART_LSR) & LSR_DR));
|
ASSERT (!(getreg (UART_LSR) & LSR_DR));
|
MARK();
|
MARK();
|
|
|
/* Send a string */
|
/* Send a string */
|
s = "send_";
|
s = "send_";
|
while (*s) {
|
while (*s) {
|
/* Wait for tx fifo to be empty */
|
/* Wait for tx fifo to be empty */
|
send_char (*s);
|
send_char (*s);
|
report((unsigned long)*s);
|
report((unsigned long)*s);
|
s++;
|
s++;
|
}
|
}
|
ASSERT (!(getreg (UART_LSR) & LSR_DR));
|
ASSERT (!(getreg (UART_LSR) & LSR_DR));
|
s = "test_";
|
s = "test_";
|
while (*s) {
|
while (*s) {
|
/* Wait for tx fifo and tx to be empty */
|
/* Wait for tx fifo and tx to be empty */
|
while (!(getreg (UART_LSR) & LSR_TXE));
|
while (!(getreg (UART_LSR) & LSR_TXE));
|
NO_ERROR();
|
NO_ERROR();
|
setreg (UART_THR, *s); /* send character */
|
setreg (UART_THR, *s); /* send character */
|
NO_ERROR();
|
NO_ERROR();
|
s++;
|
s++;
|
}
|
}
|
ASSERT (!(getreg (UART_LSR) & LSR_DR));
|
ASSERT (!(getreg (UART_LSR) & LSR_DR));
|
MARK();
|
MARK();
|
|
|
/* Send characters with delay inbetween */
|
/* Send characters with delay inbetween */
|
s = "is_running";
|
s = "is_running";
|
while (*s) {
|
while (*s) {
|
int i;
|
int i;
|
send_char (*s);
|
send_char (*s);
|
// igor for (i = 0; i < 1600; i++) /* wait at least ten chars before sending next one */
|
// igor for (i = 0; i < 1600; i++) /* wait at least ten chars before sending next one */
|
for (i = 0; i < 16; i++) /* wait at few chars before sending next one */
|
for (i = 0; i < 16; i++) /* wait at few chars before sending next one */
|
asm volatile ("l.nop");
|
asm volatile ("l.nop");
|
s++;
|
s++;
|
}
|
}
|
|
|
send_char (0); /* send terminate char */
|
send_char (0); /* send terminate char */
|
MARK();
|
MARK();
|
|
|
/* Receives and compares the string */
|
/* Receives and compares the string */
|
s = "recv";
|
s = "recv";
|
while (*s) recv_char (*s++);
|
while (*s) recv_char (*s++);
|
MARK();
|
MARK();
|
printf ("OK\n");
|
printf ("OK\n");
|
}
|
}
|
|
|
/* sends break in both directions */
|
/* sends break in both directions */
|
|
|
void break_test ()
|
void break_test ()
|
{
|
{
|
unsigned x;
|
unsigned x;
|
char *s;
|
char *s;
|
printf ("break_test\n");
|
printf ("break_test\n");
|
|
|
MARK();
|
MARK();
|
/* Send a break */
|
/* Send a break */
|
NO_ERROR();
|
NO_ERROR();
|
MARK();
|
MARK();
|
setreg (UART_LCR, 0x03 | LCR_BREAK); /* 8N1 */
|
setreg (UART_LCR, 0x03 | LCR_BREAK); /* 8N1 */
|
MARK();
|
MARK();
|
send_char ('b'); /* make sure it is recognised as a break */
|
send_char ('b'); /* make sure it is recognised as a break */
|
MARK();
|
MARK();
|
recv_char ('*');
|
recv_char ('*');
|
setreg (UART_LCR, 0x03); /* deleting break bit, 8N1 */
|
setreg (UART_LCR, 0x03); /* deleting break bit, 8N1 */
|
MARK();
|
MARK();
|
|
|
/* Receive a break */
|
/* Receive a break */
|
send_char ('!');
|
send_char ('!');
|
MARK();
|
MARK();
|
while (!((x = getreg (UART_LSR)) & LSR_DR));
|
while (!((x = getreg (UART_LSR)) & LSR_DR));
|
/* we should receive zero character with broken frame and break bit should be set */
|
/* we should receive zero character with broken frame and break bit should be set */
|
printf("[%x]\n", (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
|
printf("[%x]\n", (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
|
ASSERT (x == (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
|
ASSERT (x == (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
|
ASSERT (getreg (UART_RBR) == 0);
|
ASSERT (getreg (UART_RBR) == 0);
|
MARK();
|
MARK();
|
|
|
/* Send a # to release break */
|
/* Send a # to release break */
|
setreg (UART_THR, '#');
|
setreg (UART_THR, '#');
|
while (!(getreg (UART_LSR) & LSR_DR));
|
while (!(getreg (UART_LSR) & LSR_DR));
|
NO_ERROR(); /* BREAK bit should be cleared now */
|
NO_ERROR(); /* BREAK bit should be cleared now */
|
ASSERT (getreg (UART_RBR) == '$');
|
ASSERT (getreg (UART_RBR) == '$');
|
MARK();
|
MARK();
|
|
|
/* Break while sending characters */
|
/* Break while sending characters */
|
s = "ns";
|
s = "ns";
|
while (*s) send_char (*s++);
|
while (*s) send_char (*s++);
|
ASSERT (!(getreg (UART_LSR) & LSR_DR));
|
ASSERT (!(getreg (UART_LSR) & LSR_DR));
|
while (!(getreg (UART_LSR) & LSR_TXE)); /* Wait till we send everything */
|
while (!(getreg (UART_LSR) & LSR_TXE)); /* Wait till we send everything */
|
/* this should break the * char, so it should not be received */
|
/* this should break the * char, so it should not be received */
|
setreg (UART_THR, '*');
|
setreg (UART_THR, '*');
|
setreg (UART_LCR, 0x3 | LCR_BREAK);
|
setreg (UART_LCR, 0x3 | LCR_BREAK);
|
MARK();
|
MARK();
|
|
|
/* Drop the break, when we get acknowledge */
|
/* Drop the break, when we get acknowledge */
|
recv_char ('?');
|
recv_char ('?');
|
setreg (UART_LCR, 0x3);
|
setreg (UART_LCR, 0x3);
|
NO_ERROR();
|
NO_ERROR();
|
MARK();
|
MARK();
|
|
|
/* Receive a break */
|
/* Receive a break */
|
send_char ('#');
|
send_char ('#');
|
while (!((x = getreg (UART_LSR)) & LSR_DR));
|
while (!((x = getreg (UART_LSR)) & LSR_DR));
|
/* we should receive zero character with broken frame and break bit
|
/* we should receive zero character with broken frame and break bit
|
should not be set, because we cleared it */
|
should not be set, because we cleared it */
|
printf("[%x:%x]\n", x, (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
|
printf("[%x:%x]\n", x, (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
|
ASSERT (x == (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
|
ASSERT (x == (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
|
ASSERT (getreg (UART_RBR) == 0);
|
ASSERT (getreg (UART_RBR) == 0);
|
MARK();
|
MARK();
|
send_char ('?');
|
send_char ('?');
|
MARK();
|
MARK();
|
while (!(getreg (UART_LSR) & LSR_DR));
|
while (!(getreg (UART_LSR) & LSR_DR));
|
recv_char ('!');
|
recv_char ('!');
|
printf ("OK\n");
|
printf ("OK\n");
|
}
|
}
|
|
|
/* Tries to send data in different modes in both directions */
|
/* Tries to send data in different modes in both directions */
|
|
|
/* Utility function, that tests current configuration */
|
/* Utility function, that tests current configuration */
|
void test_mode (int nbits)
|
void test_mode (int nbits)
|
{
|
{
|
unsigned mask = (1 << nbits) - 1;
|
unsigned mask = (1 << nbits) - 1;
|
send_char (0x55);
|
send_char (0x55);
|
#if DETAILED
|
#if DETAILED
|
send_char (0x55);
|
send_char (0x55);
|
recv_char (0x55 & mask);
|
recv_char (0x55 & mask);
|
#endif
|
#endif
|
recv_char (0x55 & mask);
|
recv_char (0x55 & mask);
|
send_char ('a'); // 0x61
|
send_char ('a'); // 0x61
|
#if DETAILED
|
#if DETAILED
|
send_char ('a'); // 0x61
|
send_char ('a'); // 0x61
|
recv_char ('a' & mask);
|
recv_char ('a' & mask);
|
#endif
|
#endif
|
recv_char ('a' & mask);
|
recv_char ('a' & mask);
|
}
|
}
|
|
|
void different_modes_test ()
|
void different_modes_test ()
|
{
|
{
|
int speed, parity, length;
|
int speed, parity, length;
|
printf ("different modes test\n");
|
printf ("different modes test\n");
|
init_8n1();
|
init_8n1();
|
|
|
/* Init */
|
/* Init */
|
MARK();
|
MARK();
|
ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
|
ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
|
MARK();
|
MARK();
|
|
|
/* Test different speeds */
|
/* Test different speeds */
|
for (speed = 1; speed < 5; speed++) {
|
for (speed = 1; speed < 5; speed++) {
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_DLH, speed >> 8);
|
setreg (UART_DLH, speed >> 8);
|
setreg (UART_DLL, speed & 0xff);
|
setreg (UART_DLL, speed & 0xff);
|
setreg (UART_LCR, 0x03); /* 8N1 @ 10 => 160 instructions for one cycle */
|
setreg (UART_LCR, 0x03); /* 8N1 @ 10 => 160 instructions for one cycle */
|
test_mode (8);
|
test_mode (8);
|
MARK();
|
MARK();
|
}
|
}
|
MARK();
|
MARK();
|
|
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_DLH, 1 >> 8);
|
setreg (UART_DLH, 1 >> 8);
|
setreg (UART_DLL, 1 & 0xff);
|
setreg (UART_DLL, 1 & 0xff);
|
MARK();
|
MARK();
|
|
|
/* Test all parity modes with different char lengths */
|
/* Test all parity modes with different char lengths */
|
for (parity = 0; parity < 8; parity++)
|
for (parity = 0; parity < 8; parity++)
|
for (length = 0; length < 4; length++) {
|
for (length = 0; length < 4; length++) {
|
setreg (UART_LCR, length | (0 << 2) | (parity << 3));
|
setreg (UART_LCR, length | (0 << 2) | (parity << 3));
|
test_mode (5 + length);
|
test_mode (5 + length);
|
MARK();
|
MARK();
|
}
|
}
|
MARK();
|
MARK();
|
|
|
/* Test configuration, if we have >1 stop bits */
|
/* Test configuration, if we have >1 stop bits */
|
for (length = 0; length < 4; length++) {
|
for (length = 0; length < 4; length++) {
|
setreg (UART_LCR, length | (1 << 2) | (0 << 3));
|
setreg (UART_LCR, length | (1 << 2) | (0 << 3));
|
test_mode (5 + length);
|
test_mode (5 + length);
|
MARK();
|
MARK();
|
}
|
}
|
MARK();
|
MARK();
|
|
|
/* Restore normal mode */
|
/* Restore normal mode */
|
send_char ('T');
|
send_char ('T');
|
while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
|
while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_DLH, 2 >> 8);
|
setreg (UART_DLH, 2 >> 8);
|
setreg (UART_DLL, 2 & 0xff);
|
setreg (UART_DLL, 2 & 0xff);
|
setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
|
setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
|
MARK();
|
MARK();
|
while (!(getreg (UART_LSR) & 1)); /* Receive 'x' char */
|
while (!(getreg (UART_LSR) & 1)); /* Receive 'x' char */
|
getreg (UART_RBR);
|
getreg (UART_RBR);
|
MARK();
|
MARK();
|
|
|
send_char ('T');
|
send_char ('T');
|
while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
|
while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
|
MARK();
|
MARK();
|
printf ("OK\n");
|
printf ("OK\n");
|
}
|
}
|
|
|
/* Test various FIFO levels, break and framing error interrupt, etc */
|
/* Test various FIFO levels, break and framing error interrupt, etc */
|
|
|
void interrupt_test ()
|
void interrupt_test ()
|
{
|
{
|
int i;
|
int i;
|
printf ("interrupt_test\n");
|
printf ("interrupt_test\n");
|
/* Configure UART for interrupt mode */
|
/* Configure UART for interrupt mode */
|
ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
|
ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_DLH, 12 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
|
setreg (UART_DLH, 12 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
|
setreg (UART_DLL, 6 & 0xff);
|
setreg (UART_DLL, 6 & 0xff);
|
setreg (UART_LCR, 0x03); /* 8N1 @ 6 */
|
setreg (UART_LCR, 0x03); /* 8N1 @ 6 */
|
|
|
ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */
|
ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */
|
setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
|
setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
|
setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
|
setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
|
|
|
while (!int_cnt); /* Clear previous THR interrupt */
|
while (!int_cnt); /* Clear previous THR interrupt */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
|
|
/* I am configured - start interrupt test */
|
/* I am configured - start interrupt test */
|
send_char ('I');
|
send_char ('I');
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
|
|
int_rbr = '0';
|
int_rbr = '0';
|
while (!int_cnt); /* Wait for DR */
|
while (!int_cnt); /* Wait for DR */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc4);
|
ASSERT (int_iir == 0xc4);
|
ASSERT (int_lsr == 0x61);
|
ASSERT (int_lsr == 0x61);
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
MARK();
|
MARK();
|
|
|
setreg (UART_FCR, 0x41); /* Set trigger level = 4 chars, fifo should not be reset */
|
setreg (UART_FCR, 0x41); /* Set trigger level = 4 chars, fifo should not be reset */
|
|
|
/* Everything ok here, send me 4 more */
|
/* Everything ok here, send me 4 more */
|
send_char ('I');
|
send_char ('I');
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
|
|
int_rbr = '1';
|
int_rbr = '1';
|
while (!int_cnt); /* Wait for DR */
|
while (!int_cnt); /* Wait for DR */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc4);
|
ASSERT (int_iir == 0xc4);
|
ASSERT (int_lsr == 0x61);
|
ASSERT (int_lsr == 0x61);
|
MARK();
|
MARK();
|
|
|
setreg (UART_FCR, 0x81); /* Set trigger level = 8 chars, fifo should not be reset */
|
setreg (UART_FCR, 0x81); /* Set trigger level = 8 chars, fifo should not be reset */
|
|
|
/* Everything ok here, send me 5 more */
|
/* Everything ok here, send me 5 more */
|
send_char ('I');
|
send_char ('I');
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
|
|
int_rbr = '2';
|
int_rbr = '2';
|
while (!int_cnt); /* Wait for DR */
|
while (!int_cnt); /* Wait for DR */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc4);
|
ASSERT (int_iir == 0xc4);
|
ASSERT (int_lsr == 0x61);
|
ASSERT (int_lsr == 0x61);
|
MARK();
|
MARK();
|
|
|
setreg (UART_FCR, 0xc1); /* Set trigger level = 14 chars, fifo should not be reset */
|
setreg (UART_FCR, 0xc1); /* Set trigger level = 14 chars, fifo should not be reset */
|
|
|
/* Everything ok here, send me 7 more */
|
/* Everything ok here, send me 7 more */
|
send_char ('I');
|
send_char ('I');
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
|
|
int_rbr = '3';
|
int_rbr = '3';
|
while (!int_cnt); /* Wait for DR */
|
while (!int_cnt); /* Wait for DR */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc4);
|
ASSERT (int_iir == 0xc4);
|
ASSERT (int_lsr == 0x61);
|
ASSERT (int_lsr == 0x61);
|
MARK();
|
MARK();
|
|
|
/* Everything ok here, send me 4 more - fifo should be full OE should occur */
|
/* Everything ok here, send me 4 more - fifo should be full OE should occur */
|
setreg (UART_IER, 0x06); /* Enable interrupts: line status, THR empty */
|
setreg (UART_IER, 0x06); /* Enable interrupts: line status, THR empty */
|
send_char ('I');
|
send_char ('I');
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
|
|
while (!int_cnt); /* Wait for OE */
|
while (!int_cnt); /* Wait for OE */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_lsr == 0xe3); /* OE flag should be set */
|
ASSERT (int_lsr == 0xe3); /* OE flag should be set */
|
ASSERT (getreg (UART_LSR) == 0x61); /* LSR should be cleared by previous read */
|
ASSERT (getreg (UART_LSR) == 0x61); /* LSR should be cleared by previous read */
|
ASSERT (getreg (UART_IIR) == 0xc1); /* No interrupts should be pending */
|
ASSERT (getreg (UART_IIR) == 0xc1); /* No interrupts should be pending */
|
MARK();
|
MARK();
|
|
|
/* Check if we got everything */
|
/* Check if we got everything */
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
for (i = 0; i < 3; i++) {
|
for (i = 0; i < 3; i++) {
|
recv_char ("456"[i]); /* WARNING: read should not cause interrupt even if we step over trigger */
|
recv_char ("456"[i]); /* WARNING: read should not cause interrupt even if we step over trigger */
|
MARK ();
|
MARK ();
|
}
|
}
|
/* It is now safe to enable data ready interrupt */
|
/* It is now safe to enable data ready interrupt */
|
setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
|
setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
|
|
|
/* Check if we got everything */
|
/* Check if we got everything */
|
for (i = 0; i < 13; i++) {
|
for (i = 0; i < 13; i++) {
|
recv_char ("789abcdefghij"[i]); /* WARNING: read should not cause interrupt even if we step over trigger */
|
recv_char ("789abcdefghij"[i]); /* WARNING: read should not cause interrupt even if we step over trigger */
|
MARK ();
|
MARK ();
|
}
|
}
|
|
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
ASSERT (getreg (UART_LSR) == 0x60); /* FIFO should be empty */
|
ASSERT (getreg (UART_LSR) == 0x60); /* FIFO should be empty */
|
|
|
getreg (UART_RBR); /* check for FIFO counter overflow - fifo must still be empty */
|
getreg (UART_RBR); /* check for FIFO counter overflow - fifo must still be empty */
|
ASSERT (getreg (UART_LSR) == 0x60); /* FIFO should be empty */
|
ASSERT (getreg (UART_LSR) == 0x60); /* FIFO should be empty */
|
|
|
/* check for break interrupt */
|
/* check for break interrupt */
|
send_char ('I');
|
send_char ('I');
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
|
|
while (!int_cnt); /* Wait for break interrupt */
|
while (!int_cnt); /* Wait for break interrupt */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_lsr == 0xf1); /* BE flag should be set */
|
ASSERT (int_lsr == 0xf1); /* BE flag should be set */
|
ASSERT (getreg (UART_LSR) == 0x61); /* BE flag should be cleared by previous read */
|
ASSERT (getreg (UART_LSR) == 0x61); /* BE flag should be cleared by previous read */
|
MARK();
|
MARK();
|
recv_char (0);
|
recv_char (0);
|
MARK();
|
MARK();
|
|
|
send_char ('B'); /* Release break */
|
send_char ('B'); /* Release break */
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
/* Wait for acknowledge */
|
/* Wait for acknowledge */
|
int_rbr = '$';
|
int_rbr = '$';
|
while (!int_cnt); /* Wait for timeout */
|
while (!int_cnt); /* Wait for timeout */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xcc);
|
ASSERT (int_iir == 0xcc);
|
ASSERT (int_lsr == 0x61);
|
ASSERT (int_lsr == 0x61);
|
MARK();
|
MARK();
|
|
|
/* TODO: Check for parity error */
|
/* TODO: Check for parity error */
|
/* TODO: Check for frame error */
|
/* TODO: Check for frame error */
|
|
|
/* Check for timeout */
|
/* Check for timeout */
|
send_char ('I');
|
send_char ('I');
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
|
|
int_rbr = 'T';
|
int_rbr = 'T';
|
while (!int_cnt); /* Wait for timeout */
|
while (!int_cnt); /* Wait for timeout */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xcc); /* timeout interrupt occured */
|
ASSERT (int_iir == 0xcc); /* timeout interrupt occured */
|
ASSERT (int_lsr == 0x61); /* DR flag should be set */
|
ASSERT (int_lsr == 0x61); /* DR flag should be set */
|
ASSERT (getreg (UART_LSR) == 0x60); /* DR flag should be cleared - timeout occurred */
|
ASSERT (getreg (UART_LSR) == 0x60); /* DR flag should be cleared - timeout occurred */
|
MARK();
|
MARK();
|
|
|
send_char ('T');
|
send_char ('T');
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
|
|
setreg (UART_IER, 0x00); /* Disable interrupts */
|
setreg (UART_IER, 0x00); /* Disable interrupts */
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
NO_ERROR ();
|
NO_ERROR ();
|
|
|
while (getreg (UART_LSR) != 0x60); /* wait till we sent everynthing and then change mode */
|
while (getreg (UART_LSR) != 0x60); /* wait till we sent everynthing and then change mode */
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_DLH, 2 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
|
setreg (UART_DLH, 2 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
|
setreg (UART_DLL, 2 & 0xff);
|
setreg (UART_DLL, 2 & 0xff);
|
setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
|
setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
|
send_char ('T');
|
send_char ('T');
|
|
|
MARK ();
|
MARK ();
|
printf ("OK\n");
|
printf ("OK\n");
|
}
|
}
|
|
|
/* Test if all control bits are set correctly. Lot of this was already tested
|
/* Test if all control bits are set correctly. Lot of this was already tested
|
elsewhere and tests are not duplicated. */
|
elsewhere and tests are not duplicated. */
|
|
|
void control_register_test ()
|
void control_register_test ()
|
{
|
{
|
/* RBR already tested in send_recv_test() */
|
/* RBR already tested in send_recv_test() */
|
/* THR already tested in send_recv_test() */
|
/* THR already tested in send_recv_test() */
|
/* IER already tested in interrupt_test() */
|
/* IER already tested in interrupt_test() */
|
/* IIR already tested in interrupt_test() */
|
/* IIR already tested in interrupt_test() */
|
/* FCR0 - uart 16450 specific, not tested */
|
/* FCR0 - uart 16450 specific, not tested */
|
|
|
/* FCR1 - reset rx FIFO */
|
/* FCR1 - reset rx FIFO */
|
send_char ('*');
|
send_char ('*');
|
NO_ERROR ();
|
NO_ERROR ();
|
while (!(getreg (UART_LSR) & 0x01)); /* Wait for data ready */
|
while (!(getreg (UART_LSR) & 0x01)); /* Wait for data ready */
|
setreg (UART_FCR, 2); /* Clears rx fifo */
|
setreg (UART_FCR, 2); /* Clears rx fifo */
|
ASSERT (getreg (UART_LSR) == 0x60); /* nothing happening */
|
ASSERT (getreg (UART_LSR) == 0x60); /* nothing happening */
|
send_char ('!');
|
send_char ('!');
|
recv_char ('!');
|
recv_char ('!');
|
MARK ();
|
MARK ();
|
|
|
/* Make sure the TX fifo and the TX serial reg. are empty */
|
/* Make sure the TX fifo and the TX serial reg. are empty */
|
ASSERT (getreg (UART_LSR) & LSR_TXFE);
|
ASSERT (getreg (UART_LSR) & LSR_TXFE);
|
ASSERT (getreg (UART_LSR) & LSR_TXE);
|
ASSERT (getreg (UART_LSR) & LSR_TXE);
|
|
|
/* FCR2 - reset tx FIFO */
|
/* FCR2 - reset tx FIFO */
|
send_char_no_wait ('1');
|
send_char_no_wait ('1');
|
send_char_no_wait ('2');
|
send_char_no_wait ('2');
|
// send_char ('1');
|
// send_char ('1');
|
// send_char ('2');
|
// send_char ('2');
|
setreg (UART_FCR, 4); /* Should clear '2' from fifo, but '1' should be sent OK */
|
setreg (UART_FCR, 4); /* Should clear '2' from fifo, but '1' should be sent OK */
|
ASSERT (getreg (UART_LSR) == 0x20); /* we should still be sending '1' */
|
ASSERT (getreg (UART_LSR) == 0x20); /* we should still be sending '1' */
|
NO_ERROR();
|
NO_ERROR();
|
send_char ('*');
|
send_char ('*');
|
recv_char ('*');
|
recv_char ('*');
|
MARK ();
|
MARK ();
|
|
|
/* LCR already tested in different_modes_test () */
|
/* LCR already tested in different_modes_test () */
|
/* TODO: MSR */
|
/* TODO: MSR */
|
/* LSR already tested in different_modes_test () and interrupt_test() */
|
/* LSR already tested in different_modes_test () and interrupt_test() */
|
/* SCR already tested in register_test () */
|
/* SCR already tested in register_test () */
|
|
|
MARK ();
|
MARK ();
|
printf ("OK\n");
|
printf ("OK\n");
|
}
|
}
|
|
|
/* Tests parity error and frame error behaviour */
|
/* Tests parity error and frame error behaviour */
|
|
|
void line_error_test ()
|
void line_error_test ()
|
{
|
{
|
printf ("line_error_test\n");
|
printf ("line_error_test\n");
|
|
|
/* Test framing error if we change speed */
|
/* Test framing error if we change speed */
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_DLH, 12 >> 8);
|
setreg (UART_DLH, 12 >> 8);
|
setreg (UART_DLL, 12 & 0xff);
|
setreg (UART_DLL, 12 & 0xff);
|
setreg (UART_LCR, 0x03); /* 8N1 @ 3 */
|
setreg (UART_LCR, 0x03); /* 8N1 @ 3 */
|
MARK();
|
MARK();
|
|
|
send_char ('c');
|
send_char ('c');
|
ASSERT (int_cnt == 0);
|
ASSERT (int_cnt == 0);
|
setreg (UART_IER, 0x04); /* Enable interrupts: line status */
|
setreg (UART_IER, 0x04); /* Enable interrupts: line status */
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_lsr == 0xe9); /* Framing error and FIFO error */
|
ASSERT (int_lsr == 0xe9); /* Framing error and FIFO error */
|
getreg (UART_RBR); /* Ignore the data */
|
getreg (UART_RBR); /* Ignore the data */
|
MARK ();
|
MARK ();
|
recv_char ('b');
|
recv_char ('b');
|
MARK ();
|
MARK ();
|
|
|
#if COMPLETE
|
#if COMPLETE
|
/* Test framing error if we change stop bits */
|
/* Test framing error if we change stop bits */
|
send_char ('*');
|
send_char ('*');
|
while (getreg (UART_LSR)); /* wait till we sent everynthing and then change mode */
|
while (getreg (UART_LSR)); /* wait till we sent everynthing and then change mode */
|
setreg (UART_LCR, 0x07); /* 8N2 */
|
setreg (UART_LCR, 0x07); /* 8N2 */
|
send_char ('*');
|
send_char ('*');
|
MARK ();
|
MARK ();
|
|
|
ASSERT (int_cnt == 0);
|
ASSERT (int_cnt == 0);
|
setreg (UART_IER, 0x04); /* Enable interrupts: line status */
|
setreg (UART_IER, 0x04); /* Enable interrupts: line status */
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_lsr == 0xe9); /* Framing error and FIFO error */
|
ASSERT (int_lsr == 0xe9); /* Framing error and FIFO error */
|
getreg (UART_RBR); /* Ignore the data */
|
getreg (UART_RBR); /* Ignore the data */
|
recv_char ('b');
|
recv_char ('b');
|
MARK();
|
MARK();
|
#endif
|
#endif
|
|
|
MARK ();
|
MARK ();
|
printf ("OK\n");
|
printf ("OK\n");
|
}
|
}
|
|
|
int main ()
|
int main ()
|
{
|
{
|
/* Use our low priority interrupt handler */
|
/* Use our low priority interrupt handler */
|
excpt_int = (unsigned long)interrupt_handler;
|
excpt_int = (unsigned long)interrupt_handler;
|
|
|
/* Enable interrupts */
|
/* Enable interrupts */
|
mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
|
mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
|
mtspr (SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << UART_INT_LINE));
|
mtspr (SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << UART_INT_LINE));
|
|
|
int_cnt = 0;
|
int_cnt = 0;
|
int_iir = 0;
|
int_iir = 0;
|
int_lsr = 0;
|
int_lsr = 0;
|
int_rbr = 0;
|
int_rbr = 0;
|
|
|
register_test ();
|
register_test ();
|
init_8n1 ();
|
init_8n1 ();
|
send_recv_test ();
|
send_recv_test ();
|
break_test ();
|
break_test ();
|
different_modes_test ();
|
different_modes_test ();
|
interrupt_test ();
|
interrupt_test ();
|
control_register_test ();
|
control_register_test ();
|
line_error_test ();
|
line_error_test ();
|
|
|
/* loopback_test ();
|
/* loopback_test ();
|
modem_test ();
|
modem_test ();
|
modem_error_test ();*/
|
modem_error_test ();*/
|
recv_char ('@');
|
recv_char ('@');
|
printf ("ALL TESTS PASSED\n");
|
printf ("ALL TESTS PASSED\n");
|
return 0;
|
return 0;
|
}
|
}
|
|
|
