/* is-spr-test.S. l.mfspr and l.mtspr instruction test of Or1ksim
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/* is-spr-test.S. l.mfspr and l.mtspr instruction test of Or1ksim
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*
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*
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* Copyright (C) 1999-2006 OpenCores
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* Copyright (C) 1999-2006 OpenCores
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* Copyright (C) 2010 Embecosm Limited
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* Copyright (C) 2010 Embecosm Limited
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*
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*
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* Contributors various OpenCores participants
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* Contributors various OpenCores participants
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* Contributor Jeremy Bennett
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* Contributor Jeremy Bennett
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*
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*
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* This file is part of OpenRISC 1000 Architectural Simulator.
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* This file is part of OpenRISC 1000 Architectural Simulator.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 3 of the License, or (at your option)
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* Software Foundation; either version 3 of the License, or (at your option)
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* any later version.
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* any later version.
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*
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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* more details.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see .
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* with this program. If not, see .
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*/
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*/
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Coding conventions are described in inst-set-test.S
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* Coding conventions are described in inst-set-test.S
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Test coverage
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* Test coverage
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*
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*
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* The l.mfspr and l.mtspr should OR the immdediate operand with the register
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* The l.mfspr and l.mtspr should OR the immdediate operand with the register
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* to determine the SPR address, not add it (Bug 1779).
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* to determine the SPR address, not add it (Bug 1779).
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*
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*
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* Having fixed the problem, this is (in good software engineering style), a
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* Having fixed the problem, this is (in good software engineering style), a
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* regresison test to go with the fix.
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* regresison test to go with the fix.
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*
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*
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* This is not a comprehensive test of either instruction (yet).
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* This is not a comprehensive test of either instruction (yet).
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*
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*
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* Of course what is really needed is a comprehensive instruction test...
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* Of course what is really needed is a comprehensive instruction test...
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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#include "inst-set-test.h"
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#include "inst-set-test.h"
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* A macro to carry out a test of l.mfspr
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* A macro to carry out a test of l.mfspr
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*
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*
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* MACLO is used as the SPR, since it can be read and cleared using l.macrc
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* MACLO is used as the SPR, since it can be read and cleared using l.macrc
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* and can be set using l.maci. op1 and op2 should be chosen to address this
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* and can be set using l.maci. op1 and op2 should be chosen to address this
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* register.
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* register.
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*
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*
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* The value placed in the register is entirely arbitrary - we use 0xdeadbeef.
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* The value placed in the register is entirely arbitrary - we use 0xdeadbeef.
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*
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*
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* Arguments
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* Arguments
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* op1: First l.mfspr operand value
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* op1: First l.mfspr operand value
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* op2: Second l.mfspr operand value
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* op2: Second l.mfspr operand value
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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#define TEST_MFSPR(op1, op2) \
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#define TEST_MFSPR(op1, op2) \
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l.macrc r2 ;\
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l.macrc r2 ;\
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LOAD_CONST (r2,0xdeadbeef) ;\
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LOAD_CONST (r2,0xdeadbeef) ;\
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l.maci r2,1 ;\
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l.maci r2,1 ;\
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;\
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;\
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l.mfspr r3,r0,SPR_SR ;\
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l.mfspr r3,r0,SPR_SR ;\
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LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\
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LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\
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l.and r3,r3,r2 /* Clear flags */ ;\
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l.and r3,r3,r2 /* Clear flags */ ;\
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l.mtspr r0,r3,SPR_SR ;\
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l.mtspr r0,r3,SPR_SR ;\
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;\
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;\
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LOAD_CONST (r5,op1) /* First operand in register */ ;\
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LOAD_CONST (r5,op1) /* First operand in register */ ;\
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l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
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l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
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50: l.mfspr r4,r5,op2 ;\
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50: l.mfspr r4,r5,op2 ;\
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l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
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l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
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PUSH (r2) /* Save EPCR for later */ ;\
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PUSH (r2) /* Save EPCR for later */ ;\
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PUSH (r4) /* Save result for later */ ;\
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PUSH (r4) /* Save result for later */ ;\
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;\
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;\
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PUTS (" l.mfspr 0x") ;\
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PUTS (" l.mfspr 0x") ;\
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PUTH (op1) ;\
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PUTH (op1) ;\
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PUTS (" | 0x") ;\
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PUTS (" | 0x") ;\
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PUTHH (op2) ;\
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PUTHH (op2) ;\
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PUTS (": ") ;\
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PUTS (": ") ;\
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POP (r4) ;\
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POP (r4) ;\
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CHECK_RES1 (r4, 0xdeadbeef) ;\
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CHECK_RES1 (r4, 0xdeadbeef) ;\
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;\
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;\
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LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
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LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
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l.and r2,r2,r4 ;\
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l.and r2,r2,r4 ;\
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l.sfeq r2,r4 ;\
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l.sfeq r2,r4 ;\
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l.bnf 51f ;\
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l.bnf 51f ;\
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;\
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;\
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PUTS (" - exception triggered: TRUE\n") ;\
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PUTS (" - exception triggered: TRUE\n") ;\
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l.j 52f ;\
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l.j 52f ;\
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l.nop ;\
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l.nop ;\
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;\
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;\
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51: PUTS (" - exception triggered: FALSE\n") ;\
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51: PUTS (" - exception triggered: FALSE\n") ;\
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52:
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52:
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* A macro to carry out a test of l.mtspr
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* A macro to carry out a test of l.mtspr
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*
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*
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* MACLO is used as the SPR, since it can be read and cleared using l.macrc.
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* MACLO is used as the SPR, since it can be read and cleared using l.macrc.
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* op1 and op2 should be chosen to address this register.
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* op1 and op2 should be chosen to address this register.
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*
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*
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* The value placed in the register is entirely arbitrary - we use 0xdeadbeef.
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* The value placed in the register is entirely arbitrary - we use 0xdeadbeef.
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*
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*
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* Arguments
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* Arguments
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* op1: First l.mfspr operand value
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* op1: First l.mfspr operand value
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* op2: Second l.mfspr operand value
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* op2: Second l.mfspr operand value
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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#define TEST_MTSPR(op1, op2) \
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#define TEST_MTSPR(op1, op2) \
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l.macrc r2 ;\
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l.macrc r2 ;\
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;\
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;\
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l.mfspr r3,r0,SPR_SR ;\
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l.mfspr r3,r0,SPR_SR ;\
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LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\
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LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\
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l.and r3,r3,r2 /* Clear flags */ ;\
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l.and r3,r3,r2 /* Clear flags */ ;\
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l.mtspr r0,r3,SPR_SR ;\
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l.mtspr r0,r3,SPR_SR ;\
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;\
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;\
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LOAD_CONST (r5,op1) /* First operand in register */ ;\
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LOAD_CONST (r5,op1) /* First operand in register */ ;\
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LOAD_CONST (r4,0xdeadbeef) /* First operand in register */ ;\
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LOAD_CONST (r4,0xdeadbeef) /* First operand in register */ ;\
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l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
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l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
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50: l.mtspr r5,r4,op2 ;\
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50: l.mtspr r5,r4,op2 ;\
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l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
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l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
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PUSH (r2) /* Save EPCR for later */ ;\
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PUSH (r2) /* Save EPCR for later */ ;\
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l.macrc r4 ;\
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l.macrc r4 ;\
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PUSH (r4) /* Save result for later */ ;\
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PUSH (r4) /* Save result for later */ ;\
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;\
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;\
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PUTS (" l.mtspr 0x") ;\
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PUTS (" l.mtspr 0x") ;\
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PUTH (op1) ;\
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PUTH (op1) ;\
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PUTS (" | 0x") ;\
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PUTS (" | 0x") ;\
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PUTHH (op2) ;\
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PUTHH (op2) ;\
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PUTS (": ") ;\
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PUTS (": ") ;\
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POP (r4) ;\
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POP (r4) ;\
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CHECK_RES1 (r4, 0xdeadbeef) ;\
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CHECK_RES1 (r4, 0xdeadbeef) ;\
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;\
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;\
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LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
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LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
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l.and r2,r2,r4 ;\
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l.and r2,r2,r4 ;\
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l.sfeq r2,r4 ;\
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l.sfeq r2,r4 ;\
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l.bnf 51f ;\
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l.bnf 51f ;\
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;\
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;\
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PUTS (" - exception triggered: TRUE\n") ;\
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PUTS (" - exception triggered: TRUE\n") ;\
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l.j 52f ;\
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l.j 52f ;\
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l.nop ;\
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l.nop ;\
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;\
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;\
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51: PUTS (" - exception triggered: FALSE\n") ;\
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51: PUTS (" - exception triggered: FALSE\n") ;\
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52:
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52:
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Start of code
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* Start of code
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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.section .text
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.section .text
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.global _start
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.global _start
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_start:
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_start:
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Test of move from SPR, l.mfspr
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* Test of move from SPR, l.mfspr
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*
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*
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* MACLO (0x2801) is always used as the test register.
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* MACLO (0x2801) is always used as the test register.
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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_mfspr:
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_mfspr:
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LOAD_STR (r3, "l.mfspr\n")
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LOAD_STR (r3, "l.mfspr\n")
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l.jal _puts
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l.jal _puts
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l.nop
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l.nop
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/* Move a test value using zero in the register */
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/* Move a test value using zero in the register */
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TEST_MFSPR (0x00000000, 0x2801)
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TEST_MFSPR (0x00000000, 0x2801)
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/* Move a test value using zero as the constant */
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/* Move a test value using zero as the constant */
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TEST_MFSPR (0x00002801, 0x0000)
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TEST_MFSPR (0x00002801, 0x0000)
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/* Move a test value using non-zero in both register and constant.
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/* Move a test value using non-zero in both register and constant.
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Some of these values will not give the correct result if OR rather
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Some of these values will not give the correct result if OR rather
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than ADD is used to determine the SPR address */
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than ADD is used to determine the SPR address */
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TEST_MFSPR (0x00002801, 0x2801)
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TEST_MFSPR (0x00002801, 0x2801)
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TEST_MFSPR (0x00000801, 0x2000)
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TEST_MFSPR (0x00000801, 0x2000)
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TEST_MFSPR (0x00002000, 0x0801)
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TEST_MFSPR (0x00002000, 0x0801)
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TEST_MFSPR (0x00002801, 0x0001)
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TEST_MFSPR (0x00002801, 0x0001)
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TEST_MFSPR (0x00000800, 0x2801)
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TEST_MFSPR (0x00000800, 0x2801)
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* Test of move to SPR, l.mtspr
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* Test of move to SPR, l.mtspr
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*
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*
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* MACLO (0x2801) is always used as the test register.
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* MACLO (0x2801) is always used as the test register.
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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_mtspr:
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_mtspr:
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LOAD_STR (r3, "l.mtspr\n")
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LOAD_STR (r3, "l.mtspr\n")
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l.jal _puts
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l.jal _puts
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l.nop
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l.nop
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/* Move a test value using zero in the register */
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/* Move a test value using zero in the register */
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TEST_MTSPR (0x00000000, 0x2801)
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TEST_MTSPR (0x00000000, 0x2801)
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/* Move a test value using zero as the constant */
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/* Move a test value using zero as the constant */
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TEST_MTSPR (0x00002801, 0x0000)
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TEST_MTSPR (0x00002801, 0x0000)
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/* Move a test value using non-zero in both register and constant.
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/* Move a test value using non-zero in both register and constant.
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Some of these values will not give the correct result if OR rather
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Some of these values will not give the correct result if OR rather
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than ADD is used to determine the SPR address */
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than ADD is used to determine the SPR address */
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TEST_MTSPR (0x00002801, 0x2801)
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TEST_MTSPR (0x00002801, 0x2801)
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TEST_MTSPR (0x00000801, 0x2000)
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TEST_MTSPR (0x00000801, 0x2000)
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TEST_MTSPR (0x00002000, 0x0801)
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TEST_MTSPR (0x00002000, 0x0801)
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TEST_MTSPR (0x00002801, 0x0001)
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TEST_MTSPR (0x00002801, 0x0001)
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TEST_MTSPR (0x00000800, 0x2801)
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TEST_MTSPR (0x00000800, 0x2801)
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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* All done
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* All done
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* ------------------------------------------------------------------------- */
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* ------------------------------------------------------------------------- */
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_exit:
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_exit:
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LOAD_STR (r3, "Test completed\n")
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LOAD_STR (r3, "Test completed\n")
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l.jal _puts
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l.jal _puts
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l.nop
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l.nop
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TEST_EXIT
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TEST_EXIT
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