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Rev 19 |
Rev 128 |
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# very draft timing table for FPGA Virtex, sg -5
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# very draft timing table for FPGA Virtex, sg -5
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# size is in gates, delay in ns
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# size is in gates, delay in ns
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# instruction_name size_normal size_immediate delay_normal delay_immediate
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# instruction_name size_normal size_immediate delay_normal delay_immediate
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add 30. 15. 8. 4.
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add 30. 15. 8. 4.
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sub 30. 15. 8. 4.
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sub 30. 15. 8. 4.
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and 5. 0. 1. 0.
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and 5. 0. 1. 0.
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or 5. 0. 1. 0.
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or 5. 0. 1. 0.
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xor 10. 2. 1. 0.5
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xor 10. 2. 1. 0.5
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mul 700. 200. 12. 5.
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mul 700. 200. 12. 5.
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srl 100. 1. 24. 12.
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srl 100. 1. 24. 12.
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sll 100. 1. 24. 12.
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sll 100. 1. 24. 12.
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sra 100. 1. 24. 12.
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sra 100. 1. 24. 12.
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lb 50. 50. 5. 5.
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lb 50. 50. 5. 5.
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lh 50. 50. 5. 5.
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lh 50. 50. 5. 5.
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lw 50. 50. 5. 5.
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lw 50. 50. 5. 5.
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sb 50. 50. 5. 5.
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sb 50. 50. 5. 5.
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sh 50. 50. 5. 5.
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sh 50. 50. 5. 5.
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sw 50. 50. 5. 5.
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sw 50. 50. 5. 5.
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sfeq 20. 10. 5. 2.
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sfeq 20. 10. 5. 2.
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sfne 20. 10. 5. 2.
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sfne 20. 10. 5. 2.
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sfle 30. 10. 8. 4.
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sfle 30. 10. 8. 4.
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sflt 30. 10. 8. 4.
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sflt 30. 10. 8. 4.
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sfgt 30. 10. 8. 4.
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sfgt 30. 10. 8. 4.
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sfge 30. 10. 8. 4.
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sfge 30. 10. 8. 4.
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bf 50. 50. 1. 1.
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bf 50. 50. 1. 1.
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lrbb 60. 60. 1. 1.
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lrbb 60. 60. 1. 1.
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cmov 15. 15. 5. 2.
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cmov 15. 15. 5. 2.
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reg 60. 60. 1. 1.
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reg 60. 60. 1. 1.
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call 100. 100. 3. 3.
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call 100. 100. 3. 3.
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nop 0. 0. 0. 0.
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nop 0. 0. 0. 0.
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