# inst-set-test.exp. Tests of ORBIS32 instruction set
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# inst-set-test.exp. Tests of ORBIS32 instruction set
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# Copyright (C) 2010 Embecosm Limited
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# Copyright (C) 2010 Embecosm Limited
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# Contributor Jeremy Bennett
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# Contributor Jeremy Bennett
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# This file is part of OpenRISC 1000 Architectural Simulator.
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# This file is part of OpenRISC 1000 Architectural Simulator.
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# This program is free software; you can redistribute it and/or modify it
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 3 of the License, or (at your option)
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# Software Foundation; either version 3 of the License, or (at your option)
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# any later version.
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# any later version.
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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# more details.
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# You should have received a copy of the GNU General Public License along
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# You should have received a copy of the GNU General Public License along
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# with this program. If not, see . */
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# with this program. If not, see . */
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# -----------------------------------------------------------------------------
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# -----------------------------------------------------------------------------
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# This code is commented throughout for use with Doxygen.
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# This code is commented throughout for use with Doxygen.
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# -----------------------------------------------------------------------------
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# -----------------------------------------------------------------------------
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# Run the l.lws test
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# Run the l.lws test
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run_or1ksim "lws-test" \
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run_or1ksim "lws-test" \
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[list "!l.lws" \
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[list "!l.lws" \
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" l.lws r4,0(r5): r4=0xdeadbeef: OK" \
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" l.lws r4,0(r5): r4=0xdeadbeef: OK" \
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" l.lws r4,0(r5): r4=0x00000000: OK" \
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" l.lws r4,0(r5): r4=0x00000000: OK" \
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" l.lws r4,0(r5): r4=0x7fffffff: OK" \
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" l.lws r4,0(r5): r4=0x7fffffff: OK" \
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" l.lws r4,0(r5): r4=0x80000000: OK" \
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" l.lws r4,0(r5): r4=0x80000000: OK" \
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" l.lws r4,0(r5): r4=0xffffffff: OK" \
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" l.lws r4,0(r5): r4=0xffffffff: OK" \
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" l.lws r4,0(r5): r4=0x00000000: OK" \
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" l.lws r4,0(r5): r4=0x00000000: OK" \
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" l.lws r4,0(r5): r4=0x7fffffff: OK" \
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" l.lws r4,0(r5): r4=0x7fffffff: OK" \
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" l.lws r4,0(r5): r4=0x80000000: OK" \
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" l.lws r4,0(r5): r4=0x80000000: OK" \
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" l.lws r4,0(r5): r4=0xffffffff: OK" \
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" l.lws r4,0(r5): r4=0xffffffff: OK" \
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" l.lws r4,0(r5): r4=0xdeadbeef: OK" \
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" l.lws r4,0(r5): r4=0xdeadbeef: OK" \
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" l.lws r4,0(r5): r4=0x00000000: OK" \
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" l.lws r4,0(r5): r4=0x00000000: OK" \
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" l.lws r4,0(r5): r4=0x7fffffff: OK" \
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" l.lws r4,0(r5): r4=0x7fffffff: OK" \
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" l.lws r4,0(r5): r4=0x80000000: OK" \
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" l.lws r4,0(r5): r4=0x80000000: OK" \
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"!Test completed" \
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"!Test completed" \
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"!report(0xdeaddead);" \
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"!report(0xdeaddead);" \
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"!exit(0)"] \
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"!exit(0)"] \
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"inst-set-test.cfg" "inst-set-test/is-lws-test"
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"inst-set-test.cfg" "inst-set-test/is-lws-test"
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# Run the l.div and l.divu test
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run_or1ksim "lws-test" \
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[list "!l.div" \
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"! RANGE exception" \
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" - caused by: report(0xe0853309);" \
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"! - SR value: report(0x00008601);" \
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" 1 / 0 (with error) carry flag set: TRUE" \
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"!l.divu" \
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"! RANGE exception" \
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" - caused by: report(0xe085330a);" \
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"! - SR value: report(0x00008601);" \
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" 1 / 0 (with error) carry flag set: TRUE" \
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"!Test completed" \
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"!report(0xdeaddead);" \
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"!exit(0)"] \
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"inst-set-test.cfg" "inst-set-test/is-div-test"
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# Run the l.add, l.addc, l.addi and l.addic tests
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run_or1ksim "lws-test" \
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[list "!l.add" \
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" 0x00000001 + 0x00000002 = 0x00000003: OK" \
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" - carry flag set: FALSE" \
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" - overflow flag set: FALSE" \
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" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
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" - carry flag set: TRUE" \
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" - overflow flag set: FALSE" \
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" 0x40000000 + 0x3fffffff = 0x7fffffff: OK" \
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" - carry flag set: FALSE" \
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" - overflow flag set: FALSE" \
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" 0x40000000 + 0x40000000 = 0x80000000: OK" \
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" - carry flag set: FALSE" \
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" - overflow flag set: TRUE" \
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" 0xc0000000 + 0xc0000000 = 0x80000000: OK" \
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" - carry flag set: TRUE" \
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" - overflow flag set: FALSE" \
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" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
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" - carry flag set: TRUE" \
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" - overflow flag set: TRUE" \
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"! OVE flag set" \
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" RANGE exception" \
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" - caused by: report(0xe0853000);" \
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" - SR value: report(0x00009a01);" \
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" 0x40000000 + 0x40000000 = 0x80000000: OK" \
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" - carry flag set: FALSE" \
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" - overflow flag set: TRUE" \
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" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
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" - carry flag set: TRUE" \
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" - overflow flag set: FALSE" \
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" RANGE exception" \
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" - caused by: report(0xe0853000);" \
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" - SR value: report(0x00009e01);" \
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" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
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" - carry flag set: TRUE" \
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" - overflow flag set: TRUE" \
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"! OVE flag cleared" \
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"!Test completed" \
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"!report(0xdeaddead);" \
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"!exit(0)"] \
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"inst-set-test.cfg" "inst-set-test/is-add-test"
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