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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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| Rev 353 |
Rev 467 |
MEMORY
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MEMORY
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{
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{
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flash : ORIGIN = 0xf0000000, LENGTH = 0x04000000
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flash : ORIGIN = 0xf0000000, LENGTH = 0x04000000
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vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
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vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
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ram : ORIGIN = 0x00002000, LENGTH = 0x04000000 - 0x00002000
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ram : ORIGIN = 0x00002000, LENGTH = 0x04000000 - 0x00002000
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}
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}
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SECTIONS
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SECTIONS
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{
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{
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.reset :
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.reset :
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{
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{
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*(.crc)
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*(.crc)
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*(.reset)
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*(.reset)
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} > flash
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} > flash
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.text ALIGN(0x04):
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.text ALIGN(0x04):
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{
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{
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*(.text)
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*(.text)
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} > flash
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} > flash
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.rodata :
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.rodata :
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{
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{
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*(.rodata)
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*(.rodata)
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*(.rodata.*)
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*(.rodata.*)
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} > flash
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} > flash
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.monitor ALIGN(0x40000) :
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.monitor ALIGN(0x40000) :
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{
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{
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*(.monitor)
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*(.monitor)
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} > flash
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} > flash
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. += 0x100000;
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. += 0x100000;
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.config ALIGN(0x40000) :
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.config ALIGN(0x40000) :
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{
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{
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_config_end = .;
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_config_end = .;
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*(.config)
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*(.config)
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} > flash
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} > flash
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.dummy ALIGN(0x40000):
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.dummy ALIGN(0x40000):
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{
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{
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_src_beg = .;
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_src_beg = .;
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} > flash
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} > flash
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.vectors :
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.vectors :
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AT ( ADDR (.dummy) )
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AT ( ADDR (.dummy) )
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{
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{
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_vec_start = .;
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_vec_start = .;
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*(.vectors)
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*(.vectors)
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_vec_end = .;
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_vec_end = .;
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} > vectors
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} > vectors
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.data :
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.data :
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AT ( ADDR (.dummy) + SIZEOF (.vectors) )
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AT ( ADDR (.dummy) + SIZEOF (.vectors) )
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{
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{
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_dst_beg = .;
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_dst_beg = .;
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*(.data)
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*(.data)
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_dst_end = .;
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_dst_end = .;
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} > ram
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} > ram
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.bss :
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.bss :
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{
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{
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*(.bss)
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*(.bss)
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} > ram
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} > ram
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.stack :
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.stack :
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{
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{
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*(.stack)
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*(.stack)
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_stack_top = .;
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} > ram
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} > ram
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.mytext :
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.mytext :
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{
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{
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_fprog_addr = .;
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_fprog_addr = .;
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*(.mytext)
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*(.mytext)
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. += 0x500;
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. += 0x500;
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_src_addr = .;
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_src_addr = .;
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} > ram
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} > ram
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}
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}
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