#ifndef _MC_INIT_2_H_
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#ifndef _MC_INIT_2_H_
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#define _MC_INIT_2_H_
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#define _MC_INIT_2_H_
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/* clock period in [ns] */
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/* clock period in [ns] */
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#define SYS_CLK_PERIOD (1000000000/IN_CLK)
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#define SYS_CLK_PERIOD (1000000000/IN_CLK)
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/* FLASH timings: worst cases in ns, from data sheets */
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/* FLASH timings: worst cases in ns, from data sheets */
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# define FLASH_WA_TIME 150 /* write access*/
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# define FLASH_WA_TIME 150 /* write access*/
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# define FLASH_WE_DELAY 30 /* write enable*/
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# define FLASH_WE_DELAY 30 /* write enable*/
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# define FLASH_WH_TIME 0 /* write hold */
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# define FLASH_WH_TIME 0 /* write hold */
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# define FLASH_RA_TIME 150 /* read access*/
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# define FLASH_RA_TIME 150 /* read access*/
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# define FLASH_PRA_TIME 25 /* page read access time */
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# define FLASH_PRA_TIME 25 /* page read access time */
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# define FLASH_RT_TIME 35 /* read turnaround time */
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# define FLASH_RT_TIME 35 /* read turnaround time */
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/* SDRAM timings: worst cases in ns, from data sheets */
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/* SDRAM timings: worst cases in ns, from data sheets */
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# define SDRAM_tRCD 23
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# define SDRAM_tRCD 23
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# define SDRAM_tWR 20
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# define SDRAM_tWR 20
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# define SDRAM_tRC 60
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# define SDRAM_tRC 60
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# define SDRAM_tRFC 60 /* sometimes the same as tRC */
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# define SDRAM_tRFC 60 /* sometimes the same as tRC */
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# define SDRAM_tRAS 50 /* use the worst case minimal value */
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# define SDRAM_tRAS 50 /* use the worst case minimal value */
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# define SDRAM_tRP 23
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# define SDRAM_tRP 23
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# define SDRAM_tRRD 15
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# define SDRAM_tRRD 15
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# define SDRAM_tREF ((64000000/8192)+1)
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# define SDRAM_tREF ((64000000/8192)+1)
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# define FLASH_BAR_VAL FLASH_BASE_ADDR
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# define FLASH_BAR_VAL FLASH_BASE_ADDR
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# define FLASH_AMR_VAL (~(FLASH_SIZE-1)) /* address mask register */
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# define FLASH_AMR_VAL (~(FLASH_SIZE-1)) /* address mask register */
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# define SDRAM_BASE_ADDR 0x00000000
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# define SDRAM_BASE_ADDR 0x00000000
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# define SDRAM_SIZE 0x02000000
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# define SDRAM_SIZE 0x02000000
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# define SDRAM_BAR_VAL SDRAM_BASE_ADDR
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# define SDRAM_BAR_VAL SDRAM_BASE_ADDR
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# define SDRAM_AMR_VAL (~(SDRAM_SIZE-1))
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# define SDRAM_AMR_VAL (~(SDRAM_SIZE-1))
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/* independant from flash properties, always 0 ;) */
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/* independant from flash properties, always 0 ;) */
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# define FLASH_OE_DELAY 0 /* output enable */
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# define FLASH_OE_DELAY 0 /* output enable */
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# define FLASH_OE_VAL ((FLASH_OE_DELAY+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)
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# define FLASH_OE_VAL ((FLASH_OE_DELAY+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)
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// define FLASH_WTR_VAL 0x00011009 /* write timings */
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// define FLASH_WTR_VAL 0x00011009 /* write timings */
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# define FLASH_WTR_VAL ((0x000003ff & ((FLASH_WA_TIME-1) /SYS_CLK_PERIOD)) | \
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# define FLASH_WTR_VAL ((0x000003ff & ((FLASH_WA_TIME-1) /SYS_CLK_PERIOD)) | \
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(0x0000f000 & ((FLASH_WE_DELAY-1)/SYS_CLK_PERIOD)) | \
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(0x0000f000 & ((FLASH_WE_DELAY-1)/SYS_CLK_PERIOD)) | \
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(0x001f0000 & ((FLASH_WH_TIME) /SYS_CLK_PERIOD)))
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(0x001f0000 & ((FLASH_WH_TIME) /SYS_CLK_PERIOD)))
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// define FLASH_RTR_VAL 0x01002009 /* read timings */
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// define FLASH_RTR_VAL 0x01002009 /* read timings */
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# define FLASH_RTR_VAL ((0x000003ff & ((FLASH_RA_TIME-1) /SYS_CLK_PERIOD)) | \
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# define FLASH_RTR_VAL ((0x000003ff & ((FLASH_RA_TIME-1) /SYS_CLK_PERIOD)) | \
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(0x0000f000 & (FLASH_OE_VAL )) | \
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(0x0000f000 & (FLASH_OE_VAL )) | \
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(0x001f0000 & ((FLASH_PRA_TIME-1)/SYS_CLK_PERIOD)) | \
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(0x001f0000 & ((FLASH_PRA_TIME-1)/SYS_CLK_PERIOD)) | \
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(0x1f000000 & ((FLASH_RT_TIME-1 /SYS_CLK_PERIOD))))
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(0x1f000000 & ((FLASH_RT_TIME-1 /SYS_CLK_PERIOD))))
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/* round this value down:
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/* round this value down:
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* if it's 30 / 10 -> we want 2, so it's ok, 31 / 10 -> we want 3
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* if it's 30 / 10 -> we want 2, so it's ok, 31 / 10 -> we want 3
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*
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*
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* define SDRAM_RCDR_VAL 0x00000002
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* define SDRAM_RCDR_VAL 0x00000002
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*/
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*/
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# define SDRAM_RCDR_VAL ((SDRAM_tRCD-1)/SYS_CLK_PERIOD)
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# define SDRAM_RCDR_VAL ((SDRAM_tRCD-1)/SYS_CLK_PERIOD)
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// prviously undefined
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// prviously undefined
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# define SDRAM_WRTR_VAL ((SDRAM_tWR+(SYS_CLK_PERIOD-1)/SYS_CLK_PERIOD)-2)
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# define SDRAM_WRTR_VAL ((SDRAM_tWR+(SYS_CLK_PERIOD-1)/SYS_CLK_PERIOD)-2)
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# if SDRAM_WRTR_VAL<0
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# if SDRAM_WRTR_VAL<0
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# undef SDRAM_WRTR_VAL
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# undef SDRAM_WRTR_VAL
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# define SDRAM_WRTR_VAL 0
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# define SDRAM_WRTR_VAL 0
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# endif
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# endif
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// define SDRAM_RCTR_VAL 0x00000006
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// define SDRAM_RCTR_VAL 0x00000006
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# define SDRAM_RCTR_VAL ((SDRAM_tRC+(SYS_CLK_PERIOD-1)/SYS_CLK_PERIOD)-2)
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# define SDRAM_RCTR_VAL ((SDRAM_tRC+(SYS_CLK_PERIOD-1)/SYS_CLK_PERIOD)-2)
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# if SDRAM_RCTR_VAL<0
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# if SDRAM_RCTR_VAL<0
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# undef SDRAM_RCTR_VAL
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# undef SDRAM_RCTR_VAL
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# define SDRAM_RCTR_VAL 0
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# define SDRAM_RCTR_VAL 0
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# endif
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# endif
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// define SDRAM_REFCTR_VAL 0x00000006
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// define SDRAM_REFCTR_VAL 0x00000006
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# define SDRAM_REFCTR_VAL ((SDRAM_tRFC+(SYS_CLK_PERIOD-1)/SYS_CLK_PERIOD)-2)
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# define SDRAM_REFCTR_VAL ((SDRAM_tRFC+(SYS_CLK_PERIOD-1)/SYS_CLK_PERIOD)-2)
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# if SDRAM_REFCTR_VAL<0
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# if SDRAM_REFCTR_VAL<0
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# undef SDRAM_REFCTR_VAL
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# undef SDRAM_REFCTR_VAL
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# define SDRAM_REFCTR_VAL 0
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# define SDRAM_REFCTR_VAL 0
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# endif
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# endif
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// define SDRAM_RATR_VAL 0x00000006
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// define SDRAM_RATR_VAL 0x00000006
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# define SDRAM_RATR_VAL ((SDRAM_tRAS+(SYS_CLK_PERIOD-1)/SYS_CLK_PERIOD)-2)
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# define SDRAM_RATR_VAL ((SDRAM_tRAS+(SYS_CLK_PERIOD-1)/SYS_CLK_PERIOD)-2)
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# if SDRAM_RATR_VAL<0
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# if SDRAM_RATR_VAL<0
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# undef SDRAM_RATR_VAL
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# undef SDRAM_RATR_VAL
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# define SDRAM_RATR_VAL 0
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# define SDRAM_RATR_VAL 0
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# endif
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# endif
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// define SDRAM_PTR_VAL 0x00000001
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// define SDRAM_PTR_VAL 0x00000001
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# define SDRAM_PTR_VAL (((SDRAM_tRP+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-2)
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# define SDRAM_PTR_VAL (((SDRAM_tRP+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-2)
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# if SDRAM_PTR_VAL<0
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# if SDRAM_PTR_VAL<0
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# undef SDRAM_PTR_VAL
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# undef SDRAM_PTR_VAL
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# define SDRAM_PTR_VAL 0
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# define SDRAM_PTR_VAL 0
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# endif
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# endif
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// define SDRAM_RRDR_VAL 0x00000000
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// define SDRAM_RRDR_VAL 0x00000000
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# define SDRAM_RRDR_VAL (((SDRAM_tRRD+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-2)
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# define SDRAM_RRDR_VAL (((SDRAM_tRRD+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-2)
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# if SDRAM_RRDR_VAL<0
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# if SDRAM_RRDR_VAL<0
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# undef SDRAM_RRDR_VAL
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# undef SDRAM_RRDR_VAL
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# define SDRAM_RRDR_VAL 0
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# define SDRAM_RRDR_VAL 0
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# endif
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# endif
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/*
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/*
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* we don't want to go to the edge with refresh delays
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* we don't want to go to the edge with refresh delays
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* define SDRAM_RIR_VAL 0x00000300
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* define SDRAM_RIR_VAL 0x00000300
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*/
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*/
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# define SDRAM_RIR_VAL ((SDRAM_tREF/SYS_CLK_PERIOD)-((SDRAM_tREF/SYS_CLK_PERIOD)+10)/10)
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# define SDRAM_RIR_VAL ((SDRAM_tREF/SYS_CLK_PERIOD)-((SDRAM_tREF/SYS_CLK_PERIOD)+10)/10)
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# define MC_BAR_0 (0x00)
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# define MC_BAR_0 (0x00)
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# define MC_AMR_0 (0x04)
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# define MC_AMR_0 (0x04)
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# define MC_BAR_1 (0x08)
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# define MC_BAR_1 (0x08)
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# define MC_AMR_1 (0x0c)
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# define MC_AMR_1 (0x0c)
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# define MC_BAR_2 (0x10)
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# define MC_BAR_2 (0x10)
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# define MC_AMR_2 (0x14)
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# define MC_AMR_2 (0x14)
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# define MC_BAR_3 (0x18)
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# define MC_BAR_3 (0x18)
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# define MC_AMR_3 (0x1c)
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# define MC_AMR_3 (0x1c)
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# define MC_CCR_0 (0x20)
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# define MC_CCR_0 (0x20)
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# define MC_CCR_1 (0x24)
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# define MC_CCR_1 (0x24)
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# define MC_CCR_2 (0x28)
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# define MC_CCR_2 (0x28)
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# define MC_CCR_3 (0x2c)
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# define MC_CCR_3 (0x2c)
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# define MC_WTR_0 (0x30)
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# define MC_WTR_0 (0x30)
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# define MC_RTR_0 (0x34)
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# define MC_RTR_0 (0x34)
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# define MC_WTR_1 (0x38)
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# define MC_WTR_1 (0x38)
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# define MC_RTR_1 (0x3c)
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# define MC_RTR_1 (0x3c)
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# define MC_WTR_2 (0x40)
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# define MC_WTR_2 (0x40)
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# define MC_RTR_2 (0x44)
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# define MC_RTR_2 (0x44)
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# define MC_WTR_3 (0x48)
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# define MC_WTR_3 (0x48)
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# define MC_RTR_3 (0x4c)
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# define MC_RTR_3 (0x4c)
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# define MC_BAR_4 (0x80)
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# define MC_BAR_4 (0x80)
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# define MC_AMR_4 (0x84)
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# define MC_AMR_4 (0x84)
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# define MC_BAR_5 (0x88)
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# define MC_BAR_5 (0x88)
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# define MC_AMR_5 (0x8c)
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# define MC_AMR_5 (0x8c)
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# define MC_BAR_6 (0x90)
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# define MC_BAR_6 (0x90)
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# define MC_AMR_6 (0x94)
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# define MC_AMR_6 (0x94)
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# define MC_BAR_7 (0x98)
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# define MC_BAR_7 (0x98)
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# define MC_AMR_7 (0x9c)
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# define MC_AMR_7 (0x9c)
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# define MC_CCR_4 (0xa0)
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# define MC_CCR_4 (0xa0)
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# define MC_CCR_5 (0xa4)
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# define MC_CCR_5 (0xa4)
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# define MC_CCR_6 (0xa8)
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# define MC_CCR_6 (0xa8)
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# define MC_CCR_7 (0xac)
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# define MC_CCR_7 (0xac)
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# define MC_RATR (0xb0) /* row active time register */
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# define MC_RATR (0xb0) /* row active time register */
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# define MC_RCTR (0xb4)
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# define MC_RCTR (0xb4)
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# define MC_RRDR (0xb8)
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# define MC_RRDR (0xb8)
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# define MC_PTR (0xbc)
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# define MC_PTR (0xbc)
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# define MC_WRTR (0xc0)
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# define MC_WRTR (0xc0)
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# define MC_REFCTR (0xc4)
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# define MC_REFCTR (0xc4)
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# define MC_RCDR (0xc8)
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# define MC_RCDR (0xc8)
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# define MC_RIR (0xcc)
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# define MC_RIR (0xcc)
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# define MC_SMBOR (0xe0)
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# define MC_SMBOR (0xe0)
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# define MC_ORR (0xe4)
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# define MC_ORR (0xe4)
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# define MC_OSR (0xe8)
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# define MC_OSR (0xe8)
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# define MC_PCR (0xec)
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# define MC_PCR (0xec)
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# define MC_IIR (0xf0)
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# define MC_IIR (0xf0)
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/* POC register field definition */
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/* POC register field definition */
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# define MC_POC_EN_BW_OFFSET 0
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# define MC_POC_EN_BW_OFFSET 0
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# define MC_POC_EN_BW_WIDTH 2
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# define MC_POC_EN_BW_WIDTH 2
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# define MC_POC_EN_MEMTYPE_OFFSET 2
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# define MC_POC_EN_MEMTYPE_OFFSET 2
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# define MC_POC_EN_MEMTYPE_WIDTH 2
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# define MC_POC_EN_MEMTYPE_WIDTH 2
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/* CSC register field definition */
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/* CSC register field definition */
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# define MC_CSC_EN_OFFSET 0
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# define MC_CSC_EN_OFFSET 0
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# define MC_CSC_MEMTYPE_OFFSET 1
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# define MC_CSC_MEMTYPE_OFFSET 1
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# define MC_CSC_MEMTYPE_WIDTH 2
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# define MC_CSC_MEMTYPE_WIDTH 2
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# define MC_CSC_BW_OFFSET 4
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# define MC_CSC_BW_OFFSET 4
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# define MC_CSC_BW_WIDTH 2
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# define MC_CSC_BW_WIDTH 2
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# define MC_CSC_MS_OFFSET 6
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# define MC_CSC_MS_OFFSET 6
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# define MC_CSC_MS_WIDTH 2
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# define MC_CSC_MS_WIDTH 2
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# define MC_CSC_WP_OFFSET 8
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# define MC_CSC_WP_OFFSET 8
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# define MC_CSC_BAS_OFFSET 9
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# define MC_CSC_BAS_OFFSET 9
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# define MC_CSC_KRO_OFFSET 10
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# define MC_CSC_KRO_OFFSET 10
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# define MC_CSC_PEN_OFFSET 11
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# define MC_CSC_PEN_OFFSET 11
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# define MC_CSC_SEL_OFFSET 16
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# define MC_CSC_SEL_OFFSET 16
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# define MC_CSC_SEL_WIDTH 8
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# define MC_CSC_SEL_WIDTH 8
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# define MC_CSC_MEMTYPE_SDRAM 0
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# define MC_CSC_MEMTYPE_SDRAM 0
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# define MC_CSC_MEMTYPE_SSRAM 1
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# define MC_CSC_MEMTYPE_SSRAM 1
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# define MC_CSC_MEMTYPE_ASYNC 2
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# define MC_CSC_MEMTYPE_ASYNC 2
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# define MC_CSC_MEMTYPE_SYNC 3
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# define MC_CSC_MEMTYPE_SYNC 3
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# define MC_CSR_VALID 0xFF000703LU
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# define MC_CSR_VALID 0xFF000703LU
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# define MC_POC_VALID 0x0000000FLU
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# define MC_POC_VALID 0x0000000FLU
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# define MC_BA_MASK_VALID 0x000003FFLU
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# define MC_BA_MASK_VALID 0x000003FFLU
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# define MC_CSC_VALID 0x00FF0FFFLU
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# define MC_CSC_VALID 0x00FF0FFFLU
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# define MC_TMS_SDRAM_VALID 0x0FFF83FFLU
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# define MC_TMS_SDRAM_VALID 0x0FFF83FFLU
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# define MC_TMS_SSRAM_VALID 0x00000000LU
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# define MC_TMS_SSRAM_VALID 0x00000000LU
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# define MC_TMS_ASYNC_VALID 0x03FFFFFFLU
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# define MC_TMS_ASYNC_VALID 0x03FFFFFFLU
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# define MC_TMS_SYNC_VALID 0x01FFFFFFLU
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# define MC_TMS_SYNC_VALID 0x01FFFFFFLU
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# define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */
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# define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */
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/* TMS register field definition SDRAM */
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/* TMS register field definition SDRAM */
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# define MC_TMS_SDRAM_TRFC_OFFSET 24
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# define MC_TMS_SDRAM_TRFC_OFFSET 24
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# define MC_TMS_SDRAM_TRFC_WIDTH 4
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# define MC_TMS_SDRAM_TRFC_WIDTH 4
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# define MC_TMS_SDRAM_TRP_OFFSET 20
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# define MC_TMS_SDRAM_TRP_OFFSET 20
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# define MC_TMS_SDRAM_TRP_WIDTH 4
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# define MC_TMS_SDRAM_TRP_WIDTH 4
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# define MC_TMS_SDRAM_TRCD_OFFSET 17
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# define MC_TMS_SDRAM_TRCD_OFFSET 17
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# define MC_TMS_SDRAM_TRCD_WIDTH 4
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# define MC_TMS_SDRAM_TRCD_WIDTH 4
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# define MC_TMS_SDRAM_TWR_OFFSET 15
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# define MC_TMS_SDRAM_TWR_OFFSET 15
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# define MC_TMS_SDRAM_TWR_WIDTH 2
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# define MC_TMS_SDRAM_TWR_WIDTH 2
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# define MC_TMS_SDRAM_WBL_OFFSET 9
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# define MC_TMS_SDRAM_WBL_OFFSET 9
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# define MC_TMS_SDRAM_OM_OFFSET 7
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# define MC_TMS_SDRAM_OM_OFFSET 7
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# define MC_TMS_SDRAM_OM_WIDTH 2
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# define MC_TMS_SDRAM_OM_WIDTH 2
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# define MC_TMS_SDRAM_CL_OFFSET 4
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# define MC_TMS_SDRAM_CL_OFFSET 4
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# define MC_TMS_SDRAM_CL_WIDTH 3
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# define MC_TMS_SDRAM_CL_WIDTH 3
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# define MC_TMS_SDRAM_BT_OFFSET 3
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# define MC_TMS_SDRAM_BT_OFFSET 3
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# define MC_TMS_SDRAM_BL_OFFSET 0
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# define MC_TMS_SDRAM_BL_OFFSET 0
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# define MC_TMS_SDRAM_BL_WIDTH 3
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# define MC_TMS_SDRAM_BL_WIDTH 3
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/* TMS register field definition ASYNC */
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/* TMS register field definition ASYNC */
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# define MC_TMS_ASYNC_TWWD_OFFSET 20
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# define MC_TMS_ASYNC_TWWD_OFFSET 20
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# define MC_TMS_ASYNC_TWWD_WIDTH 6
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# define MC_TMS_ASYNC_TWWD_WIDTH 6
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# define MC_TMS_ASYNC_TWD_OFFSET 16
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# define MC_TMS_ASYNC_TWD_OFFSET 16
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# define MC_TMS_ASYNC_TWD_WIDTH 4
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# define MC_TMS_ASYNC_TWD_WIDTH 4
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# define MC_TMS_ASYNC_TWPW_OFFSET 12
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# define MC_TMS_ASYNC_TWPW_OFFSET 12
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# define MC_TMS_ASYNC_TWPW_WIDTH 4
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# define MC_TMS_ASYNC_TWPW_WIDTH 4
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# define MC_TMS_ASYNC_TRDZ_OFFSET 8
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# define MC_TMS_ASYNC_TRDZ_OFFSET 8
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# define MC_TMS_ASYNC_TRDZ_WIDTH 4
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# define MC_TMS_ASYNC_TRDZ_WIDTH 4
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# define MC_TMS_ASYNC_TRDV_OFFSET 0
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# define MC_TMS_ASYNC_TRDV_OFFSET 0
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# define MC_TMS_ASYNC_TRDV_WIDTH 8
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# define MC_TMS_ASYNC_TRDV_WIDTH 8
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/* TMS register field definition SYNC */
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/* TMS register field definition SYNC */
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# define MC_TMS_SYNC_TTO_OFFSET 16
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# define MC_TMS_SYNC_TTO_OFFSET 16
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# define MC_TMS_SYNC_TTO_WIDTH 9
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# define MC_TMS_SYNC_TTO_WIDTH 9
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# define MC_TMS_SYNC_TWR_OFFSET 12
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# define MC_TMS_SYNC_TWR_OFFSET 12
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# define MC_TMS_SYNC_TWR_WIDTH 4
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# define MC_TMS_SYNC_TWR_WIDTH 4
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# define MC_TMS_SYNC_TRDZ_OFFSET 8
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# define MC_TMS_SYNC_TRDZ_OFFSET 8
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# define MC_TMS_SYNC_TRDZ_WIDTH 4
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# define MC_TMS_SYNC_TRDZ_WIDTH 4
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# define MC_TMS_SYNC_TRDV_OFFSET 0
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# define MC_TMS_SYNC_TRDV_OFFSET 0
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# define MC_TMS_SYNC_TRDV_WIDTH 8
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# define MC_TMS_SYNC_TRDV_WIDTH 8
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#endif /* _MC_INIT_2_H_ */
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#endif /* _MC_INIT_2_H_ */
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