#include "spr-defs.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "board.h"
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#define TRAP_ON_ERROR 0
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#define TRAP_ON_ERROR 0
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#define LOOP_ON_ERROR 0
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#define LOOP_ON_ERROR 0
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#define EXIT_NOP_ON_ERROR 1
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#define EXIT_NOP_ON_ERROR 1
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#define PRINT_AND_RESET_ON_ERROR 1
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#define PRINT_AND_RESET_ON_ERROR 1
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.extern _src_beg
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.extern _dst_beg
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.extern _dst_end
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.extern int_main
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.extern int_main
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.extern int_error
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.extern int_error
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.extern tick_interrupt
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.extern _crc32
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.extern _bstart
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.extern _bstart
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.extern _bend
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.extern _bend
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.global _calc_mycrc32
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.global _mycrc32
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.global _mysize
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.section .stack, "aw", @nobits
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.section .stack, "aw", @nobits
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.space STACK_SIZE
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.space STACK_SIZE
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_stack:
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_stack:
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.section .crc
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_mycrc32:
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.word 0xcccccccc
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_mysize:
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.word 0xdddddddd
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.if SELF_CHECK
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_calc_mycrc32:
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l.addi r3,r0,0
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l.movhi r4,hi(_calc_mycrc32)
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l.ori r4,r4,lo(_calc_mycrc32)
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l.movhi r5,hi(_mysize)
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l.ori r5,r5,lo(_mysize)
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l.lwz r5,0(r5)
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l.addi r1,r1,-4
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l.sw 0(r1),r9
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/* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
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l.jal _crc32
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l.nop
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l.movhi r3,hi(_mycrc32)
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l.ori r3,r3,lo(_mycrc32)
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l.lwz r3,0(r3)
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l.xor r11,r3,r11
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l.lwz r9,0(r1)
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l.jr r9
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l.addi r1,r1,4
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.endif
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.org 0x100
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.section .vectors, "ax"
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.section .vectors, "ax"
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.org 0x100
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_reset:
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_reset:
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l.movhi r0, 0
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l.movhi r0, 0
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/* Clear status register, set supervisor mode */
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/* Clear status register, set supervisor mode */
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l.ori r1, r0, SPR_SR_SM
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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l.mtspr r0, r0, SPR_TTMR
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/* Jump to start routine */
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/* Jump to start routine */
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l.movhi r3,hi(_start)
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l.movhi r3,hi(_start)
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l.ori r3,r3,lo(_start)
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l.ori r3,r3,lo(_start)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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.org (0x200 - 0x100 + _reset)
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.org (0x200 - 0x100 + _reset)
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_buserr:
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_buserr:
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.if TRAP_ON_ERROR
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.if TRAP_ON_ERROR
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/* Just trap */
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/* Just trap */
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l.trap 0
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l.trap 0
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.endif
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.endif
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.if EXIT_NOP_ON_ERROR
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.if EXIT_NOP_ON_ERROR
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l.nop 0x1
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l.nop 0x1
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.endif
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.endif
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.if LOOP_ON_ERROR
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.if LOOP_ON_ERROR
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l.j 0
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l.j 0
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l.nop
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l.nop
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.endif
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.endif
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.if PRINT_AND_RESET_ON_ERROR
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.if PRINT_AND_RESET_ON_ERROR
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l.mfspr r4, r0, SPR_EPCR_BASE
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l.mfspr r4, r0, SPR_EPCR_BASE
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l.j _int_error /* This will reset */
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l.j _int_error /* This will reset */
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l.ori r3, r0, 0x2
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l.ori r3, r0, 0x2
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.endif
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.endif
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.org (0x500 - 0x100 + _reset)
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.org (0x500 - 0x100 + _reset)
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_tickint:
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_tickint:
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#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
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#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
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/* Simply load timer_ticks variable and increment */
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/* Simply load timer_ticks variable and increment */
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.extern _timer_ticks
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.extern _timer_ticks
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l.addi r1, r1, -136 /* 128 + what we need (8),avoid area used by gcc*/
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l.addi r1, r1, -136 /* 128 + what we need (8),avoid area used by gcc*/
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l.sw 0(r1), r25
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l.sw 0(r1), r25
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l.sw 4(r1), r26
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l.sw 4(r1), r26
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l.movhi r25, hi(timestamp)
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l.movhi r25, hi(timestamp)
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l.ori r25, r25, lo(timestamp)
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l.ori r25, r25, lo(timestamp)
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l.lwz r26, 0(r25) /* Load variable addr.*/
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l.lwz r26, 0(r25) /* Load variable addr.*/
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l.addi r26, r26, 1 /* Increment variable */
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l.addi r26, r26, 1 /* Increment variable */
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l.sw 0(r25), r26 /* Store variable */
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l.sw 0(r25), r26 /* Store variable */
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l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */
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l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */
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l.ori r25, r25, lo(TIMER_RELOAD_VALUE)
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l.ori r25, r25, lo(TIMER_RELOAD_VALUE)
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l.mtspr r0, r25, SPR_TTMR /* Reset timer */
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l.mtspr r0, r25, SPR_TTMR /* Reset timer */
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l.lwz r25, 0(r1)
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l.lwz r25, 0(r1)
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l.lwz r26, 4(r1)
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l.lwz r26, 4(r1)
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l.addi r1, r1, 136
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l.addi r1, r1, 136
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l.rfe
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l.rfe
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.org (0x600 - 0x100 + _reset)
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.org (0x600 - 0x100 + _reset)
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_alignerr:
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_alignerr:
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.if TRAP_ON_ERROR
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.if TRAP_ON_ERROR
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/* Just trap */
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/* Just trap */
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l.trap 0
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l.trap 0
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.endif
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.endif
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.if EXIT_NOP_ON_ERROR
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.if EXIT_NOP_ON_ERROR
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l.nop 0x1
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l.nop 0x1
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.endif
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.endif
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.if LOOP_ON_ERROR
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.if LOOP_ON_ERROR
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l.j 0
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l.j 0
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l.nop
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l.nop
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.endif
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.endif
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.if PRINT_AND_RESET_ON_ERROR
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.if PRINT_AND_RESET_ON_ERROR
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l.mfspr r4, r0, SPR_EPCR_BASE
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l.mfspr r4, r0, SPR_EPCR_BASE
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l.j _int_error /* This will reset */
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l.j _int_error /* This will reset */
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l.ori r3, r0, 0x6
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l.ori r3, r0, 0x6
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.endif
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.endif
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.org (0x700 - 0x100 + _reset)
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.org (0x700 - 0x100 + _reset)
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_illinsn:
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_illinsn:
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.if TRAP_ON_ERROR
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.if TRAP_ON_ERROR
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/* Just trap */
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/* Just trap */
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l.trap 0
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l.trap 0
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.endif
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.endif
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.if EXIT_NOP_ON_ERROR
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.if EXIT_NOP_ON_ERROR
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l.nop 0x1
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l.nop 0x1
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.endif
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.endif
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.if LOOP_ON_ERROR
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.if LOOP_ON_ERROR
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l.j 0
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l.j 0
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l.nop
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l.nop
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.endif
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.endif
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.if PRINT_AND_RESET_ON_ERROR
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.if PRINT_AND_RESET_ON_ERROR
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l.mfspr r4, r0, SPR_EPCR_BASE
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l.mfspr r4, r0, SPR_EPCR_BASE
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l.j _int_error /* This will reset */
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l.j _int_error /* This will reset */
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l.ori r3, r0, 0x7
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l.ori r3, r0, 0x7
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.endif
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.endif
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.org (0x800 - 0x100 + _reset)
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.org (0x800 - 0x100 + _reset)
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_userint:
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_userint:
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l.addi r1,r1,-256 /*(128 + 128) */
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l.addi r1,r1,-256 /*(128 + 128) */
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l.sw 0x0(r1),r2
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l.sw 0x0(r1),r2
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l.addi r2, r1, 256
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l.addi r2, r1, 256
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l.sw 0x4(r1), r3
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l.sw 0x4(r1), r3
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l.movhi r3,hi(_int_wrapper)
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l.movhi r3,hi(_int_wrapper)
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l.ori r3,r3,lo(_int_wrapper)
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l.ori r3,r3,lo(_int_wrapper)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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.section .text
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.section .text
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_start:
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_start:
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/* Instruction cache enable */
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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/* Check if IC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_ICP
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l.andi r26,r24,SPR_UPR_ICP
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l.sfeq r26,r0
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l.sfeq r26,r0
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l.bf .L8
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l.bf .L8
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l.nop
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l.nop
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/* Disable IC */
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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/* Establish cache block size
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If BS=0, 16;
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If BS=0, 16;
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If BS=1, 32;
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If BS=1, 32;
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r14 contain block size
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r14 contain block size
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*/
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*/
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l.mfspr r24,r0,SPR_ICCFGR
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l.mfspr r24,r0,SPR_ICCFGR
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.srli r28,r26,7
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.ori r30,r0,16
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l.sll r14,r30,r28
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l.sll r14,r30,r28
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/* Establish number of cache sets
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/* Establish number of cache sets
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r16 contains number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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r28 contains log(# of cache sets)
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*/
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*/
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.srli r28,r26,3
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.ori r30,r0,1
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l.sll r16,r30,r28
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l.sll r16,r30,r28
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/* Invalidate IC */
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/* Invalidate IC */
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l.addi r6,r0,0
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l.addi r6,r0,0
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l.sll r5,r14,r28
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l.sll r5,r14,r28
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.L7:
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.L7:
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l.mtspr r0,r6,SPR_ICBIR
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l.mtspr r0,r6,SPR_ICBIR
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l.sfne r6,r5
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l.sfne r6,r5
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l.bf .L7
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l.bf .L7
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l.add r6,r6,r14
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l.add r6,r6,r14
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/* Enable IC */
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/* Enable IC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_ICE
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l.ori r6,r6,SPR_SR_ICE
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l.mtspr r0,r6,SPR_SR
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l.mtspr r0,r6,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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.L8:
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.L8:
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/* Data cache enable */
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/* Data cache enable */
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/* Check if DC present and skip enabling otherwise */
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/* Check if DC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_DCP
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l.andi r26,r24,SPR_UPR_DCP
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l.sfeq r26,r0
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l.sfeq r26,r0
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l.bf .L10
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l.bf .L10
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l.nop
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l.nop
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/* Disable DC */
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/* Disable DC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_DCE
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l.xori r5,r5,SPR_SR_DCE
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l.and r5,r6,r5
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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/* Establish cache block size
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If BS=0, 16;
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If BS=0, 16;
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If BS=1, 32;
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If BS=1, 32;
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r14 contain block size
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r14 contain block size
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*/
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*/
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l.mfspr r24,r0,SPR_DCCFGR
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l.mfspr r24,r0,SPR_DCCFGR
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l.andi r26,r24,SPR_DCCFGR_CBS
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l.andi r26,r24,SPR_DCCFGR_CBS
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l.srli r28,r26,7
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.ori r30,r0,16
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l.sll r14,r30,r28
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l.sll r14,r30,r28
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/* Establish number of cache sets
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/* Establish number of cache sets
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r16 contains number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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r28 contains log(# of cache sets)
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*/
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*/
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l.andi r26,r24,SPR_DCCFGR_NCS
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l.andi r26,r24,SPR_DCCFGR_NCS
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l.srli r28,r26,3
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.ori r30,r0,1
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l.sll r16,r30,r28
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l.sll r16,r30,r28
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/* Invalidate DC */
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/* Invalidate DC */
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l.addi r6,r0,0
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l.addi r6,r0,0
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l.sll r5,r14,r28
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l.sll r5,r14,r28
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.L9:
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.L9:
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l.mtspr r0,r6,SPR_DCBIR
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l.mtspr r0,r6,SPR_DCBIR
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l.sfne r6,r5
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l.sfne r6,r5
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l.bf .L9
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l.bf .L9
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l.add r6,r6,r14
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l.add r6,r6,r14
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/* Enable DC */
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/* Enable DC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_DCE
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l.ori r6,r6,SPR_SR_DCE
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l.mtspr r0,r6,SPR_SR
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l.mtspr r0,r6,SPR_SR
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.L10:
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.L10:
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/* Set up stack */
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/* Set up stack */
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l.movhi r1,hi(_stack-4)
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l.movhi r1,hi(_stack-4)
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l.ori r1,r1,lo(_stack-4)
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l.ori r1,r1,lo(_stack-4)
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l.addi r2,r0,-3
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l.addi r2,r0,-3
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l.and r1,r1,r2
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l.and r1,r1,r2
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l.or r2,r1,r1
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/* Clear BSS */
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/* Clear BSS */
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l.movhi r3, hi(_bstart)
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l.movhi r3, hi(_bstart)
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l.ori r3, r3, lo(_bstart)
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l.ori r3, r3, lo(_bstart)
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l.movhi r4, hi(_bend)
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l.movhi r4, hi(_bend)
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l.ori r4, r4, lo(_bend)
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l.ori r4, r4, lo(_bend)
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.L11:
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.L11:
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l.sw 0(r3),r0
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l.sw 0(r3),r0
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l.sfgtu r3, r4
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l.sfgtu r3, r4
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l.bnf .L11
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l.bnf .L11
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l.addi r3, r3, 4
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l.addi r3, r3, 4
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l.movhi r3,hi(main)
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l.movhi r3,hi(main)
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l.ori r3,r3,lo(main)
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l.ori r3,r3,lo(main)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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_int_wrapper:
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_int_wrapper:
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l.sw 0x8(r1), r4
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l.sw 0x8(r1), r4
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l.sw 0xc(r1), r5
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l.sw 0xc(r1), r5
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l.sw 0x10(r1), r6
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l.sw 0x10(r1), r6
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l.sw 0x14(r1), r7
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l.sw 0x14(r1), r7
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l.sw 0x18(r1), r8
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l.sw 0x18(r1), r8
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l.sw 0x1c(r1), r9
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l.sw 0x1c(r1), r9
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l.sw 0x20(r1), r10
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l.sw 0x20(r1), r10
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l.sw 0x24(r1), r11
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l.sw 0x24(r1), r11
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l.sw 0x28(r1), r12
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l.sw 0x28(r1), r12
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l.sw 0x2c(r1), r13
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l.sw 0x2c(r1), r13
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l.sw 0x30(r1), r14
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l.sw 0x30(r1), r14
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l.sw 0x34(r1), r15
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l.sw 0x34(r1), r15
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l.sw 0x38(r1), r16
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l.sw 0x38(r1), r16
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l.sw 0x3c(r1), r17
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l.sw 0x3c(r1), r17
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l.sw 0x40(r1), r18
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l.sw 0x40(r1), r18
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l.sw 0x44(r1), r19
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l.sw 0x44(r1), r19
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l.sw 0x48(r1), r20
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l.sw 0x48(r1), r20
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l.sw 0x4c(r1), r21
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l.sw 0x4c(r1), r21
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l.sw 0x50(r1), r22
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l.sw 0x50(r1), r22
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l.sw 0x54(r1), r23
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l.sw 0x54(r1), r23
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l.sw 0x58(r1), r24
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l.sw 0x58(r1), r24
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l.sw 0x5c(r1), r25
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l.sw 0x5c(r1), r25
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l.sw 0x60(r1), r26
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l.sw 0x60(r1), r26
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l.sw 0x64(r1), r27
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l.sw 0x64(r1), r27
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l.sw 0x68(r1), r28
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l.sw 0x68(r1), r28
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l.sw 0x6c(r1), r29
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l.sw 0x6c(r1), r29
|
l.sw 0x70(r1), r30
|
l.sw 0x70(r1), r30
|
l.sw 0x74(r1), r31
|
l.sw 0x74(r1), r31
|
|
|
l.movhi r3,hi(int_main)
|
l.movhi r3,hi(int_main)
|
l.ori r3,r3,lo(int_main)
|
l.ori r3,r3,lo(int_main)
|
l.jalr r3
|
l.jalr r3
|
l.nop
|
l.nop
|
|
|
l.lwz r3,0x4(r1)
|
l.lwz r3,0x4(r1)
|
l.lwz r4,0x8(r1)
|
l.lwz r4,0x8(r1)
|
l.lwz r5,0xc(r1)
|
l.lwz r5,0xc(r1)
|
l.lwz r6,0x10(r1)
|
l.lwz r6,0x10(r1)
|
l.lwz r7,0x14(r1)
|
l.lwz r7,0x14(r1)
|
l.lwz r8,0x18(r1)
|
l.lwz r8,0x18(r1)
|
l.lwz r9,0x1c(r1)
|
l.lwz r9,0x1c(r1)
|
l.lwz r10,0x20(r1)
|
l.lwz r10,0x20(r1)
|
l.lwz r11,0x24(r1)
|
l.lwz r11,0x24(r1)
|
l.lwz r12,0x28(r1)
|
l.lwz r12,0x28(r1)
|
l.lwz r13,0x2c(r1)
|
l.lwz r13,0x2c(r1)
|
l.lwz r14,0x30(r1)
|
l.lwz r14,0x30(r1)
|
l.lwz r15,0x34(r1)
|
l.lwz r15,0x34(r1)
|
l.lwz r16,0x38(r1)
|
l.lwz r16,0x38(r1)
|
l.lwz r17,0x3c(r1)
|
l.lwz r17,0x3c(r1)
|
l.lwz r18,0x40(r1)
|
l.lwz r18,0x40(r1)
|
l.lwz r19,0x44(r1)
|
l.lwz r19,0x44(r1)
|
l.lwz r20,0x48(r1)
|
l.lwz r20,0x48(r1)
|
l.lwz r21,0x4c(r1)
|
l.lwz r21,0x4c(r1)
|
l.lwz r22,0x50(r1)
|
l.lwz r22,0x50(r1)
|
l.lwz r23,0x54(r1)
|
l.lwz r23,0x54(r1)
|
l.lwz r24,0x58(r1)
|
l.lwz r24,0x58(r1)
|
l.lwz r25,0x5c(r1)
|
l.lwz r25,0x5c(r1)
|
l.lwz r26,0x60(r1)
|
l.lwz r26,0x60(r1)
|
l.lwz r27,0x64(r1)
|
l.lwz r27,0x64(r1)
|
l.lwz r28,0x68(r1)
|
l.lwz r28,0x68(r1)
|
l.lwz r29,0x6c(r1)
|
l.lwz r29,0x6c(r1)
|
l.lwz r30,0x70(r1)
|
l.lwz r30,0x70(r1)
|
l.lwz r31,0x74(r1)
|
l.lwz r31,0x74(r1)
|
|
|
l.lwz r2, 0x0(r1)
|
l.lwz r2, 0x0(r1)
|
l.addi r1,r1,256
|
l.addi r1,r1,256
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
|
|
/* Jump to error function. Clobber r2 */
|
/* Jump to error function. Clobber r2 */
|
_int_error:
|
_int_error:
|
l.movhi r2,hi(int_error)
|
l.movhi r2,hi(int_error)
|
l.ori r2,r2,lo(int_error)
|
l.ori r2,r2,lo(int_error)
|
l.jr r2
|
l.jr r2
|
l.nop
|
l.nop
|
|
|