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OpenRISC 1000Architecture Manual





 TIME \@ "MMMM d, yyyy" November 16, 2005




Table of Contents

 TOC \o "2-3" \h \z \t "Heading 1,1"  HYPERLINK \l "_Toc119923053" 
1       About this Manual        PAGEREF _Toc119923053 \h 
10
 HYPERLINK \l "_Toc119923054" 
1.1  Introduction     PAGEREF _Toc119923054 \h 
10
 HYPERLINK \l "_Toc119923055" 
1.2  Authors  PAGEREF _Toc119923055 \h 
10
 HYPERLINK \l "_Toc119923056" 
1.3  Revision History         PAGEREF _Toc119923056 \h 
11
 HYPERLINK \l "_Toc119923057" 
1.4  Work in Progress         PAGEREF _Toc119923057 \h 
12
 HYPERLINK \l "_Toc119923058" 
1.5  Fonts in this Manual     PAGEREF _Toc119923058 \h 
12
 HYPERLINK \l "_Toc119923059" 
1.6  Conventions      PAGEREF _Toc119923059 \h 
13
 HYPERLINK \l "_Toc119923060" 
1.7  Numbering        PAGEREF _Toc119923060 \h 
13
 HYPERLINK \l "_Toc119923061" 
2    Architecture Overview    PAGEREF _Toc119923061 \h 
14
 HYPERLINK \l "_Toc119923062" 
2.1  Features         PAGEREF _Toc119923062 \h 
14
 HYPERLINK \l "_Toc119923063" 
2.2  Introduction     PAGEREF _Toc119923063 \h 
14
 HYPERLINK \l "_Toc119923064" 
3    Addressing Modes and Operand Conventions         PAGEREF _Toc119923064 \h 
16
 HYPERLINK \l "_Toc119923065" 
3.1  Memory Addressing Modes  PAGEREF _Toc119923065 \h 
16
 HYPERLINK \l "_Toc119923066" 
3.1.1        Register Indirect with Displacement      PAGEREF _Toc119923066 \h 
16
 HYPERLINK \l "_Toc119923067" 
3.1.2        PC Relative      PAGEREF _Toc119923067 \h 
17
 HYPERLINK \l "_Toc119923068" 
3.2  Memory Operand Conventions       PAGEREF _Toc119923068 \h 
17
 HYPERLINK \l "_Toc119923069" 
3.2.1        Bit and Byte Ordering    PAGEREF _Toc119923069 \h 
18
 HYPERLINK \l "_Toc119923070" 
3.2.2        Aligned and Misaligned Accesses  PAGEREF _Toc119923070 \h 
19
 HYPERLINK \l "_Toc119923071" 
4    Register Set     PAGEREF _Toc119923071 \h 
20
 HYPERLINK \l "_Toc119923072" 
4.1  Features         PAGEREF _Toc119923072 \h 
20
 HYPERLINK \l "_Toc119923073" 
4.2  Overview         PAGEREF _Toc119923073 \h 
20
 HYPERLINK \l "_Toc119923074" 
4.3  Special-Purpose Registers        PAGEREF _Toc119923074 \h 
20
 HYPERLINK \l "_Toc119923075" 
4.4  General-Purpose Registers (GPRs)         PAGEREF _Toc119923075 \h 
24
 HYPERLINK \l "_Toc119923076" 
4.5  Support for Custom Number of GPRs        PAGEREF _Toc119923076 \h 
25
 HYPERLINK \l "_Toc119923077" 
4.6  Supervision Register (SR)        PAGEREF _Toc119923077 \h 
25
 HYPERLINK \l "_Toc119923078" 
4.7  Exception Program Counter Registers (EPCR0 - EPCR15)     PAGEREF _Toc119923078 \h 
27
 HYPERLINK \l "_Toc119923079" 
4.8  Exception Effective Address Registers (EEAR0-EEAR15)     PAGEREF _Toc119923079 \h 
27
 HYPERLINK \l "_Toc119923080" 
4.9  Exception Supervision Registers          (ESR0-ESR15)    PAGEREF _Toc119923080 \h 
28
 HYPERLINK \l "_Toc119923081" 
4.10 Next and Previous Program Counter (NPC and PPC)  PAGEREF _Toc119923081 \h 
28
 HYPERLINK \l "_Toc119923082" 
4.11 Floating Point Control Status Register (FPCSR)   PAGEREF _Toc119923082 \h 
28
 HYPERLINK \l "_Toc119923083" 
5    Instruction Set  PAGEREF _Toc119923083 \h 
31
 HYPERLINK \l "_Toc119923084" 
5.1  Features         PAGEREF _Toc119923084 \h 
31
 HYPERLINK \l "_Toc119923085" 
5.2  Overview         PAGEREF _Toc119923085 \h 
31
 HYPERLINK \l "_Toc119923086" 
5.3  ORBIS32/64       PAGEREF _Toc119923086 \h 
33
 HYPERLINK \l "_Toc119923087" 
6    Exception Model  PAGEREF _Toc119923087 \h 
252
 HYPERLINK \l "_Toc119923088" 
6.1 Introduction     PAGEREF _Toc119923088 \h 
252
 HYPERLINK \l "_Toc119923089" 
6.2 Exception Classes        PAGEREF _Toc119923089 \h 
252
 HYPERLINK \l "_Toc119923090" 
6.3 Exception Processing     PAGEREF _Toc119923090 \h 
254
 HYPERLINK \l "_Toc119923091" 
6.4 Fast Context Switching (Optional)        PAGEREF _Toc119923091 \h 
255
 HYPERLINK \l "_Toc119923092" 
6.4.1       Changing Context in Supervisor Mode      PAGEREF _Toc119923092 \h 
255
 HYPERLINK \l "_Toc119923093" 
6.4.2       Context Switch Caused by Exception       PAGEREF _Toc119923093 \h 
256
 HYPERLINK \l "_Toc119923094" 
6.4.3       Accessing Other Contexts� Registers      PAGEREF _Toc119923094 \h 
257
 HYPERLINK \l "_Toc119923095" 
7   Memory Model     PAGEREF _Toc119923095 \h 
258
 HYPERLINK \l "_Toc119923096" 
7.1 Memory   PAGEREF _Toc119923096 \h 
258
 HYPERLINK \l "_Toc119923097" 
7.2 Memory Access Ordering   PAGEREF _Toc119923097 \h 
258
 HYPERLINK \l "_Toc119923098" 
7.2.1       Memory Synchronize Instruction   PAGEREF _Toc119923098 \h 
258
 HYPERLINK \l "_Toc119923099" 
7.2.2       Pages Designated as Weakly-Ordered-Memory        PAGEREF _Toc119923099 \h 
258
 HYPERLINK \l "_Toc119923100" 
8   Memory Management        PAGEREF _Toc119923100 \h 
260
 HYPERLINK \l "_Toc119923101" 
8.1 MMU Features     PAGEREF _Toc119923101 \h 
260
 HYPERLINK \l "_Toc119923102" 
8.2 MMU Overview     PAGEREF _Toc119923102 \h 
260
 HYPERLINK \l "_Toc119923103" 
8.3 MMU Exceptions   PAGEREF _Toc119923103 \h 
262
 HYPERLINK \l "_Toc119923104" 
8.4 MMU Special-Purpose Registers    PAGEREF _Toc119923104 \h 
262
 HYPERLINK \l "_Toc119923105" 
8.4.1       Data MMU Control Register (DMMUCR)       PAGEREF _Toc119923105 \h 
264
 HYPERLINK \l "_Toc119923106" 
8.4.2       Data MMU Protection Register (DMMUPR)    PAGEREF _Toc119923106 \h 
264
 HYPERLINK \l "_Toc119923107" 
8.4.3       Instruction MMU Control Register (IMMUCR)        PAGEREF _Toc119923107 \h 
265
 HYPERLINK \l "_Toc119923108" 
8.4.4       Instruction MMU Protection Register (IMMUPR)     PAGEREF _Toc119923108 \h 
266
 HYPERLINK \l "_Toc119923109" 
8.4.5       Instruction/Data TLB Entry Invalidate Registers (xTLBEIR)        PAGEREF _Toc119923109 \h 
267
 HYPERLINK \l "_Toc119923110" 
8.4.6       Instruction/Data Translation Lookaside Buffer Way y Match Registers (xTLBWyMR0-xTLBWyMR127)      PAGEREF _Toc119923110 \h 
268
 HYPERLINK \l "_Toc119923111" 
8.4.7       Data Translation Lookaside Buffer Way y Translate Registers (DTLBWyTR0-DTLBWyTR127)      PAGEREF _Toc119923111 \h 
270
 HYPERLINK \l "_Toc119923112" 
8.4.8       Instruction Translation Lookaside Buffer Way y Translate Registers (ITLBWyTR0-ITLBWyTR127)       PAGEREF _Toc119923112 \h 
271
 HYPERLINK \l "_Toc119923113" 
8.4.9       Instruction/Data Area Translation Buffer Match Registers (xATBMR0-xATBMR3)       PAGEREF _Toc119923113 \h 
272
 HYPERLINK \l "_Toc119923114" 
8.4.10      Data Area Translation Buffer Translate Registers (DATBTR0-DATBTR3)       PAGEREF _Toc119923114 \h 
274
 HYPERLINK \l "_Toc119923115" 
8.4.11      Instruction Area Translation Buffer Translate Registers (IATBTR0-IATBTR3)        PAGEREF _Toc119923115 \h 
275
 HYPERLINK \l "_Toc119923116" 
8.5 Address Translation Mechanism in 32-bit Implementations  PAGEREF _Toc119923116 \h 
276
 HYPERLINK \l "_Toc119923117" 
8.6 Address Translation Mechanism in 64-bit Implementations  PAGEREF _Toc119923117 \h 
280
 HYPERLINK \l "_Toc119923118" 
8.7 Memory Protection Mechanism      PAGEREF _Toc119923118 \h 
283
 HYPERLINK \l "_Toc119923119" 
8.8 Page Table Entry Definition      PAGEREF _Toc119923119 \h 
284
 HYPERLINK \l "_Toc119923120" 
8.9 Page Table Search Operation      PAGEREF _Toc119923120 \h 
286
 HYPERLINK \l "_Toc119923121" 
8.10        Page History Recording   PAGEREF _Toc119923121 \h 
286
 HYPERLINK \l "_Toc119923122" 
8.11        Page Table Updates       PAGEREF _Toc119923122 \h 
286
 HYPERLINK \l "_Toc119923123" 
9   Cache Model & Cache Coherency	 PAGEREF _Toc119923123 \h 
288
 HYPERLINK \l "_Toc119923124" 
9.1	Cache Special-Purpose Registers	 PAGEREF _Toc119923124 \h 
288
 HYPERLINK \l "_Toc119923125" 
9.1.1	Data Cache Control Register	 PAGEREF _Toc119923125 \h 
289
 HYPERLINK \l "_Toc119923126" 
9.1.2	Instruction Cache Control Register	 PAGEREF _Toc119923126 \h 
289
 HYPERLINK \l "_Toc119923127" 
9.2	Cache Management	 PAGEREF _Toc119923127 \h 
290
 HYPERLINK \l "_Toc119923128" 
9.2.1	Data Cache Block Prefetch (Optional)	 PAGEREF _Toc119923128 \h 
290
 HYPERLINK \l "_Toc119923129" 
9.2.2	Data Cache Block Flush	 PAGEREF _Toc119923129 \h 
291
 HYPERLINK \l "_Toc119923130" 
9.2.3	Data Cache Block Invalidate	 PAGEREF _Toc119923130 \h 
292
 HYPERLINK \l "_Toc119923131" 
9.2.4	Data Cache Block Write-Back	 PAGEREF _Toc119923131 \h 
293
 HYPERLINK \l "_Toc119923132" 
9.2.5	Data Cache Block Lock (Optional)	 PAGEREF _Toc119923132 \h 
293
 HYPERLINK \l "_Toc119923133" 
9.2.6	Instruction Cache Block Prefetch (Optional)	 PAGEREF _Toc119923133 \h 
294
 HYPERLINK \l "_Toc119923134" 
9.2.7	Instruction Cache Block Invalidate	 PAGEREF _Toc119923134 \h 
294
 HYPERLINK \l "_Toc119923135" 
9.2.8	Instruction Cache Block Lock (Optional)	 PAGEREF _Toc119923135 \h 
295
 HYPERLINK \l "_Toc119923136" 
9.3	Cache/Memory Coherency	 PAGEREF _Toc119923136 \h 
296
 HYPERLINK \l "_Toc119923137" 
9.3.1	Pages Designated as Cache Coherent Pages	 PAGEREF _Toc119923137 \h 
296
 HYPERLINK \l "_Toc119923138" 
9.3.2	Pages Designated as Caching-Inhibited Pages	 PAGEREF _Toc119923138 \h 
296
 HYPERLINK \l "_Toc119923139" 
9.3.3	Pages Designated as Write-Back Cache Pages	 PAGEREF _Toc119923139 \h 
297
 HYPERLINK \l "_Toc119923140" 
10	Debug Unit (Optional)	 PAGEREF _Toc119923140 \h 
298
 HYPERLINK \l "_Toc119923141" 
10.1	Features	 PAGEREF _Toc119923141 \h 
298
 HYPERLINK \l "_Toc119923142" 
10.2	Debug Value Registers (DVR0-DVR7)	 PAGEREF _Toc119923142 \h 
299
 HYPERLINK \l "_Toc119923143" 
10.3	Debug Control Registers (DCR0-DCR7)	 PAGEREF _Toc119923143 \h 
300
 HYPERLINK \l "_Toc119923144" 
10.4	Debug Mode Register 1 (DMR1)	 PAGEREF _Toc119923144 \h 
301
 HYPERLINK \l "_Toc119923145" 
10.5	Debug Mode Register 2(DMR2)	 PAGEREF _Toc119923145 \h 
303
 HYPERLINK \l "_Toc119923146" 
10.6	Debug Watchpoint Counter Register (DWCR0-DWCR1)	 PAGEREF _Toc119923146 \h 
304
 HYPERLINK \l "_Toc119923147" 
10.7	Debug Stop Register (DSR)	 PAGEREF _Toc119923147 \h 
304
 HYPERLINK \l "_Toc119923148" 
10.8	Debug Reason Register (DRR)	 PAGEREF _Toc119923148 \h 
306
 HYPERLINK \l "_Toc119923149" 
11	Performance Counters Unit (Optional)	 PAGEREF _Toc119923149 \h 
308
 HYPERLINK \l "_Toc119923150" 
11.1	Features	 PAGEREF _Toc119923150 \h 
308
 HYPERLINK \l "_Toc119923151" 
11.2	Performance Counters Count Registers (PCCR0-PCCR7)	 PAGEREF _Toc119923151 \h 
308
 HYPERLINK \l "_Toc119923152" 
11.3	Performance Counters Mode Registers (PCMR0-PCMR7)	 PAGEREF _Toc119923152 \h 
309
 HYPERLINK \l "_Toc119923153" 
12	Power Management (Optional)	 PAGEREF _Toc119923153 \h 
311
 HYPERLINK \l "_Toc119923154" 
12.1	Features	 PAGEREF _Toc119923154 \h 
311
 HYPERLINK \l "_Toc119923155" 
12.2	Power Management Register (PMR)	 PAGEREF _Toc119923155 \h 
312
 HYPERLINK \l "_Toc119923156" 
13	Programmable Interrupt Controller (Optional)	 PAGEREF _Toc119923156 \h 
313
 HYPERLINK \l "_Toc119923157" 
13.1	Features	 PAGEREF _Toc119923157 \h 
313
 HYPERLINK \l "_Toc119923158" 
13.2	PIC Mask Register (PICMR)	 PAGEREF _Toc119923158 \h 
313
 HYPERLINK \l "_Toc119923159" 
13.3	PIC Status Register (PICSR)	 PAGEREF _Toc119923159 \h 
314
 HYPERLINK \l "_Toc119923160" 
14	Tick Timer Facility (Optional)	 PAGEREF _Toc119923160 \h 
316
 HYPERLINK \l "_Toc119923161" 
14.1	Features	 PAGEREF _Toc119923161 \h 
316
 HYPERLINK \l "_Toc119923162" 
14.2	Timer interrupts	 PAGEREF _Toc119923162 \h 
317
 HYPERLINK \l "_Toc119923163" 
14.3	Timer modes	 PAGEREF _Toc119923163 \h 
317
 HYPERLINK \l "_Toc119923164" 
14.3.1	Disabled timer	 PAGEREF _Toc119923164 \h 
317
 HYPERLINK \l "_Toc119923165" 
14.3.2	Auto-restart timer	 PAGEREF _Toc119923165 \h 
317
 HYPERLINK \l "_Toc119923166" 
14.3.3	One-shot timer	 PAGEREF _Toc119923166 \h 
317
 HYPERLINK \l "_Toc119923167" 
14.3.4	Continuous timer	 PAGEREF _Toc119923167 \h 
318
 HYPERLINK \l "_Toc119923168" 
14.4	Tick Timer Mode Register (TTMR)	 PAGEREF _Toc119923168 \h 
318
 HYPERLINK \l "_Toc119923169" 
14.5	Tick Timer Count Register (TTCR)	 PAGEREF _Toc119923169 \h 
319
 HYPERLINK \l "_Toc119923170" 
15	OpenRISC 1000 Implementations	 PAGEREF _Toc119923170 \h 
320
 HYPERLINK \l "_Toc119923171" 
15.1	Overview	 PAGEREF _Toc119923171 \h 
320
 HYPERLINK \l "_Toc119923172" 
15.2	Version Register (VR)	 PAGEREF _Toc119923172 \h 
320
 HYPERLINK \l "_Toc119923173" 
15.3	Unit Present Register (UPR)	 PAGEREF _Toc119923173 \h 
321
 HYPERLINK \l "_Toc119923174" 
15.4	CPU Configuration Register (CPUCFGR)	 PAGEREF _Toc119923174 \h 
322
 HYPERLINK \l "_Toc119923175" 
15.5	DMMU Configuration Register (DMMUCFGR)	 PAGEREF _Toc119923175 \h 
323
 HYPERLINK \l "_Toc119923176" 
15.6	IMMU Configuration Register (IMMUCFGR)	 PAGEREF _Toc119923176 \h 
325
 HYPERLINK \l "_Toc119923177" 
15.7	DC Configuration Register (DCCFGR)	 PAGEREF _Toc119923177 \h 
326
 HYPERLINK \l "_Toc119923178" 
15.8	IC Configuration Register (ICCFGR)	 PAGEREF _Toc119923178 \h 
327
 HYPERLINK \l "_Toc119923179" 
15.9	Debug Configuration Register (DCFGR)	 PAGEREF _Toc119923179 \h 
328
 HYPERLINK \l "_Toc119923180" 
15.10	Performance Counters Configuration Register (PCCFGR)	 PAGEREF _Toc119923180 \h 
329
 HYPERLINK \l "_Toc119923181" 
16	Application Binary Interface	 PAGEREF _Toc119923181 \h 
330
 HYPERLINK \l "_Toc119923182" 
16.1	Data Representation	 PAGEREF _Toc119923182 \h 
330
 HYPERLINK \l "_Toc119923183" 
16.1.1	Fundamental Types	 PAGEREF _Toc119923183 \h 
330
 HYPERLINK \l "_Toc119923184" 
16.1.2	Aggregates and Unions	 PAGEREF _Toc119923184 \h 
331
 HYPERLINK \l "_Toc119923185" 
16.1.3	Bit-fields	 PAGEREF _Toc119923185 \h 
332
 HYPERLINK \l "_Toc119923186" 
16.2	Function Calling Sequence	 PAGEREF _Toc119923186 \h 
333
 HYPERLINK \l "_Toc119923187" 
16.2.1	Register Usage	 PAGEREF _Toc119923187 \h 
333
 HYPERLINK \l "_Toc119923188" 
16.2.2	The Stack Frame	 PAGEREF _Toc119923188 \h 
335
 HYPERLINK \l "_Toc119923189" 
16.2.3	Parameter Passing	 PAGEREF _Toc119923189 \h 
335
 HYPERLINK \l "_Toc119923190" 
16.2.4	Functions Returning Scalars or No Value	 PAGEREF _Toc119923190 \h 
336
 HYPERLINK \l "_Toc119923191" 
16.2.5	Functions Returning Structures or Unions	 PAGEREF _Toc119923191 \h 
336
 HYPERLINK \l "_Toc119923192" 
16.3	Operating System Interface	 PAGEREF _Toc119923192 \h 
336
 HYPERLINK \l "_Toc119923193" 
16.3.1	Exception Interface	 PAGEREF _Toc119923193 \h 
336
 HYPERLINK \l "_Toc119923194" 
16.3.2	Virtual Address Space	 PAGEREF _Toc119923194 \h 
337
 HYPERLINK \l "_Toc119923195" 
16.3.3	Page Size	 PAGEREF _Toc119923195 \h 
337
 HYPERLINK \l "_Toc119923196" 
16.3.4	Virtual Address Assignments	 PAGEREF _Toc119923196 \h 
337
 HYPERLINK \l "_Toc119923197" 
16.3.5	Stack	 PAGEREF _Toc119923197 \h 
338
 HYPERLINK \l "_Toc119923198" 
16.3.6	Processor Execution Modes	 PAGEREF _Toc119923198 \h 
338
 HYPERLINK \l "_Toc119923199" 
16.4	Position-Independent Code	 PAGEREF _Toc119923199 \h 
338
 HYPERLINK \l "_Toc119923200" 
16.5	ELF	 PAGEREF _Toc119923200 \h 
338
 HYPERLINK \l "_Toc119923201" 
16.5.1	Header Convention	 PAGEREF _Toc119923201 \h 
338
 HYPERLINK \l "_Toc119923202" 
16.5.2	Sections	 PAGEREF _Toc119923202 \h 
339
 HYPERLINK \l "_Toc119923203" 
16.5.3	Relocation	 PAGEREF _Toc119923203 \h 
339
 HYPERLINK \l "_Toc119923204" 
16.6	COFF	 PAGEREF _Toc119923204 \h 
340
 HYPERLINK \l "_Toc119923205" 
16.6.1	Sections	 PAGEREF _Toc119923205 \h 
340
 HYPERLINK \l "_Toc119923206" 
16.6.2	Relocation	 PAGEREF _Toc119923206 \h 
340

Table Of Figures
 TOC \h \z \c "Figure"  HYPERLINK \l "_Toc118810327" 
Figure 31. Register Indirect with Displacement Addressing	 PAGEREF _Toc118810327 \h 
16
 HYPERLINK \l "_Toc118810328" 
Figure 32. PC Relative Addressing	 PAGEREF _Toc118810328 \h 
17
 HYPERLINK \l "_Toc118810329" 
Figure 51. Instruction Set	 PAGEREF _Toc118810329 \h 
31
 HYPERLINK \l "_Toc118810330" 
Figure 81. Translation of Effective to Physical Address � Simplified block diagram for 32-bit processor implementations	 PAGEREF _Toc118810330 \h 
261
 HYPERLINK \l "_Toc118810331" 
Figure 82. Memory Divided Into L1 and L2 pages	 PAGEREF _Toc118810331 \h 
277
 HYPERLINK \l "_Toc118810332" 
Figure 83. Address Translation Mechanism using Two-Level Page Table	 PAGEREF _Toc118810332 \h 
278
 HYPERLINK \l "_Toc118810333" 
Figure 84. Address Translation Mechanism using only L1 Page Table	 PAGEREF _Toc118810333 \h 
279
 HYPERLINK \l "_Toc118810334" 
Figure 85. Memory Divided Into L0, L1 and L2 pages	 PAGEREF _Toc118810334 \h 
280
 HYPERLINK \l "_Toc118810335" 
Figure 86. Address Translation Mechanism using Three-Level Page Table	 PAGEREF _Toc118810335 \h 
281
 HYPERLINK \l "_Toc118810336" 
Figure 87. Address Translation Mechanism using Two-Level Page Table	 PAGEREF _Toc118810336 \h 
282
 HYPERLINK \l "_Toc118810337" 
Figure 88. Selection of Page Protection Attributes for Data Accesses	 PAGEREF _Toc118810337 \h 
284
 HYPERLINK \l "_Toc118810338" 
Figure 89. Selection of Page Protection Attributes for Instruction Fetch Accesses	 PAGEREF _Toc118810338 \h 
284
 HYPERLINK \l "_Toc118810339" 
Figure 810. Page Table Entry Format	 PAGEREF _Toc118810339 \h 
285
 HYPERLINK \l "_Toc118810340" 
Figure 101. Block Diagram of Debug Support	 PAGEREF _Toc118810340 \h 
299
 HYPERLINK \l "_Toc118810341" 
Figure 131. Programmable Interrupt Controller Block Diagram	 PAGEREF _Toc118810341 \h 
313
 HYPERLINK \l "_Toc118810342" 
Figure 141. Tick Timer Block Diagram	 PAGEREF _Toc118810342 \h 
316
 HYPERLINK \l "_Toc118810343" 
Figure 161. Byte aligned, sizeof is 1	 PAGEREF _Toc118810343 \h 
331
 HYPERLINK \l "_Toc118810344" 
Figure 162. No padding, sizeof is 8	 PAGEREF _Toc118810344 \h 
331
 HYPERLINK \l "_Toc118810345" 
Figure 163. Padding, sizeof is 18	 PAGEREF _Toc118810345 \h 
332
 HYPERLINK \l "_Toc118810346" 
Figure 164. Storage unit sharingand alignment padding, sizeof is 12	 PAGEREF _Toc118810346 \h 
333

Table Of Tables
 TOC \h \z \c "Table"  HYPERLINK \l "_Toc118810248" 
Table 11. Acronyms and Abbreviations	 PAGEREF _Toc118810248 \h 
9
 HYPERLINK \l "_Toc118810249" 
Table 11. Authors of this Manual	 PAGEREF _Toc118810249 \h 
10
 HYPERLINK \l "_Toc118810250" 
Table 12. Revision History	 PAGEREF _Toc118810250 \h 
12
 HYPERLINK \l "_Toc118810251" 
Table 13. Conventions	 PAGEREF _Toc118810251 \h 
13
 HYPERLINK \l "_Toc118810252" 
Table 31. Memory Operands and their sizes	 PAGEREF _Toc118810252 \h 
18
 HYPERLINK \l "_Toc118810253" 
Table 32. Default Bit and Byte Ordering in Halfwords	 PAGEREF _Toc118810253 \h 
18
 HYPERLINK \l "_Toc118810254" 
Table 33. Default Bit and Byte Ordering in Singlewords and Single Precision Floats	 PAGEREF _Toc118810254 \h 
18
 HYPERLINK \l "_Toc118810255" 
Table 34. Default Bit and Byte Ordering in Doublewords, Double Precision Floats and all Vector Types	 PAGEREF _Toc118810255 \h 
19
 HYPERLINK \l "_Toc118810256" 
Table 35. Memory Operand Alignment	 PAGEREF _Toc118810256 \h 
19
 HYPERLINK \l "_Toc118810257" 
Table 41. Groups of SPRs	 PAGEREF _Toc118810257 \h 
21
 HYPERLINK \l "_Toc118810258" 
Table 42. List of All Special-Purpose Registers	 PAGEREF _Toc118810258 \h 
24
 HYPERLINK \l "_Toc118810259" 
Table 43. General-Purpose Registers	 PAGEREF _Toc118810259 \h 
24
 HYPERLINK \l "_Toc118810260" 
Table 44. SR Field Descriptions	 PAGEREF _Toc118810260 \h 
27
 HYPERLINK \l "_Toc118810261" 
Table 45. EPCR Field Descriptions	 PAGEREF _Toc118810261 \h 
27
 HYPERLINK \l "_Toc118810262" 
Table 46. EEAR Field Descriptions	 PAGEREF _Toc118810262 \h 
28
 HYPERLINK \l "_Toc118810263" 
Table 47. ESR Field Descriptions	 PAGEREF _Toc118810263 \h 
28
 HYPERLINK \l "_Toc118810264" 
Table 48. FPCSR Field Descriptions	 PAGEREF _Toc118810264 \h 
30
 HYPERLINK \l "_Toc118810265" 
Table 51. OpenRISC 1000 Instruction Classes	 PAGEREF _Toc118810265 \h 
32
 HYPERLINK \l "_Toc118810266" 
Table 61. Exception Classes	 PAGEREF _Toc118810266 \h 
252
 HYPERLINK \l "_Toc118810267" 
Table 62. Exception Types and Causal Conditions	 PAGEREF _Toc118810267 \h 
253
 HYPERLINK \l "_Toc118810268" 
Table 63. Values of EPCR and EEAR After Exception	 PAGEREF _Toc118810268 \h 
255
 HYPERLINK \l "_Toc118810269" 
Table 81. MMU Exceptions	 PAGEREF _Toc118810269 \h 
262
 HYPERLINK \l "_Toc118810270" 
Table 82. List of MMU Special-Purpose Registers	 PAGEREF _Toc118810270 \h 
263
 HYPERLINK \l "_Toc118810271" 
Table 83. DMMUCR Field Descriptions	 PAGEREF _Toc118810271 \h 
264
 HYPERLINK \l "_Toc118810272" 
Table 84. DMMUPR Field Descriptions	 PAGEREF _Toc118810272 \h 
265
 HYPERLINK \l "_Toc118810273" 
Table 85. IMMUCR Field Descriptions	 PAGEREF _Toc118810273 \h 
266
 HYPERLINK \l "_Toc118810274" 
Table 86. IMMUPR Field Descriptions	 PAGEREF _Toc118810274 \h 
267
 HYPERLINK \l "_Toc118810275" 
Table 87. xTLBEIR Field Descriptions	 PAGEREF _Toc118810275 \h 
267
 HYPERLINK \l "_Toc118810276" 
Table 88. xTLBMR Field Descriptions	 PAGEREF _Toc118810276 \h 
269
 HYPERLINK \l "_Toc118810277" 
Table 89. DTLBTR Field Descriptions	 PAGEREF _Toc118810277 \h 
271
 HYPERLINK \l "_Toc118810278" 
Table 810. ITLBWyTR Field Descriptions	 PAGEREF _Toc118810278 \h 
272
 HYPERLINK \l "_Toc118810279" 
Table 811. xATBMR Field Descriptions	 PAGEREF _Toc118810279 \h 
273
 HYPERLINK \l "_Toc118810280" 
Table 812. DATBTR Field Descriptions	 PAGEREF _Toc118810280 \h 
275
 HYPERLINK \l "_Toc118810281" 
Table 813. IATBTR Field Descriptions	 PAGEREF _Toc118810281 \h 
276
 HYPERLINK \l "_Toc118810282" 
Table 814. Protection Attributes	 PAGEREF _Toc118810282 \h 
283
 HYPERLINK \l "_Toc118810283" 
Table 815. PTE Field Descriptions	 PAGEREF _Toc118810283 \h 
285
 HYPERLINK \l "_Toc118810284" 
Table 91. Cache Registers	 PAGEREF _Toc118810284 \h 
289
 HYPERLINK \l "_Toc118810285" 
Table 92. DCCR Field Descriptions	 PAGEREF _Toc118810285 \h 
289
 HYPERLINK \l "_Toc118810286" 
Table 93. ICCR Field Descriptions	 PAGEREF _Toc118810286 \h 
290
 HYPERLINK \l "_Toc118810287" 
Table 94. DCBPR Field Descriptions	 PAGEREF _Toc118810287 \h 
291
 HYPERLINK \l "_Toc118810288" 
Table 95. DCBFR Field Descriptions	 PAGEREF _Toc118810288 \h 
292
 HYPERLINK \l "_Toc118810289" 
Table 96. DCBIR Field Descriptions	 PAGEREF _Toc118810289 \h 
292
 HYPERLINK \l "_Toc118810290" 
Table 97. DCBWR Field Descriptions	 PAGEREF _Toc118810290 \h 
293
 HYPERLINK \l "_Toc118810291" 
Table 98. DCBLR Field Descriptions	 PAGEREF _Toc118810291 \h 
294
 HYPERLINK \l "_Toc118810292" 
Table 99. ICBPR Field Descriptions	 PAGEREF _Toc118810292 \h 
294
 HYPERLINK \l "_Toc118810293" 
Table 910. ICBIR Field Descriptions	 PAGEREF _Toc118810293 \h 
295
 HYPERLINK \l "_Toc118810294" 
Table 911. ICBLR Field Descriptions	 PAGEREF _Toc118810294 \h 
295
 HYPERLINK \l "_Toc118810295" 
Table 101. DVR Field Descriptions	 PAGEREF _Toc118810295 \h 
299
 HYPERLINK \l "_Toc118810296" 
Table 102. DCR Field Descriptions	 PAGEREF _Toc118810296 \h 
300
 HYPERLINK \l "_Toc118810297" 
Table 103. DMR1 Field Descriptions	 PAGEREF _Toc118810297 \h 
302
 HYPERLINK \l "_Toc118810298" 
Table 104. DMR2 Field Descriptions	 PAGEREF _Toc118810298 \h 
304
 HYPERLINK \l "_Toc118810299" 
Table 105. DWCR Field Descriptions	 PAGEREF _Toc118810299 \h 
304
 HYPERLINK \l "_Toc118810300" 
Table 106. DSR Field Descriptions	 PAGEREF _Toc118810300 \h 
306
 HYPERLINK \l "_Toc118810301" 
Table 107. DRR Field Descriptions	 PAGEREF _Toc118810301 \h 
307
 HYPERLINK \l "_Toc118810302" 
Table 111. PCCR0 Field Descriptions	 PAGEREF _Toc118810302 \h 
309
 HYPERLINK \l "_Toc118810303" 
Table 112. PCMR Field Descriptions	 PAGEREF _Toc118810303 \h 
310
 HYPERLINK \l "_Toc118810304" 
Table 121. PMR Field Descriptions	 PAGEREF _Toc118810304 \h 
312
 HYPERLINK \l "_Toc118810305" 
Table 131. PICMR Field Descriptions	 PAGEREF _Toc118810305 \h 
314
 HYPERLINK \l "_Toc118810306" 
Table 132. PICSR Field Descriptions	 PAGEREF _Toc118810306 \h 
315
 HYPERLINK \l "_Toc118810307" 
Table 141. TTMR Field Descriptions	 PAGEREF _Toc118810307 \h 
318
 HYPERLINK \l "_Toc118810308" 
Table 142. TTCR Field Descriptions	 PAGEREF _Toc118810308 \h 
319
 HYPERLINK \l "_Toc118810309" 
Table 151. VR Field Descriptions	 PAGEREF _Toc118810309 \h 
321
 HYPERLINK \l "_Toc118810310" 
Table 152. UPR Field Descriptions	 PAGEREF _Toc118810310 \h 
322
 HYPERLINK \l "_Toc118810311" 
Table 153. CPUCFGR Field Descriptions	 PAGEREF _Toc118810311 \h 
323
 HYPERLINK \l "_Toc118810312" 
Table 154. DMMUCFGR Field Descriptions	 PAGEREF _Toc118810312 \h 
324
 HYPERLINK \l "_Toc118810313" 
Table 155. IMMUCFGR Field Descriptions	 PAGEREF _Toc118810313 \h 
326
 HYPERLINK \l "_Toc118810314" 
Table 156. DCCFGR Field Descriptions	 PAGEREF _Toc118810314 \h 
327
 HYPERLINK \l "_Toc118810315" 
Table 157. ICCFGR Field Descriptions	 PAGEREF _Toc118810315 \h 
328
 HYPERLINK \l "_Toc118810316" 
Table 158. DCFGR Field Descriptions	 PAGEREF _Toc118810316 \h 
329
 HYPERLINK \l "_Toc118810317" 
Table 159. PCCFGR Field Descriptions	 PAGEREF _Toc118810317 \h 
329
 HYPERLINK \l "_Toc118810318" 
Table 161.  Scalar Types	 PAGEREF _Toc118810318 \h 
330
 HYPERLINK \l "_Toc118810319" 
Table 162.  Vector Types	 PAGEREF _Toc118810319 \h 
331
 HYPERLINK \l "_Toc118810320" 
Table 163.  Bit-Field Types and Ranges	 PAGEREF _Toc118810320 \h 
332
 HYPERLINK \l "_Toc118810321" 
Table 164. General-Purpose Registers	 PAGEREF _Toc118810321 \h 
334
 HYPERLINK \l "_Toc118810322" 
Table 165. Stack Frame	 PAGEREF _Toc118810322 \h 
335
 HYPERLINK \l "_Toc118810323" 
Table 166. Hardware Exceptions and Signals	 PAGEREF _Toc118810323 \h 
336
 HYPERLINK \l "_Toc118810324" 
Table 167. Virtual Address Configuration	 PAGEREF _Toc118810324 \h 
338
 HYPERLINK \l "_Toc118810325" 
Table 168.  e_ident Field Values	 PAGEREF _Toc118810325 \h 
339
 HYPERLINK \l "_Toc118810326" 
Table 169.  e_flags Field Values	 PAGEREF _Toc118810326 \h 
339

Acronyms & Abbreviations
ALUArithmetic Logic UnitATBArea Translation BufferBIUBus Interface UnitBTCBranch Target CacheCPUCentral Processing UnitDCData CacheDMMUData MMUDTLBData TLBDUDebug UnitEAEffective addressFPUFloating-Point UnitGPRGeneral-Purpose RegisterICInstruction CacheIMMUInstruction MMUITLBInstruction TLBMMUMemory Management UnitOR1KOpenRISC 1000 ArchitectureORBISOpenRISC Basic Instruction SetORFPXOpenRISC Floating-Point eXtensionORVDXOpenRISC Vector/DSP eXtensionPCProgram CounterPCUPerformance Counters UnitPICProgrammable Interrupt ControllerPMPower ManagementPTEPage Table EntryR/WRead/WriteRISCReduced Instruction Set ComputerSMPSymmetrical Multi-ProcessingSMTSimultaneous Multi-ThreadingSPRSpecial-Purpose RegisterSRSupervison RegisterTLBTranslation Lookaside BufferTable  STYLEREF 1 \s 1 SEQ Table \* ARABIC \s 1 1. Acronyms and Abbreviations
About this Manual
Introduction
The OpenRISC 1000 system architecture manual defines the architecture for a family of open-source, synthesizable RISC microprocessor cores. The OpenRISC 1000 architecture allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, and scalability. The OpenRISC 1000 architecture targets medium and high performance networking and embedded computer environments.
This manual covers the instruction set, register set, cache management and coherency, memory model, exception model, addressing modes, operands conventions, and the application binary interface (ABI).
This manual does not specify implementation-specific details such as pipeline depth, cache organization, branch prediction, instruction timing, bus interface etc.

Authors
If you have contributed to this manual but your name isn't listed here, it is not meant as a slight � We simply don't know about it. Send an email to the maintainer(s), and we'll correct the situation.

NameE-mailContributionDamjan Lampret HYPERLINK "mailto:damjanl@opencores.org" 
damjanl@opencores.orgInitial documentChen-Min Chen HYPERLINK "mailto:jimmy@ee.nctu.edu.tw" 
jimmy@ee.nctu.edu.twSome notesMarko Mlinar HYPERLINK "mailto:markom@opencores.org" 
markom@opencores.orgFast context switchesJohan Rydberg HYPERLINK "mailto:jrydberg@opencores.org" 
jrydberg@opencores.orgELF sectionMatan Ziv-Av HYPERLINK "mailto:matan@svgalib.org" 
matan@svgalib.orgSeveral suggestionsChris Ziomkowski HYPERLINK "mailto:chris@opencores.org" 
chris@opencores.orgSeveral suggestionsGreg McGary HYPERLINK "mailto:greg@mcgary.org" 
greg@mcgary.orgl.cmov, trap exceptionBob GardnerNative Speaker CheckRohit Mathur HYPERLINK "mailto:rmathur@binghamton.edu" 
rohitmathurs@opencores.orgTechnical review and correctionsMaria Bolado HYPERLINK "mailto:mbolado@teisa.unican.es" 
mbolado@teisa.unican.esTechnical review and correctionsTable  STYLEREF 1 \s 1 SEQ Table \* ARABIC \s 1 1. Authors of this Manual
Revision History
The revision history of this manual is presented in the table below.

Revision DateByModifications15/Mar/2000Damjan LampretInitial document7/Apr/2001Damjan LampretFirst public release22/Apr/2001Damjan LampretIncorporated changes from Johan and Matan16/May/2001Damjan LampretChanged SR, Debug, Exceptions, TT, PM. Added l.cmov, l.ff1, etc.23/May/2001Damjan LampretAdded SR[SUMRA], configuration registerc etc.24/May/2001Damjan LampretChanged virtually almost all chapters in some way � major change is addition of configuration registers.28/May/2001Damjan LampretChanged addresses of some SPRs, removed group SPR group 11, added DCR[CT]=7.24/Jan/2002Marko MlinarMajor check and update9/Apr/2002Marko MlinarPICPR register removed; l.sys convention added; mtspr/mfspr now use bitwise OR instead of sum28/July/2002Jeanne WiegelmannFirst overall review & layout adjustment20/Spetember/2002Rohit MathurSecond overall review12/January/2003Damjan LampretSynchronization with or1ksim and OR1200 RTL. Not all chapters have been checked.26/January/2003Damjan LampretSynchronization with or1ksim and OR1200 RTL. From this revision on the manual carries revision number 1.0 and parts of the architecture that are implemented in OR1200 will no longer change because OR1200 is being implemented in silicon. Major parts that are not implemented in OR1200 and could change in the future include ORFPX, ORVDX, PCU, fast context switching, and 64-bit extension.26/June/2004Damjan LampretFixed typos in instruction set description reported by Victor Lopez, Giles Hall and Lu�s Vit�rio Cargnini. Fixed typos in various chapters reported by Matjaz Breskvar. Changed description of PICSR. Updated ABI chapter based on agreed ABI from the openrisc mailing list. Removed DMR1[ETE], clearly defined watchpoints&breakpoint, split long watchpoint chain into two, removed WP10 and removed DMR1[DXFW], updated DMR2. Fixed FP definition (added FP exception. FPCSR register).3/Nov/2005Damjan LampretCorrected description of l.ff1, added l.fl1 instruction, corrected encoding of l.maci and added more description of tick timer.15/Nov/2005Damjan LampretCorrected description of l.sfXXui (arch manual had a wrong description compared to behavior implemented in or1ksim/gcc/or1200). Removed Atomicity chapter.Table  STYLEREF 1 \s 1 SEQ Table \* ARABIC \s 1 2. Revision History

Work in Progress
This document is work in progress. Anything in the manual could change until we have made our first silicon. The latest version is always available from OPENCORES CVS. See details about how to get it on HYPERLINK "http://www.opencores.org/"
www.opencores.org. 
We are currently looking for people to work on and maintain this document. If you would like to contribute, please send an email to one of the authors.

Fonts in this Manual
In this manual, fonts are used as follows:
Typewriter font is used for programming examples.
Bold font is used for emphasis.
UPPER CASE items may be either acronyms or register mode fields that can be written by software. Some common acronyms appear in the glossary.
Square brackets [] indicate an addressed field in a register or a numbered register in a register file.

Conventions
l.mnemonicIdentifies an ORBIS32/64 instruction.lv.mnemonicIdentifies an ORVDX32/64 instruction.lf.mnemonicIdentifies an ORFPX32/64 instruction.0xIndicates a hexadecimal number.rAInstruction syntax used to identify a general purpose registerREG[FIELD]Syntax used to identify specific bit(s) of a general or special purpose register. FIELD can be a name of one bit or a group of bits or a numerical range constructed from two values separated by a colon.XIn certain contexts, this indicates a �don't care�.NIn certain contexts, this indicates an undefined numerical value.ImplementationAn actual processor implementing the OpenRISC 1000 architecture.UnitSometimes referred to as a coprocessor. An implemented unit usually with some special registers and controlling instructions. It can be defined by the architecture or it may be custom.ExceptionA vectored transfer of control to supervisor software through an exception vector table. A way in which a processor can request operating system assistance (division by zero, TLB miss, external interrupt etc).PrivilegedAn instruction (or register) that can only be executed (or accessed) when the processor is in supervisor mode (when SR[SM]=1).Table  STYLEREF 1 \s 1 SEQ Table \* ARABIC \s 1 3. Conventions

Numbering
All numbers are decimal or hexadecimal unless otherwise indicated. The prefix 0x indicates a hexadecimal number. Decimal numbers don't have a special prefix. Binary and other numbers are marked with their base.

Architecture Overview
This chapter introduces the OpenRISC 1000 architecture and describes the general architectural features.

Features
The OpenRISC 1000 architecture includes the following principal features:
A completely free and open architecture.
A linear, 32-bit or 64-bit logical address space with implementation-specific physical address space.
Simple and uniform-length instruction formats featuring different instruction set extensions:
OpenRISC Basic Instruction Set (ORBIS32/64) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 32- and 64-bit data
OpenRISC Vector/DSP eXtension (ORVDX64) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 8-, 16-, 32- and 64-bit data
OpenRISC Floating-Point eXtension (ORFPX32/64) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 32- and 64-bit data
Two simple memory addressing modes, whereby memory address is calculated by:
addition of a register operand and a signed 16-bit immediate value
addition of a register operand and a signed 16-bit immediate value followed by update of the register operand with the calculated effective address
Two register operands (or one register and a constant) for most instructions who then place the result in a third register
Shadowed or single 32-entry or narrow 16-entry general purpose register file
Branch delay slot for keeping the pipeline as full as possible
Support for separate instruction and data caches/MMUs (Harvard architecture) or for unified instruction and data caches/MMUs (Stanford architecture)
A flexible architecture definition that allows certain functions to be performed either in hardware or with the assistance of implementation-specific software
Number of different, separated exceptions simplifying exception model
Fast context switch support in register set, caches, and MMUs

Introduction
The OpenRISC 1000 architecture is a completely open architecture. It defines the architecture of a family of open source, RISC microprocessor cores. The OpenRISC 1000 architecture allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, and scalability. OpenRISC 1000 targets medium and high performance networking and embedded computer environments.
Performance features include a full 32/64-bit architecture; vector, DSP and floating-point instructions; powerful virtual memory support; cache coherency; optional SMP and SMT support, and support for fast context switching. The architecture defines several features for networking and embedded computer environments. Most notable are several instruction extensions, a configurable number of general-purpose registers, configurable cache and TLB sizes, dynamic power management support, and space for user-provided instructions.
The OpenRISC 1000 architecture is the predecessor of a richer and more powerful next generation of OpenRISC architectures.
The full source for implementations of the OpenRISC 1000 architecture is available at  HYPERLINK "http://www.opencores.org" 
www.opencores.org and is supported with GNU software development tools and a behavioral simulator. Most OpenRISC implementations are designed to be modular and vendor-independent. They can be interfaced with other open-source cores available at  HYPERLINK "http://www.opencores.org" 
www.opencores.org.
Opencores.org encourages third parties to design and market their own implementations of the OpenRISC 1000 architecture and to participate in further development of the architecture.
Addressing Modes andOperand Conventions
This chapter describes memory-addressing modes and memory operand conventions defined by the OpenRISC 1000 system architecture.

Memory Addressing Modes
The processor computes an effective address when executing a memory access instruction or branch instruction or when fetching the next sequential instruction. If the sum of the effective address and the operand length exceeds the maximum effective address in logical address space, the memory operand wraps around from the maximum effective address through effective address 0.

Register Indirect with Displacement
Load/store instructions using this address mode contain a signed 16-bit immediate value, which is sign-extended and added to the contents of a general-purpose register specified in the instruction.
 EMBED Visio.Drawing.5  

Figure  STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 1. Register Indirect with Displacement Addressing

 REF _Ref479666317 \h 
Figure 31 shows how an effective address is computed when using register indirect with displacement addressing mode.

PC Relative        
Branch instructions using this address mode contain a signed 26-bit immediate value that is sign-extended and added to the contents of a Program Counter register. Before the execution at the destination PC, instruction in delay slot is executed.
 EMBED Visio.Drawing.5  

Figure  STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 2. PC Relative Addressing

 REF _Ref479669695 \h 
Figure 32 shows how an effective address is generated when using PC relative addressing mode.

Memory Operand Conventions
The architecture defines an 8-bit byte, 16-bit halfword, a 32-bit word, and a 64-bit doubleword. It also defines IEEE-754 compliant 32-bit single precision float and 64-bit double precision float storage units. 64-bit vectors of bytes, 64-bit vectors of halfwords, 64-bit vectors of singlewords, and 64-bit vectors of single precision floats are also defined.

Type of DataLength in BytesLength in BitsByte18Halfword (or half)216Singleword (or word)432Doubleword (or double)864Single precision float432Double precision float864Vector of bytes864Vector of halfwords864Vector of singlewords864Vector of single precision floats864Table  STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 1. Memory Operands and their sizes

Bit and Byte Ordering
Byte ordering defines how the bytes that make up halfwords, singlewords and doublewords are ordered in memory. To simplify OpenRISC implementations, the architecture implements Most Significant Byte (MSB) ordering � or big endian byte ordering by default. But implementations can support Least Significant Byte (LSB) ordering if they implement byte reordering hardware. Reordering is enabled with bit SR[LEE].
The figures below illustrate the conventions for bit and byte numbering within various width storage units. These conventions hold for both integer and floating-point data, where the most significant byte of a floating-point value holds the sign and at least significant byte holds the start of the exponent.
 REF _Ref478299719 \h 
Table 32 shows how bits and bytes are ordered in a halfword.

Bit 15Bit 8Bit 7Bit 0MSBLSBByte address 0Byte address 1Table  STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 2. Default Bit and Byte Ordering in Halfwords

 REF _Ref478306009 \h 
Table 33 shows how bits and bytes are ordered in a singleword.

Bit 31Bit 24Bit 23Bit 16Bit 15Bit 8Bit 7Bit 0MSBLSBByte address 0Byte address 1Byte address 2Byte address 3Table  STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 3. Default Bit and Byte Ordering in Singlewords and Single Precision Floats

 REF _Ref478306020 \h 
Table 34 shows how bits and bytes are ordered in a doubleword.

Bit 63Bit 56MSBByte address 0Byte address 1Byte address 2Byte address 3Bit 7Bit 0LSBByte address 4Byte address 5Byte address 6Byte address 7Table  STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 4. Default Bit and Byte Ordering in Doublewords, Double Precision Floats and all Vector Types

Aligned and Misaligned Accesses
A memory operand is naturally aligned if its address is an integral multiple of the operand length. Implementations might support accessing unaligned memory operands, but the default behavior is that accesses to unaligned operands result in an alignment exception. See chapter  REF _Ref478994165 \h Error! Reference source not found. on page  PAGEREF _Ref478994182 \h Error! Bookmark not defined. for information on alignment exception.

OperandLengthaddr[3:0] if alignedByte8 bitsXxxxHalfword (or half)2 bytesXxx0Singleword (or word)4 bytesXx00Doubleword (or double)8 bytesX000Single precision float4 bytesXx00Double precision float8 bytesX000Vector of bytes8 bytesX000Vector of halfwords8 bytesX000Vector of singlewords8 bytesX000Vector of single precision floats8 bytesX000Table  STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 5. Memory Operand Alignment

OR32 instructions are four bytes long and word-aligned.
Register Set
Features
The OpenRISC 1000 register set includes the following principal features:
Thirty-two or sixteen 32/64-bit general-purpose registers � OpenRISC 1000 implementations optimized for use in FPGAs and ASICs in embedded and similar environments may implement only the first sixteen of the possible thirty-two registers.
All other registers are special-purpose registers defined for each unit separately and accessible through the l.mtspr/l.mfspr instructions.

Overview
An OpenRISC 1000 processor includes several types of registers: user level general-purpose and special-purpose registers, supervisor level special-purpose registers and unit-dependent registers.
User level general-purpose and special-purpose registers are accessible both in user mode and supervisor mode of operation. Supervisor level special-purpose registers are accessible only in supervisor mode of operation (SR[SM]=1).
Unit dependent registers are usually only accessible in supervisor mode but there can be exceptions to this rule. Accessibility for architecture-defined units is defined in this manual. Accessibility for custom units not covered by this manual will be defined in the appropriate implementation-specific manuals.

Special-Purpose Registers
The special-purpose registers of all units are grouped into thirty-two groups. Each group can have different register address decoding depending on the maximum theoretical number of registers in that particular group. A group can contain registers from several different units or processes. The SR[SM] bit is also used in register address decoding, as some registers are accessible only in supervisor mode. The l.mtspr and l.mfspr instructions are used for reading and writing registers.

GROUP #UNIT DESCRIPTION0System Control and Status registers1Data MMU (in the case of a single unified MMU, groups 1 and 2 decode into a single set of registers)2Instruction MMU (in the case of a single unified MMU, groups 1 and 2 decode into a single set of registers)3Data Cache (in the case of a single unified cache, groups 3 and 4 decode into a single set of registers)4Instruction Cache (in the case of a single unified cache, groups 3 and 4 decode into a single set of registers)5MAC unit6Debug unit7Performance counters unit8Power Management9Programmable Interrupt Controller10Tick Timer11Floating Point unit12-23Reserved for future use24-31Custom unitsTable  STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 1. Groups of SPRs

An OpenRISC 1000 processor implementation is required to implement at least the special purpose registers from group 0. All other groups are optional, and registers from these groups are implemented only if the implementation has the corresponding unit. Which units are actually implemented may be determined by reading the UPR register from group 0.
           A 16-bit SPR address is made of 5-bit group index (bits 15-11) and 11-bit register index (bits 10-0).

Grp #Reg #Reg NameUSER MODESUPV MODEDescription00VR�RVersion register01UPR�RUnit Present register02CPUCFGR�RCPU Configuration register03DMMUCFGR�RData MMU Configuration register04IMMUCFGR�RInstruction MMU Configuration register05DCCFGR�RData Cache Configuration register06ICCFGR�RInstruction Cache Configuration register07DCFGR�RDebug Configuration register08PCCFGR�RPerformance Counters Configuration register016NPC�R/WPC mapped to SPR space (next PC)017SR�R/WSupervision register018PPC�R/WPC mapped to SPR space (previous PC)020FPCSRR*R/WFP Control Status register032-47EPCR0-EPCR15�R/WException PC registers048-63EEAR0-EEAR15�R/WException EA registers064-79ESR0-ESR15�R/WException SR registers01024-1535GPR0-GPR511�R/WGPRs mapped to SPR space10DMMUCR�R/WData MMU Control register11DMMUPR�R/WData MMU Protection Register12DTLBEIR�WData TLB Entry Invalidate register14-7DATBMR0-DATBMR3�R/WData ATB Match registers18-11DATBTR0-DATBTR3�R/WData ATB Translate registers1512-639DTLBW0MR0-DTLBW0MR127�R/WData TLB Match registers Way 01640-767DTLBW0TR0-DTLBW0TR127�R/WData TLB Translate registers Way 01768-895DTLBW1MR0-DTLBW1MR127�R/WData TLB Match registers Way 11896-1023DTLBW1TR0-DTLBW1TR127�R/WData TLB Translate registers Way 111024-1151DTLBW2MR0-DTLBW2MR127�R/WData TLB Match registers Way 211152-1279DTLBW2TR0-DTLBW2TR127�R/WData TLB Translate registers Way 211280-1407DTLBW3MR0-DTLBW3MR127�R/WData TLB Match registers Way 311408-1535DTLBW3TR0-DTLBW3TR127�R/WData TLB Translate registers Way 320IMMUCR�R/WInstruction MMU Control register21IMMUPR�R/WInstruction MMU Protection Register22ITLBEIR�WInstruction TLB Entry Invalidate register24-7IATBMR0-IATBMR3�R/WInstruction ATB Match registers28-11IATBTR0-IATBTR3�R/WInstruction ATB Translate registers2512-639ITLBW0MR0-ITLBW0MR127�R/WInstruction TLB Match registers Way 02640-767ITLBW0TR0-ITLBW0TR127�R/WInstruction TLB Translate registers Way 02768-895ITLBW1MR0-ITLBW1MR127�R/WInstruction TLB Match registers Way 12896-1023ITLBW1TR0-ITLBW1TR127�R/WInstruction TLB Translate registers Way 121024-1151ITLBW2MR0-ITLBW2MR127�R/WInstruction TLB Match registers Way 221152-1279ITLBW2TR0-
ITLBW2TR127�R/WInstruction TLB Translate registers Way 221280-1407ITLBW3MR0-ITLBW3MR127�R/WInstruction TLB Match registers Way 321408-1535ITLBW3TR0-ITLBW3TR127�R/WInstruction TLB Translate registers Way 330DCCR�R/WDC Control register31DCBPRWWDC Block Prefetch register32DCBFRWWDC Block Flush register33DCBIR�WDC Block Invalidate register34DCBWRWWDC Block Write-back register35DCBLRWWDC Block Lock register40ICCR�R/WIC Control register41ICBPRWWIC Block Prefetch register42ICBIR�WIC Block Invalidate register43ICBLRWWIC Block Lock register51MACLOR/WR/WMAC Low52MACHIR/WR/WMAC High60-7DVR0-DVR7�R/WDebug Value registers68-15DCR0-DCR7�R/WDebug Control registers616DMR1�R/WDebug Mode register 1617DMR2�R/WDebug Mode register 2618-19DCWR0-DCWR1�R/WDebug Watchpoint Counter registers620DSR�R/WDebug Stop register621DRR�R/WDebug Reason register70-7PCCR0-PCCR7R*R/WPerformance Counters Count registers78-15PCMR0-PCMR7�R/WPerformance Counters Mode registers80PMR�R/WPower Management register90PICMR�R/WPIC Mask register92PICSR�R/WPIC Status register100TTMR�R/WTick Timer Mode register101TTCRR*R/WTick Timer Count registerTable  STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 2. List of All Special-Purpose Registers

SPRs with R* for user mode access are readable in user mode if SR[SUMRA] is set.

General-Purpose Registers (GPRs)
The thirty-two general-purpose registers are labeled R0-R31 and are 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementations. They hold scalar integer data, floting-point data, vectors or memory pointers.  REF _Ref478990852 \h 
 \* MERGEFORMAT Table 43 contains a list of general-purpose registers. The GPRs may be accessed as both source and destination registers by ORBIS, ORVDX and ORFPX instructions.
See chapter  REF _Ref509591491 \h 
Application Binary Interface on page  PAGEREF _Ref506705387 \h 
324 for information on floating-point data types.

Registerr31r30RegisterR29R28r27r26r25r24RegisterR23R22r21r20r19r18RegisterR17R16r15r14r13r12RegisterR11r10r9r8r7r6RegisterR5r4r3r2r1r0Table  STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 3. General-Purpose Registers

R0 is used as a constant zero. Whether or not R0 is actually hardwired to zero is implementation dependent. R0 should never be used as a destination register. Functions of other registers are explained in chapter  REF _Ref509591491 \h 
Application Binary Interfaceon page  PAGEREF _Ref506705387 \h 
324.
An implementation may have several sets of GPRs and use them as shadow registers, switching between them whenever a new exception occurs. The current set is identified by the SR[CID] value.
An implementation is not required to initialize GPRs to zero during the reset procedure. The reset exception handler is responsible for initializing GPRs to zero if that is necessary.

Support for Custom Number of GPRs
Programs may be compiled with less than thirty-two registers. Unused registers are disabled (set as fixed registers) when compiling code. Such code is also executable on normal implementations with thirty-two registers but not vice versa. This feature is quite useful since users are expected to move from less powerful OpenRISC implementations with less than thirty-two registers to more powerful thirty-two register OpenRISC implementations.
If configuration registers are implemented, CPUCFGR[CGF] indicates whether implementation has complete thirty-two general-purpose registers or less than thirty-two registers.

Supervision Register (SR)
The Supervison register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode only.
The SR value defines the state of the processor.

Bit31-2827-1716IdentifierCIDReservedSUMRAReset000R/WR/WRead OnlyR/W
Bit15141312111098IdentifierFOEPHDSXOVEOVCYFCEReset10000000R/WR/WR/WR/WR/WR/WR/WR/WR/W
Bit76543210IdentifierLEEIMEDMEICEDCEIEETEESMReset00000001R/WR/WR/WR/WR/WR/WR/WR/WR/W
SMSupervisor Mode
0 Processor is in User Mode
1 Processor is in Supervisor ModeTEETick Timer Exception Enabled
0 Tick Timer Exceptions are not recognized
1 Tick Timer Exceptions are recognizedIEEInterrupt Exception Enabled
0 Interrupts are not recognized
1 Interrupts are recognizedDCEData Cache Enable
0 Data Cache is not enabled
1 Data Cache is enabledICEInstruction Cache Enable
0 Instruction Cache is not enabled
1 Instruction Cache is enabledDMEData MMU Enable
0 Data MMU is not enabled
1 Data MMU is enabledIMEInstruction MMU Enable
0 Instruction MMU is not enabled
1 Instruction MMU is enabledLEELittle Endian Enable
0 Little Endian (LSB) byte ordering is not enabled
1 Little Endian (LSB) byte ordering is enabledCECID Enable
0 CID disabled and shadow registers disabled
1 CID automatic increment and shadow registers enabledFFlag
0 Conditional branch flag was cleared by sfXX instructions
1 Conditional branch flag was set by sfXX instructionsCYCarry flag
0 No carry out produced by last arithmetic operation
1 Carry out was produced by last arithmetic operationOVOverflow flag
0 No overflow occured during last arithmetic operation
1 Overflow occured during last arithmetic operationOVEOverflow flag Exception
0 Overflow flag does not cause an exception
1 Overflow flag causes range exceptionDSXDelay Slot Exception
0 EPCR points to instruction not in the delay slot
1 EPCR points to instruction in delay slotEPHException Prefix High
0 Exceptions vectors are located in memory area starting at 0x0
1 Exception vectors are located in memory area starting at 0xF0000000FOFixed One
This bit is always setSUMRASPRs User Mode Read Access
0 All SPRs are inaccessible in user mode
1 Certain SPRs can be read in user modeCIDContext ID (optional)
0-15 Current Processor ContextTable  STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 4. SR Field Descriptions

Exception Program Counter Registers (EPCR0 - EPCR15)
The Exception Program Counter registers are special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode. Read access in user mode is possible if it is enabled in PCMRx[SUMRA]. They are 32-bit wide registers in 32-bit implementations and can be wider than 32 bits in 64-bit implementations.
After an exception, the EPCR is set to the program counter address (PC) of the instruction that was interrupted by the exception. If only one EPCR is present in the implementation, it must be saved by the exception handler routine before exception recognition is re-enabled in the SR.

Bit31-0IdentifierEPCReset0R/WR/W
EPCException Program Counter AddressTable  STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 5. EPCR Field Descriptions

Exception Effective Address Registers (EEAR0-EEAR15)
The Exception Effective Address registers are special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode. Read access in user mode is possible if it is enabled in SR[SUMRA]. The EEARs are 32-bit wide registers in 32-bit implementations and can be wider than 32 bits in 64-bit implementations.
After an exception, the EEAR is set to the effective address (EA) generated by the faulting instruction. If only one EEAR is present in the implementation, it must be saved by the exception handler routine before exception recognition is re-enabled in the SR.

Bit31-0IdentifierEEAReset0R/WR/W
EEAException Effective AddressTable  STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 6. EEAR Field Descriptions

  Exception Supervision Registers                   (ESR0-ESR15)
The Exception Supervision registers are special-purpose supervisor-level registers accessible with l.mtspr/l.mfspr instructions in supervisor mode. They are 32 bits wide registers in 32-bit implementations and can be wider than 32 bits in 64-bit implementations.
After an exception, the Supervision register (SR) is copied into the ESR. If only one ESR is present in the implementation, it must be saved by the exception handler routine before exception recognition is re-enabled in the SR.

Bit31-0IdentifierESRReset0R/WR/W
EEAException SRTable  STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 7. ESR Field Descriptions

  Next and Previous Program Counter(NPC and PPC)
The Program Counter registers represent the address just executed and the address instruction just to be executed. 
These and the GPR registers mapped into SPR space should only be used for debugging purposes by an external debugger. Applications should use the l.jal instruction to obtain the current program counter and arithmethic instructions to obtain GPR register values.
Floating Point Control Status Register (FPCSR)
Floating point control status register is a 32-bit special-purpose register accessible with the l.mtspr/l.mfspr instructions in supervisor mode and as read-only register in user mode if enabled in SR[SUMRA].
The FPCSR value controls floating point rounding modes, optional generation of floating point exception and provides floating point status flags. Status flags are updated after every floating point instruction is completed and can serve to determine what caused the floating point exception.
If floating point exception is enabled then FPCSR status flags have to be cleared in floating point exception handler.  Status flags are cleared by writing 0 to all status bits.

Bit31-12111098IdentifierReservedDZFINFIVFIXFReset00000R/WRead OnlyR/WR/WR/WR/W
Bit765432-10IdentifierZFQNFSNFUNFOVFRMFPEEReset0000000R/WR/WR/WR/WR/WR/WR/WR/W
FPEEFloating Point Exception Enabled
0 FP Exception is disabled
1 FP Exception is enabledRMRounding Mode
0 Round to nearest
1 Round to zero
2 Round to infinity+
3 Round to infinity-OVFOVerflow Flag
0 No overflow
1 Result overflowedUNFUNderflow Flag
0 No underflow
1 Result underflowedSNFSNAN Flag
0 Result not SNAN
1 Result SNANQNFQNAN Flag
0 Result not QNAN
1 Result QNANZFZero Flag
0 Result not zero
1 Result zeroIXFIneXact Flag
0 Result precise
1 Result inexactIVFInaValid Flag
0 Result valid
1 Result invalidINFINfinity Flag
0 Result finite
1 Result infiniteDZFDivide by Zero Flag
0 Proper divide
1 Divide by zeroTable  STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 8. FPCSR Field Descriptions


Instruction Set
This chapter describes the OpenRISC 1000 instruction set.
Features
The OpenRISC 1000 instruction set includes the following principal features:
Simple and uniform-length instruction formats featuring five Instruction Subsets
OpenRISC Basic Instruction Set (ORBIS32/64) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 32-bit and 64-bit data
OpenRISC Vector/DSP eXtension (ORVDX64) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 8-, 16-, 32- and 64-bit data
OpenRISC Floating-Point eXtension (ORFPX32/64) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 32-bit and 64-bit data
Reserved opcodes for custom instructions
Note: Instructions are divided into instruction classes. Only the basic classes are required to be implemented in an OpenRISC 1000 implementation.

Figure  STYLEREF 1 \s 5 SEQ Figure \* ARABIC \s 1 1. Instruction Set

Overview
OpenRISC 1000 instructions belong to one of the following instruction subsets:
ORBIS32:
32-bit integer instructions
Basic DSP instructions
32-bit load and store instructions
Program flow instructions
Special instructions
ORBIS64:
64-bit integer instructions
64-bit load and store instructions
ORFPX32:
Single-precision floating-point instructions
ORFPX64:
Double-precision floating-point instructions
64-bit load and store instructions
ORVDX64:
Vector instructions
DSP instructions

Instructions in each subset are also split into two instruction classes according to implementation importance:
Class I
Class II

ClassDescriptionIInstructions in class I must always be implemented.IIInstructions from class II are optional and an implementation may choose to use some or all instructions from this class based on requirements of the target application.Table  STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 1. OpenRISC 1000 Instruction Classes

ORBIS32/64
Format: 
l.add�rD,rA,rB 
Description: 
The contents of general-purpose register rA are added to the contents of general-purpose register rB to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] + rB[31:0]SR[CY] < - carrySR[OV] < - overflow 
64-bit Implementation: 
rD[63:0] < - rA[63:0] + rB[63:0]SR[CY] < - carrySR[OV] < - overflow 
Exceptions: 
Range Exception 

Format: 
l.addc�rD,rA,rB 
Description: 
The contents of general-purpose register rA are added to the contents of general-purpose register rB and carry SR[CY] to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] + rB[31:0] + SR[CY]SR[CY] < - carrySR[OV] < - overflow 
64-bit Implementation: 
rD[63:0] < - rA[63:0] + rB[63:0] + SR[CY]SR[CY] < - carrySR[OV] < - overflow 
Exceptions: 
Range Exception 

Format: 
l.addi�rD,rA,I 
Description: 
The immediate value is sign-extended and added to the contents of general-purposeregister rA to form the result. The result is placed into general-purposeregister rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] + exts(Immediate)SR[CY] < - carrySR[OV] < - overflow 
64-bit Implementation: 
rD[63:0] < - rA[63:0] + exts(Immediate)SR[CY] < - carrySR[OV] < - overflow 
Exceptions: 
Range Exception 

Format: 
l.addic�rD,rA,I 
Description: 
The immediate value is sign-extended and added to the contents of general-purposeregister rA and carry SR[CY] to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] + exts(Immediate) + SR[CY]SR[CY] < - carrySR[OV] < - overflow 
64-bit Implementation: 
rD[63:0] < - rA[63:0] + exts(Immediate) + SR[CY]SR[CY] < - carrySR[OV] < - overflow 
Exceptions: 
Range Exception 

Format: 
l.and�rD,rA,rB 
Description: 
The contents of general-purpose register rA are combined with the contents of general-purpose register rB in a bit-wise logical AND operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] AND rB[31:0] 
64-bit Implementation: 
rD[63:0] < - rA[63:0] AND rB[63:0] 
Exceptions: 
None 

Format: 
l.andi�rD,rA,K 
Description: 
The immediate value is zero-extended and combined with the contents of general-purpose register rA in a bit-wise logical AND operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] AND extz(Immediate) 
64-bit Implementation: 
rD[63:0] < - rA[63:0] AND extz(Immediate) 
Exceptions: 
None 

Format: 
l.bf�N 
Description: 
The immediate value is shifted left two bits, sign-extended to program counter width, and then added to the address of the branch instruction. The result is the effective address of the branch. If the flag is set, the program branches to EA with a delay of one instruction. 
32-bit Implementation: 
EA < - exts(Immediate < < 2) + BranchInsnAddrPC < - EA if SR[F] set 
64-bit Implementation: 
EA < - exts(Immediate < < 2) + BranchInsnAddrPC < - EA if SR[F] set 
Exceptions: 
None 

Format: 
l.bnf�N 
Description: 
The immediate value is shifted left two bits, sign-extended to program counter width, and then added to the address of the branch instruction. The result is the effective address of the branch. If the flag is cleared, the program branches to EA with a delay of one instruction. 
32-bit Implementation: 
EA < - exts(Immediate < < 2) + BranchInsnAddrPC < - EA if SR[F] cleared 
64-bit Implementation: 
EA < - exts(Immediate < < 2) + BranchInsnAddrPC < - EA if SR[F] cleared 
Exceptions: 
None 

Format: 
l.cmov�rD,rA,rB 
Description: 
If SR[F] is set, general-purpose register rA is placed in general-purpose register rD. If SR[F] is cleared, general-purpose register rB is placed in general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - SR[F] ? rA[31:0] : rB[31:0] 
64-bit Implementation: 
rD[63:0] < - SR[F] ? rA[63:0] : rB[63:0] 
Exceptions: 
None 

Format: 
l.csync� 
Description: 
Execution of context synchronization instruction results in completion of all operations inside the processor and a flush of the instruction pipelines. When all operations are complete, the RISC core resumes with an empty instruction pipeline and fresh context in all units (MMU for example). 
32-bit Implementation: 
context-synchronization 
64-bit Implementation: 
context-synchronization 
Exceptions: 
None 

Format: 
l.cust1� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but rather by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
l.cust2� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but rather by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
l.cust3� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but rather by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
l.cust4� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but rather by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
l.cust5�rD,rA,rB,L,K 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but rather by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
l.cust6� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but rather by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
l.cust7� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but rather by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
l.cust8� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but rather by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
l.div�rD,rA,rB 
Description: 
The content of general-purpose register rA are divided by the content of general-purpose register rB, and the result is placed into general-purpose register rD. Both operands are treated as signed integers. A carry flag is set when the divisor is zero (if carry SR[CY] is implemented). 
32-bit Implementation: 
rD[31:0] < - rA[31:0] / rB[31:0]SR[OV] < - overflowSR[CY] < - carry 
64-bit Implementation: 
rD[63:0] < - rA[63:0] / rB[63:0]SR[OV] < - overflowSR[CY] < - carry 
Exceptions: 
Range Exception 

Format: 
l.divu�rD,rA,rB 
Description: 
The content of general-purpose register rA are divided by the content of general-purpose register rB, and the result is placed into general-purpose register rD. Both operands are treated as unsigned integers. A carry flag is set when the divisor is zero (if carry SR[CY] is implemented). 
32-bit Implementation: 
rD[31:0] < - rA[31:0] / rB[31:0]SR[OV] < - overflowSR[CY] < - carry 
64-bit Implementation: 
rD[63:0] < - rA[63:0] / rB[63:0]SR[OV] < - overflowSR[CY] < - carry 
Exceptions: 
Range Exception 

Format: 
l.extbs�rD,rA 
Description: 
Bit 7 of general-purpose register rA is placed in high-order bits of general-purpose register rD. The low-order eight bits of general-purpose register rA are copied into the low-order eight bits of general-purpose register rD. 
32-bit Implementation: 
rD[31:8] < - rA[7]rD[7:0] < - rA[7:0] 
64-bit Implementation: 
rD[63:8] < - rA[7]rD[7:0] < - rA[7:0] 
Exceptions: 
None 

Format: 
l.extbz�rD,rA 
Description: 
Zero is placed in high-order bits of general-purpose register rD. The low-order eight bits of general-purpose register rA are copied into the low-order eight bits of general-purpose register rD. 
32-bit Implementation: 
rD[31:8] < - 0rD[7:0] < - rA[7:0] 
64-bit Implementation: 
rD[63:8] < - 0rD[7:0] < - rA[7:0] 
Exceptions: 
None 

Format: 
l.exths�rD,rA 
Description: 
Bit 15 of general-purpose register rA is placed in high-order bits of general-purpose register rD. The low-order 16 bits of general-purpose register rA are copied into the low-order 16 bits of general-purpose register rD. 
32-bit Implementation: 
rD[31:16] < - rA[15]rD[15:0] < - rA[15:0] 
64-bit Implementation: 
rD[63:16] < - rA[15]rD[15:0] < - rA[15:0] 
Exceptions: 
None 

Format: 
l.exthz�rD,rA 
Description: 
Zero is placed in high-order bits of general-purpose register rD. The low-order 16 bits of general-purpose register rA are copied into the low-order 16 bits of general-purpose register rD. 
32-bit Implementation: 
rD[31:16] < - 0rD[15:0] < - rA[15:0] 
64-bit Implementation: 
rD[63:16] < - 0rD[15:0] < - rA[15:0] 
Exceptions: 
None 

Format: 
l.extws�rD,rA 
Description: 
Bit 31 of general-purpose register rA is placed in high-order bits of general-purpose register rD. The low-order 32 bits of general-purpose register rA are copied from low-order 32 bits of general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] 
64-bit Implementation: 
rD[63:32] < - rA[31]rD[31:0] < - rA[31:0] 
Exceptions: 
None 

Format: 
l.extwz�rD,rA 
Description: 
Zero is placed in high-order bits of general-purpose register rD. The low-order 32 bits of general-purpose register rA are copied into the low-order 32 bits of general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] 
64-bit Implementation: 
rD[63:32] < - 0rD[31:0] < - rA[31:0] 
Exceptions: 
None 

Format: 
l.ff1�rD,rA,rB 
Description: 
Position of the first '1' bit is written into general-purpose register rD. Checking for bit '1' starts with bit 0 (LSB), and counting is incremented for every zero bit. If first '1' bit is discovered in LSB, one is written into rD, if first �1� bit is discovered in MSB, 32 is written into rD. If there is no '1' bit, zero is written in rD. 
32-bit Implementation: 
rD[31:0] < - rA[0] ? 1 : rA[1] ? 2 ... rA[31] ? 32 : 0 
64-bit Implementation: 
rD[63:0] < - rA[0] ? 1 : rA[1] ? 2 ... rA[63] ? 64 : 0 
Exceptions: 
None 


Format: 
l.fl1�rD,rA,rB 
Description: 
Position of the last '1' bit is written into general-purpose register rD. Checking for bit '1' starts with bit 0 (LSB), and counting is inccremented for every zero bit until the last �1� bit is found nearing the MSB. If first '1' bit is discovered in bit 32(64) MSB, 32 (64) is written into rD, if first �1� bit is discovered in LSB, one is written into rD. If there is no '1' bit, zero is written in rD. 
32-bit Implementation: 
rD[31:0] < - rA[31] ? 32 : rA[30] ? 31 ... rA[0] ? 1 : 0 
64-bit Implementation: 
rD[63:0] < - rA[63] ? 64 : rA[62] ? 63 ... rA[0] ? 1 : 0 
Exceptions: 
None 

Format: 
l.j�N 
Description: 
The immediate value is shifted left two bits, sign-extended to program counter width, and then added to the address of the jump instruction. The result is the effective address of the jump. The program unconditionally jumps to EA with a delay of one instruction. 
32-bit Implementation: 
PC < - exts(Immediate < < 2) + JumpInsnAddr 
64-bit Implementation: 
PC < - exts(Immediate < < 2) + JumpInsnAddr 
Exceptions: 
None 

Format: 
l.jal�N 
Description: 
The immediate value is shifted left two bits, sign-extended to program counter width, and then added to the address of the jump instruction. The result is the effective address of the jump. The program unconditionally jumps to EA with a delay of one instruction. The address of the instruction after the delay slot is placed in the link register. 
32-bit Implementation: 
PC < - exts(Immediate < < 2) + JumpInsnAddrLR < - DelayInsnAddr + 4 
64-bit Implementation: 
PC < - exts(Immediate < < 2) + JumpInsnAddrLR < - DelayInsnAddr + 4 
Exceptions: 
None 

Format: 
l.jalr�rB 
Description: 
The contents of general-purpose register rB is the effective address of the jump. The program unconditionally jumps to EA with a delay of one instruction. The address of the instruction after the delay slot is placed in the link register. It is not allowed to specify link register as rB. 
32-bit Implementation: 
PC < - rBLR < - DelayInsnAddr + 4 
64-bit Implementation: 
PC < - rBLR < - DelayInsnAddr + 4 
Exceptions: 
None 

Format: 
l.jr�rB 
Description: 
The contents of general-purpose register rB is the effective address of the jump. The program unconditionally jumps to EA with a delay of one instruction. 
32-bit Implementation: 
PC < - rB 
64-bit Implementation: 
PC < - rB 
Exceptions: 
None 

Format: 
l.lbs�rD,I(rA) 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The byte in memory addressed by EA is loaded into the low-order eight bits of general-purpose register rD. High-order bits of general-purpose register rD are replaced with bit 7 of the loaded value. 
32-bit Implementation: 
EA < - exts(Immediate) + rA[31:0]rD[7:0] < - (EA)[7:0]rD[31:8] < - (EA)[7] 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0]rD[7:0] < - (EA)[7:0]rD[63:8] < - (EA)[7] 
Exceptions: 
TLB missPage faultBus error 

Format: 
l.lbz�rD,I(rA) 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The byte in memory addressed by EA is loaded into the low-order eight bits of general-purpose register rD. High-order bits of general-purpose register rD are replaced with zero. 
32-bit Implementation: 
EA < - exts(Immediate) + rA[31:0]rD[7:0] < - (EA)[7:0]rD[31:8] < - 0 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0]rD[7:0] < - (EA)[7:0]rD[63:8] < - 0 
Exceptions: 
TLB missPage faultBus error 

Format: 
l.ld�rD,I(rA) 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The double word in memory addressed by EA is loaded into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0]rD[63:0] < - (EA)[63:0] 
Exceptions: 
TLB missPage faultBus errorAlignment 

Format: 
l.lhs�rD,I(rA) 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The half word in memory addressed by EA is loaded into the low-order 16 bits of general-purpose register rD. High-order bits of general-purpose register rD are replaced with bit 15 of the loaded value. 
32-bit Implementation: 
EA < - exts(Immediate) + rA[31:0]rD[15:0] < - (EA)[15:0]rD[31:16] < - (EA)[15] 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0]rD[15:0] < - (EA)[15:0]rD[63:16] < - (EA)[15] 
Exceptions: 
TLB missPage faultBus errorAlignment 

Format: 
l.lhz�rD,I(rA) 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The half word in memory addressed by EA is loaded into the low-order 16 bits of general-purpose register rD. High-order bits of general-purpose register rD are replaced with zero. 
32-bit Implementation: 
EA < - exts(Immediate) + rA[31:0]rD[15:0] < - (EA)[15:0]rD[31:16] < - 0 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0]rD[15:0] < - (EA)[15:0]rD[63:16] < - 0 
Exceptions: 
TLB missPage faultBus errorAlignment 

Format: 
l.lws�rD,I(rA) 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The single word in memory addressed by EA is loaded into the low-order 32 bits of general-purpose register rD. High-order bits of general-purpose register rD are replaced with bit 31 of the loaded value. 
32-bit Implementation: 
EA < - exts(Immediate) + rA[31:0]rD[31:0] < - (EA)[31:0] 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0]rD[31:0] < - (EA)[31:0]rD[63:32] < - (EA)[31] 
Exceptions: 
TLB missPage faultBus errorAlignment 

Format: 
l.lwz�rD,I(rA) 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The single word in memory addressed by EA is loaded into the low-order 32 bits of general-purpose register rD. High-order bits of general-purpose register rD are replaced with zero. 
32-bit Implementation: 
EA < - exts(Immediate) + rA[31:0]rD[31:0] < - (EA)[31:0] 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0]rD[31:0] < - (EA)[31:0]rD[63:32] < - 0 
Exceptions: 
TLB missPage faultBus errorAlignment 

Format: 
l.mac�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are multiplied, and the result is truncated to 32 bits and added to the special-purpose registers MACHI and MACLO. All operands are treated as signed integers. 
32-bit Implementation: 
temp[31:0] < - rA[31:0] * rB[31:0]MACHI[31:0]MACLO[31:0] < - temp[31:0] + MACHI[31:0]MACLO[31:0]
64-bit Implementation: 
temp[31:0] < - rA[63:0] * rB[63:0]MACHI[31:0]MACLO[31:0] < - temp[31:0] + MACHI[31:0]MACLO[31:0]
Exceptions: 
None 

Format: 
l.maci�rA,I 
Description: 
The immediate value and the contents of general-purpose register rA are multiplied, and the result is truncated to 32 bits and added to the special-purpose registers MACHI and MACLO. All operands are treated as signed integers. 
32-bit Implementation: 
temp[31:0] < - rA[31:0] * exts(Immediate)MACHI[31:0]MACLO[31:0] < - temp[31:0] + MACHI[31:0]MACLO[31:0]
64-bit Implementation: 
temp[31:0] < - rA[63:0] * exts(Immediate)MACHI[31:0]MACLO[31:0] < - temp[31:0] + MACHI[31:0]MACLO[31:0]
Exceptions: 
None 

Format: 
l.macrc�rD 
Description: 
Once all instructions in MAC pipeline are completed, the contents of MAC is placed into general-purpose register rD and MAC accumulator is cleared. 
32-bit Implementation: 
synchronize-macrD[31:0] < - MACLO[31:0]
MACLO[31:0], MACHI[31:0] <- 0
64-bit Implementation: 
synchronize-macrD[63:0] < - MACHI[31:0]MACLO[31:0]
MACLO[31:0], MACHI[31:0] <- 0
Exceptions: 
None 

Format: 
l.mfspr�rD,rA,K 
Description: 
The contents of the special register, defined by contents of general-purpose rA logically ORed with immediate value, are moved into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - spr(rA OR Immediate) 
64-bit Implementation: 
rD[63:0] < - spr(rA OR Immediate) 
Exceptions: 
None 

Format: 
l.movhi�rD,K 
Description: 
The 16-bit immediate value is zero-extended, shifted left by 16 bits, and placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - extz(Immediate) < < 16 
64-bit Implementation: 
rD[63:0] < - extz(Immediate) < < 16 
Exceptions: 
None 

Format: 
l.msb�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are multiplied, and the result is truncated to 32 bits and subtracted from the special-purpose registers MACHI and MACLO. Result of the subtraction is placed into MACHI and MACLO registers.All operands are treated as signed integers. 
32-bit Implementation: 
temp[31:0] < - rA[31:0] * rB[31:0]MACHI[31:0]MACLO[31:0] < - MACHI[31:0]MACLO[31:0] - temp[31:0]
64-bit Implementation: 
temp[31:0] < - rA[63:0] * rB[63:0]MACHI[31:0]MACLO[31:0] < - MACHI[31:0]MACLO[31:0] - temp[31:0]
Exceptions: 
None 

Format: 
l.msync� 
Description: 
Execution of the memory synchronization instruction results in completion of all load/store operations before the RISC core continues. 
32-bit Implementation: 
memory-synchronization 
64-bit Implementation: 
memory-synchronization 
Exceptions: 
None 

Format: 
l.mtspr�rA,rB,K 
Description: 
The contents of general-purpose register rB are moved into the special register defined by contents of general-purpose register rA logically ORed with the immediate value. 
32-bit Implementation: 
spr(rA OR Immediate) < - rB[31:0] 
64-bit Implementation: 
spr(rA OR Immediate) < - rB[31:0] 
Exceptions: 
None 

Format: 
l.mul�rD,rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are multiplied, and the result is truncated to destination register width and placed into general-purpose register rD. Both operands are treated as signed integers. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] * rB[31:0]SR[OV] < - overflowSR[CY] < - carry 
64-bit Implementation: 
rD[63:0] < - rA[63:0] * rB[63:0]SR[OV] < - overflowSR[CY] < - carry 
Exceptions: 
Range Exception 

Format: 
l.muli�rD,rA,I 
Description: 
The immediate value and the contents of general-purpose register rA are multiplied, and the result is truncated to destination register width and placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] * ImmediateSR[OV] < - overflowSR[CY] < - carry 
64-bit Implementation: 
rD[63:0] < - rA[63:0] * ImmediateSR[OV] < - overflowSR[CY] < - carry 
Exceptions: 
Range Exception 

Format: 
l.mulu�rD,rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are multiplied, and the result is truncated to destination register width and placed into general-purpose register rD. Both operands are treated as unsigned integers. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] * rB[31:0]SR[OV] < - overflowSR[CY] < - carry 
64-bit Implementation: 
rD[63:0] < - rA[63:0] * rB[63:0]SR[OV] < - overflowSR[CY] < - carry 
Exceptions: 
Range Exception 

Format: 
l.nop�K 
Description: 
This instruction does not do anything except that it takes at least one clock cycle to complete. It is often used to fill delay slot gaps.Immediate value can be used for simulation purposes. 
32-bit Implementation: 

64-bit Implementation: 

Exceptions: 
None 

Format: 
l.or�rD,rA,rB 
Description: 
The contents of general-purpose register rA are combined with the contents of general-purpose register rB in a bit-wise logical OR operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] OR rB[31:0] 
64-bit Implementation: 
rD[63:0] < - rA[63:0] OR rB[63:0] 
Exceptions: 
None 

Format: 
l.ori�rD,rA,K 
Description: 
The immediate value is zero-extended and combined with the contents of general-purpose register rA in a bit-wise logical OR operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] OR extz(Immediate) 
64-bit Implementation: 
rD[63:0] < - rA[63:0] OR extz(Immediate) 
Exceptions: 
None 

Format: 
l.psync� 
Description: 
Execution of pipeline synchronization instruction results in completion of all instructions that were fetched before l.psync instruction. Once all instructions are completed, instructions fetched after l.psync are flushed from the pipeline and fetched again. 
32-bit Implementation: 
pipeline-synchronization 
64-bit Implementation: 
pipeline-synchronization 
Exceptions: 
None 

Format: 
l.rfe� 
Description: 
Execution of this instruction partially restores the state of the processor prior to the exception. This instruction does not have a delay slot. 
32-bit Implementation: 
PC < - EPCRSR < - ESR 
64-bit Implementation: 
PC < - EPCRSR < - ESR 
Exceptions: 
None 

Format: 
l.ror�rD,rA,rB 
Description: 
General-purpose register rB specifies the number of bit positions; the contents of general-purpose register rA are rotated right. The result is written into general-purpose register rD. In 32-bit implementations bit 5 of rB is ignored. 
32-bit Implementation: 
rD[31-rB[4:0]:0] < - rA[31:rB]rD[31:32-rB[4:0]] < - rA[rB[4:0]-1:0] 
64-bit Implementation: 
rD[63-rB[5:0]:0] < - rA[63:rB]rD[63:64-rB[5:0]] < - rA[rB[5:0]-1:0] 
Exceptions: 
None 

Format: 
l.rori�rD,rA,L 
Description: 
The 6-bit immediate value specifies the number of bit positions; the contents of general-purpose register rA are rotated right. The result is written into general-purpose register rD. In 32-bit implementations bit 5 of immediate is ignored. 
32-bit Implementation: 
rD[31-L:0] < - rA[31:L]rD[31:32-L] < - rA[L-1:0] 
64-bit Implementation: 
rD[63-L:0] < - rA[63:L]rD[63:64-L] < - rA[L-1:0] 
Exceptions: 
None 

Format: 
l.sb�I(rA),rB 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The low-order 8 bits of general-purpose register rB are stored to memory location addressed by EA. 
32-bit Implementation: 
EA < - exts(Immediate) + rA[31:0](EA)[7:0] < - rB[7:0] 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0](EA)[7:0] < - rB[7:0] 
Exceptions: 
TLB missPage faultBus error 

Format: 
l.sd�I(rA),rB 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The double word in general-purpose register rB is stored to memory location addressed by EA. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0](EA)[63:0] < - rB[63:0] 
Exceptions: 
TLB missPage faultBus errorAlignment 

Format: 
l.sfeq�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared. If the contents are equal, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] == rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] == rB[63:0] 
Exceptions: 
None 

Format: 
l.sfeqi�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared. If the two values are equal, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] == exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] == exts(Immediate) 
Exceptions: 
None 

Format: 
l.sfges�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared as signed integers. If the contents of the first register are greater than or equal to the contents of the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] >= rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] >= rB[63:0] 
Exceptions: 
None 

Format: 
l.sfgesi�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared as signed integers. If the contents of the first register are greater than or equal to the immediate value the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] >= exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] >= exts(Immediate) 
Exceptions: 
None 

Format: 
l.sfgeu�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared as unsigned integers. If the contents of the first register are greater than or equal to the contents of the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] >= rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] >= rB[63:0] 
Exceptions: 
None 

Format: 
l.sfgeui�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared as unsigned integers. If the contents of the first register are greater than or equal to the immediate value the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] >= exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] >= exts(Immediate) 
Exceptions: 
None 

Format: 
l.sfgts�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared as signed integers. If the contents of the first register are greater than the contents of the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] > rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] > rB[63:0] 
Exceptions: 
None 

Format: 
l.sfgtsi�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared as signed integers. If the contents of the first register are greater than the immediate value the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] > exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] > exts(Immediate) 
Exceptions: 
None 

Format: 
l.sfgtu�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared as unsigned integers. If the contents of the first register are greater than the contents of the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] > rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] > rB[63:0] 
Exceptions: 
None 

Format: 
l.sfgtui�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared as unsigned integers. If the contents of the first register are greater than the immediate value the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] > exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] > exts(Immediate) 
Exceptions: 
None 

Format: 
l.sfles�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared as signed integers. If the contents of the first register are less than or equal to the contents of the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < = rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] < = rB[63:0] 
Exceptions: 
None 

Format: 
l.sflesi�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared as signed integers. If the contents of the first register are less than or equal to the immediate value the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < = exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] < = exts(Immediate) 
Exceptions: 
None 

Format: 
l.sfleu�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared as unsigned integers. If the contents of the first register are less than or equal to the contents of the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < = rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] < = rB[63:0] 
Exceptions: 
None 

Format: 
l.sfleui�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared as unsigned integers. If the contents of the first register are less than or equal to the immediate value the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < = exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] < = exts(Immediate) 
Exceptions: 
None 

Format: 
l.sflts�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared as signed integers. If the contents of the first register are less than the contents of the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] < rB[63:0] 
Exceptions: 
None 

Format: 
l.sfltsi�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared as signed integers. If the contents of the first register are less than the immediate value the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] < exts(Immediate) 
Exceptions: 
None 

Format: 
l.sfltu�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared as unsigned integers. If the contents of the first register are less than the contents of the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] < rB[63:0] 
Exceptions: 
None 

Format: 
l.sfltui�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared as unsigned integers. If the contents of the first register are less than the immediate value the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] < exts(Immediate) 
Exceptions: 
None 

Format: 
l.sfne�rA,rB 
Description: 
The contents of general-purpose registers rA and rB are compared. If the contents are not equal, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] != rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[63:0] != rB[63:0] 
Exceptions: 
None 

Format: 
l.sfnei�rA,I 
Description: 
The contents of general-purpose register rA and the sign-extended immediate value are compared. If the two values are not equal, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] != exts(Immediate) 
64-bit Implementation: 
SR[F] < - rA[63:0] != exts(Immediate) 
Exceptions: 
None 

Format: 
l.sh�I(rA),rB 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The low-order 16 bits of general-purpose register rB are stored to memory location addressed by EA. 
32-bit Implementation: 
EA < - exts(Immediate) + rA[31:0](EA)[15:0] < - rB[15:0] 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0](EA)[15:0] < - rB[15:0] 
Exceptions: 
TLB missPage faultBus errorAlignment 

Format: 
l.sll�rD,rA,rB 
Description: 
General-purpose register rB specifies the number of bit positions; the contents of general-purpose register rA are shifted left, inserting zeros into the low-order bits. The result is written into general-purpose rD. In 32-bit implementations bit 5 of rB is ignored. 
32-bit Implementation: 
rD[31:rB[4:0]] < - rA[31-rB[4:0]:0]rD[rB[4:0]-1:0] < - 0 
64-bit Implementation: 
rD[63:rB[5:0]] < - rA[63-rB[5:0]:0]rD[rB[5:0]-1:0] < - 0 
Exceptions: 
None 

Format: 
l.slli�rD,rA,L 
Description: 
The immediate value specifies the number of bit positions; the contents of general-purpose register rA are shifted left, inserting zeros into the low-order bits. The result is written into general-purpose register rD. In 32-bit implementations bit 5 of immediate is ignored. 
32-bit Implementation: 
rD[31:L] < - rA[31-L:0]rD[L-1:0] < - 0 
64-bit Implementation: 
rD[63:L] < - rA[63-L:0]rD[L-1:0] < - 0 
Exceptions: 
None 

Format: 
l.sra�rD,rA,rB 
Description: 
General-purpose register rB specifies the number of bit positions; the contents of general-purpose register rA are shifted right, sign-extending the high-order bits. The result is written into general-purpose register rD. In 32-bit implementations bit 5 of rB is ignored. 
32-bit Implementation: 
rD[31-rB[4:0]:0] < - rA[31:rB[4:0]]rD[31:32-rB[4:0]] < - rA[31] 
64-bit Implementation: 
rD[63-rB[5:0]:0] < - rA[63:rB[5:0]]rD[63:64-rB[5:0]] < - rA[63] 
Exceptions: 
None 

Format: 
l.srai�rD,rA,L 
Description: 
The 6-bit immediate value specifies the number of bit positions; the contents of general-purpose register rA are shifted right, sign-extending the high-order bits. The result is written into general-purpose register rD. In 32-bit implementations bit 5 of immediate is ignored. 
32-bit Implementation: 
rD[31-L:0] < - rA[31:L]rD[31:32-L] < - rA[31] 
64-bit Implementation: 
rD[63-L:0] < - rA[63:L]rD[63:64-L] < - rA[63] 
Exceptions: 
None 

Format: 
l.srl�rD,rA,rB 
Description: 
General-purpose register rB specifies the number of bit positions; the contents of general-purpose register rA are shifted right, inserting zeros into the high-order bits. The result is written into general-purpose register rD. In 32-bit implementations bit 5 of rB is ignored. 
32-bit Implementation: 
rD[31-rB[4:0]:0] < - rA[31:rB[4:0]]rD[31:32-rB[4:0]] < - 0 
64-bit Implementation: 
rD[63-rB[5:0]:0] < - rA[63:rB[5:0]]rD[63:64-rB[5:0]] < - 0 
Exceptions: 
None 

Format: 
l.srli�rD,rA,L 
Description: 
The 6-bit immediate value specifies the number of bit positions; the contents of general-purpose register rA are shifted right, inserting zeros into the high-order bits. The result is written into general-purpose register rD. In 32-bit implementations bit 5 of immediate is ignored. 
32-bit Implementation: 
rD[31-L:0] < - rA[31:L]rD[31:32-L] < - 0 
64-bit Implementation: 
rD[63-L:0] < - rA[63:L]rD[63:64-L] < - 0 
Exceptions: 
None 

Format: 
l.sub�rD,rA,rB 
Description: 
The contents of general-purpose register rB are subtracted from the contents of general-purpose register rA to form the result. The result is placed into general-purpose register rD. This isntruction does not change carry SR[CY] flag. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] - rB[31:0]SR[CY] < - carrySR[OV] < - overflow 
64-bit Implementation: 
rD[63:0] < - rA[63:0] - rB[63:0]SR[CY] < - carrySR[OV] < - overflow 
Exceptions: 
Range Exception 

Format: 
l.sw�I(rA),rB 
Description: 
The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The low-order 32 bits of general-purpose register rB are stored to memory location addressed by EA. 
32-bit Implementation: 
EA < - exts(Immediate) + rA[31:0](EA)[31:0] < - rB[31:0] 
64-bit Implementation: 
EA < - exts(Immediate) + rA[63:0](EA)[31:0] < - rB[31:0] 
Exceptions: 
TLB missPage faultBus errorAlignment 

Format: 
l.sys�K 
Description: 
Execution of the system call instruction results in the system call exception. The system calls exception is a request to the operating system to provide operating system services. The immediate value can be used to specify which system service is requested, alternatively a GPR defined by the ABI can be used to specify system service. 
32-bit Implementation: 
system-call-exception(K) 
64-bit Implementation: 
system-call-exception(K) 
Exceptions: 
System Call 

Format: 
l.trap�K 
Description: 
Execution of trap instruction results in the trap exception if specified bit in SR is set. Trap exception is a request to the operating system or to the debug facility to execute certain debug services. Immediate value is used to select which SR bit is tested by trap instruction. 
32-bit Implementation: 
if SR[K] = 1 then trap-exception() 
64-bit Implementation: 
if SR[K] = 1 then trap-exception() 
Exceptions: 
Trap exception 

Format: 
l.xor�rD,rA,rB 
Description: 
The contents of general-purpose register rA are combined with the contents of general-purpose register rB in a bit-wise logical XOR operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] XOR rB[31:0] 
64-bit Implementation: 
rD[63:0] < - rA[63:0] XOR rB[63:0] 
Exceptions: 
None 

Format: 
l.xori�rD,rA,I 
Description: 
The immediate value is sign-extended and combined with the contents of general-purpose register rA in a bit-wise logical XOR operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] XOR exts(Immediate) 
64-bit Implementation: 
rD[63:0] < - rA[63:0] XOR exts(Immediate) 
Exceptions: 
None 

Format: 
lf.add.d�rD,rA,rB 
Description: 
The contents of general-purpose register rA are added to the contents of general-purpose register rB to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] + rB[63:0] 
Exceptions: 
Floating Point 

Format: 
lf.add.s�rD,rA,rB 
Description: 
The contents of general-purpose register rA are added to the contents of general-purpose register rB to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] + rB[31:0] 
64-bit Implementation: 
rD[31:0] < - rA[31:0] + rB[31:0]rD[63:32] < - 0 
Exceptions: 
Floating Point 

Format: 
lf.cust1.d�rA,rB 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but instead by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
lf.cust1.s�rA,rB 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but instead by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
lf.div.d�rD,rA,rB 
Description: 
The contents of general-purpose register rA are divided by the contents of general-purpose register rB to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] / rB[63:0] 
Exceptions: 
Floating Point 

Format: 
lf.div.s�rD,rA,rB 
Description: 
The contents of general-purpose register rA are divided by the contents of general-purpose register rB to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] / rB[31:0] 
64-bit Implementation: 
rD[31:0] < - rA[31:0] / rB[31:0]rD[63:32] < - 0 
Exceptions: 
Floating Point 

Format: 
lf.ftoi.d�rD,rA 
Description: 
The contents of general-purpose register rA are converted to an integer and stored in general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - ftoi(rA[63:0]) 
Exceptions: 
Floating Point 

Format: 
lf.ftoi.s�rD,rA 
Description: 
The contents of general-purpose register rA are converted to an integer and stored into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - ftoi(rA[31:0]) 
64-bit Implementation: 
rD[31:0] < - ftoi(rA[31:0])rD[63:32] < - 0 
Exceptions: 
Floating Point 

Format: 
lf.itof.d�rD,rA 
Description: 
The contents of general-purpose register rA are converted to a double-precision floating-point number and stored in general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - itof(rA[63:0]) 
Exceptions: 
Floating Point 

Format: 
lf.itof.s�rD,rA 
Description: 
The contents of general-purpose register rA are converted to a single-precision floating-point number and stored into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - itof(rA[31:0]) 
64-bit Implementation: 
rD[31:0] < - itof(rA[31:0])rD[63:32] < - 0 
Exceptions: 
Floating Point 

Format: 
lf.madd.d�rD,rA,rB 
Description: 
The contents of general-purpose register rA are multiplied by the contents of general-purpose register rB, and added to special-purpose register FPMADDLO/FPMADDHI. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
FPMADDHI[31:0]FPMADDLO[31:0] < - rA[63:0] * rB[63:0] + FPMADDHI[31:0]FPMADDLO[31:0] 
Exceptions: 
Floating Point 

Format: 
lf.madd.s�rD,rA,rB 
Description: 
The contents of general-purpose register rA are multiplied by the contents of general-purpose register rB, and added to special-purpose register FPMADDLO/FPMADDHI. 
32-bit Implementation: 
FPMADDHI[31:0]FPMADDLO[31:0] < - rA[31:0] * rB[31:0] + FPMADDHI[31:0]FPMADDLO[31:0] 
64-bit Implementation: 
FPMADDHI[31:0]FPMADDLO[31:0] < - rA[31:0] * rB[31:0] + FPMADDHI[31:0]FPMADDLO[31:0]FPMADDHI < - 0FPMADDLO < - 0 
Exceptions: 
Floating Point 

Format: 
lf.mul.d�rD,rA,rB 
Description: 
The contents of general-purpose register rA are multiplied by the contents of general-purpose register rB to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] * rB[63:0] 
Exceptions: 
Floating Point 

Format: 
lf.mul.s�rD,rA,rB 
Description: 
The contents of general-purpose register rA are multiplied by the contents of general-purpose register rB to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] * rB[31:0] 
64-bit Implementation: 
rD[31:0] < - rA[31:0] * rB[31:0]rD[63:32] < - 0 
Exceptions: 
Floating Point 

Format: 
lf.rem.d�rD,rA,rB 
Description: 
The contents of general-purpose register rA are divided by the contents of general-purpose register rB, and remainder is used as the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] % rB[63:0] 
Exceptions: 
Floating Point 

Format: 
lf.rem.s�rD,rA,rB 
Description: 
The contents of general-purpose register rA are divided by the contents of general-purpose register rB, and remainder is used as the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] % rB[31:0] 
64-bit Implementation: 
rD[31:0] < - rA[31:0] % rB[31:0]rD[63:32] < - 0 
Exceptions: 
Floating Point 

Format: 
lf.sfeq.d�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the two registers are equal, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
SR[F] < - rA[63:0] == rB[63:0] 
Exceptions: 
None 

Format: 
lf.sfeq.s�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the two registers are equal, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] == rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[31:0] == rB[31:0] 
Exceptions: 
None 

Format: 
lf.sfge.d�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the first register is greater than or equal to the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
SR[F] < - rA[63:0] >= rB[63:0] 
Exceptions: 
None 

Format: 
lf.sfge.s�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the first register is greater than or equal to the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] >= rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[31:0] >= rB[31:0] 
Exceptions: 
None 

Format: 
lf.sfgt.d�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the first register is greater than the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
SR[F] < - rA[63:0] > rB[63:0] 
Exceptions: 
None 

Format: 
lf.sfgt.s�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the first register is greater than the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] > rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[31:0] > rB[31:0] 
Exceptions: 
None 

Format: 
lf.sfle.d�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the first register is less than or equal to the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
SR[F] < - rA[363:0] < = rB[63:0] 
Exceptions: 
None 

Format: 
lf.sfle.s�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the first register is less than or equal to the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < = rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[31:0] < = rB[31:0] 
Exceptions: 
None 

Format: 
lf.sflt.d�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the first register is less than the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
SR[F] < - rA[63:0] < rB[63:0] 
Exceptions: 
None 

Format: 
lf.sflt.s�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the first register is less than the second register, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] < rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[31:0] < rB[31:0] 
Exceptions: 
None 

Format: 
lf.sfne.d�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the two registers are not equal, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
SR[F] < - rA[63:0] != rB[63:0] 
Exceptions: 
None 

Format: 
lf.sfne.s�rA,rB 
Description: 
The contents of general-purpose register rA and the contents of general-purpose register rB are compared. If the two registers are not equal, the compare flag is set; otherwise the compare flag is cleared. 
32-bit Implementation: 
SR[F] < - rA[31:0] != rB[31:0] 
64-bit Implementation: 
SR[F] < - rA[31:0] != rB[31:0] 
Exceptions: 
None 

Format: 
lf.sub.d�rD,rA,rB 
Description: 
The contents of general-purpose register rB are subtracted from the contents of general-purpose register rA to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] - rB[63:0] 
Exceptions: 
Floating Point 

Format: 
lf.sub.s�rD,rA,rB 
Description: 
The contents of general-purpose register rB are subtracted from the contents of general-purpose register rA to form the result. The result is placed into general-purpose register rD. 
32-bit Implementation: 
rD[31:0] < - rA[31:0] - rB[31:0] 
64-bit Implementation: 
rD[31:0] < - rA[31:0] - rB[31:0]rD[63:32] < - 0 
Exceptions: 
Floating Point 

Format: 
lv.add.b�rD,rA,rB 
Description: 
The byte elements of general-purpose register rA are added to the byte elements of general-purpose register rB to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] + rB[7:0]rD[15:8] < - rA[15:8] + rB[15:8]rD[23:16] < - rA[23:16] + rB[23:16]rD[31:24] < - rA[31:24] + rB[31:24]rD[39:32] < - rA[39:32] + rB[39:32]rD[47:40] < - rA[47:40] + rB[47:40]rD[55:48] < - rA[55:48] + rB[55:48]rD[63:56] < - rA[63:56] + rB[63:56] 
Exceptions: 
None 

Format: 
lv.add.h�rD,rA,rB 
Description: 
The half-word elements of general-purpose register rA are added to the half-word elements of general-purpose register rB to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] + rB[15:0]rD[31:16] < - rA[31:16] + rB[31:16]rD[47:32] < - rA[47:32] + rB[47:32]rD[63:48] < - rA[63:48] + rB[63:48]
Exceptions: 
None 

Format: 
lv.adds.b�rD,rA,rB 
Description: 
The byte elements of general-purpose register rA are added to the byte elements of general-purpose register rB to form the result elements. If the result exceeds the min/max value for the destination data type, it is saturated to the min/max value and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - sat8s(rA[7:0] + rB[7:0])rD[15:8] < - sat8s(rA[15:8] + rB[15:8])rD[23:16] < - sat8s(rA[23:16] + rB[23:16])rD[31:24] < - sat8s(rA[31:24] + rB[31:24])rD[39:32] < - sat8s(rA[39:32] + rB[39:32])rD[47:40] < - sat8s(rA[47:40] + rB[47:40])rD[55:48] < - sat8s(rA[55:48] + rB[55:48])rD[63:56] < - sat8s(rA[63:56] + rB[63:56]) 
Exceptions: 
None 

Format: 
lv.adds.h�rD,rA,rB 
Description: 
The half-word elements of general-purpose register rA are added to the half-word elements of general-purpose register rB to form the result elements. If the result exceeds the min/max value for the destination data type, it is saturated to the min/max value and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - sat16s(rA[15:0] + rB[15:0])rD[31:16] < - sat16s(rA[31:16] + rB[31:16])rD[47:32] < - sat16s(rA[47:32] + rB[47:32])rD[63:48] < - sat16s(rA[63:48] + rB[63:48]) 
Exceptions: 
None 

Format: 
lv.addu.b�rD,rA,rB 
Description: 
The unsigned byte elements of general-purpose register rA are added to the unsigned byte elements of general-purpose register rB to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] + rB[7:0]rD[15:8] < - rA[15:8] + rB[15:8]rD[23:16] < - rA[23:16] + rB[23:16]rD[31:24] < - rA[31:24] + rB[31:24]rD[39:32] < - rA[39:32] + rB[39:32]rD[47:40] < - rA[47:40] + rB[47:40]rD[55:48] < - rA[55:48] + rB[55:48]rD[63:56] < - rA[63:56] + rB[63:56] 
Exceptions: 
None 

Format: 
lv.addu.h�rD,rA,rB 
Description: 
The unsigned half-word elements of general-purpose register rA are added to the unsigned half-word elements of general-purpose register rB to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] + rB[15:0]rD[31:16] < - rA[31:16] + rB[31:16]rD[47:32] < - rA[47:32] + rB[47:32]rD[63:48] < - rA[63:48] + rB[63:48]
Exceptions: 
None 

Format: 
lv.addus.b�rD,rA,rB 
Description: 
The unsigned byte elements of general-purpose register rA are added to the unsigned byte elements of general-purpose register rB to form the result elements. If the result exceeds the min/max value for the destination data type, it is saturated to the min/max value and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - sat8u(rA[7:0] + rB[7:0])rD[15:8] < - sat8u(rA[15:8] + rB[15:8])rD[23:16] < - sat8u(rA[23:16] + rB[23:16])rD[31:24] < - sat8u(rA[31:24] + rB[31:24])rD[39:32] < - sat8u(rA[39:32] + rB[39:32])rD[47:40] < - sat8u(rA[47:40] + rB[47:40])rD[55:48] < - sat8u(rA[55:48] + rB[55:48])rD[63:56] < - sat8u(rA[63:56] + rB[63:56]) 
Exceptions: 
None 

Format: 
lv.addus.h�rD,rA,rB 
Description: 
The unsigned half-word elements of general-purpose register rA are added to the unsigned half-word elements of general-purpose register rB to form the result elements. If the result exceeds the min/max value for the destination data type, it is saturated to the min/max value and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - sat16s(rA[15:0] + rB[15:0])rD[31:16] < - sat16s(rA[31:16] + rB[31:16])rD[47:32] < - sat16s(rA[47:32] + rB[47:32])rD[63:48] < - sat16s(rA[63:48] + rB[63:48]) 
Exceptions: 
None 

Format: 
lv.all_eq.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if all corresponding elements are equal; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] == rB[7:0] rA[15:8] == rB[15:8] &&rA[23:16] == rB[23:16] &&rA[31:24] == rB[31:24] &&rA[39:32] == rB[39:32] &&rA[47:40] == rB[47:40] &&rA[55:48] == rB[55:48] &&rA[63:56] == rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_eq.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if all corresponding elements are equal; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] == rB[15:0] &&rA[31:16] == rB[31:16] &&rA[47:32] == rB[47:32] &&rA[63:48] == rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_ge.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if all elements of rA are greater than or equal to the elements of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] >= rB[7:0] &&rA[15:8] >= rB[15:8] &&rA[23:16] >= rB[23:16] &&rA[31:24] >= rB[31:24] &&rA[39:32] >= rB[39:32] &&rA[47:40] >= rB[47:40] &&rA[55:48] >= rB[55:48] &&rA[63:56] >= rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_ge.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if all elements of rA are greater than or equal to the elements of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] >= rB[15:0] &&rA[31:16] >= rB[31:16] &&rA[47:32] >= rB[47:32] &&rA[63:48] >= rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_gt.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if all elements of rA are greater than the elements of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] > rB[7:0] &&rA[15:8] > rB[15:8] &&rA[23:16] > rB[23:16] &&rA[31:24] > rB[31:24] &&rA[39:32] > rB[39:32] &&rA[47:40] > rB[47:40] &&rA[55:48] > rB[55:48] &&rA[63:56] > rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_gt.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if all elements of rA are greater than the elements of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] > rB[15:0] &&rA[31:16] > rB[31:16] &&rA[47:32] > rB[47:32] &&rA[63:48] > rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_le.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if all elements of rA are less than or equal to the elements of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] < = rB[7:0] &&rA[15:8] < = rB[15:8] &&rA[23:16] < = rB[23:16] &&rA[31:24] < = rB[31:24] &&rA[39:32] < = rB[39:32] &&rA[47:40] < = rB[47:40] &&rA[55:48] < = rB[55:48] &&rA[63:56] < = rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_le.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if all elements of rA are less than or equal to the elements of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] < = rB[15:0] &&rA[31:16] < = rB[31:16] &&rA[47:32] < = rB[47:32] &&rA[63:48] < = rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_lt.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if all elements of rA are less than the elements of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] < rB[7:0] &&rA[15:8] < rB[15:8] &&rA[23:16] < rB[23:16] &&rA[31:24] < rB[31:24] &&rA[39:32] < rB[39:32] &&rA[47:40] < rB[47:40] &&rA[55:48] < rB[55:48] &&rA[63:56] < rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_lt.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if all elements of rA are less than the elements of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] < rB[15:0] &&rA[31:16] < rB[31:16] &&rA[47:32] < rB[47:32] &&rA[63:48] < rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_ne.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if all corresponding elements are not equal; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] != rB[7:0] &&rA[15:8] != rB[15:8] &&rA[23:16] != rB[23:16] &&rA[31:24] != rB[31:24] &&rA[39:32] != rB[39:32] &&rA[47:40] != rB[47:40] &&rA[55:48] != rB[55:48] &&rA[63:56] != rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.all_ne.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if all corresponding elements are not equal; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] != rB[15:0] &&rA[31:16] != rB[31:16] &&rA[47:32] != rB[47:32] &&rA[63:48] != rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.and�rD,rA,rB 
Description: 
The contents of general-purpose register rA are combined with the contents of general-purpose register rB in a bit-wise logical AND operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] AND rB[63:0] 
Exceptions: 
None 

Format: 
lv.any_eq.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if any two corresponding elements are equal; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] == rB[7:0] ||rA[15:8] == rB[15:8] ||rA[23:16] == rB[23:16] ||rA[31:24] == rB[31:24] ||rA[39:32] == rB[39:32] ||rA[47:40] == rB[47:40] ||rA[55:48] == rB[55:48] ||rA[63:56] == rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_eq.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if any two corresponding elements are equal; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] == rB[15:0] ||rA[31:16] == rB[31:16] ||rA[47:32] == rB[47:32] ||rA[63:48] == rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_ge.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if any element of rA is greater than or equal to the corresponding element of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] >= rB[7:0] ||rA[15:8] >= rB[15:8] ||rA[23:16] >= rB[23:16] ||rA[31:24] >= rB[31:24] ||rA[39:32] >= rB[39:32] ||rA[47:40] >= rB[47:40] ||rA[55:48] >= rB[55:48] ||rA[63:56] >= rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_ge.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if any element of rA is greater than or equal to the corresponding element of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] >= rB[15:0] ||rA[31:16] >= rB[31:16] ||rA[47:32] >= rB[47:32] ||rA[63:48] >= rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_gt.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if any element of rA is greater than the corresponding element of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] > rB[7:0] ||rA[15:8] > rB[15:8] ||rA[23:16] > rB[23:16] ||rA[31:24] > rB[31:24] ||rA[39:32] > rB[39:32] ||rA[47:40] > rB[47:40] ||rA[55:48] > rB[55:48] ||rA[63:56] > rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_gt.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if any element of rA is greater than the corresponding element of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] > rB[15:0] ||rA[31:16] > rB[31:16] ||rA[47:32] > rB[47:32] ||rA[63:48] > rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_le.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if any element of rA is less than or equal to the corresponding element of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] < = rB[7:0] ||rA[15:8] < = rB[15:8] ||rA[23:16] < = rB[23:16] ||rA[31:24] < = rB[31:24] ||rA[39:32] < = rB[39:32] ||rA[47:40] < = rB[47:40] ||rA[55:48] < = rB[55:48] ||rA[63:56] < = rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_le.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if any element of rA is less than or equal to the corresponding element of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] ,= rB[15:0] ||rA[31:16] < = rB[31:16] ||rA[47:32] < = rB[47:32] ||rA[63:48] < = rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_lt.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if any element of rA is less than the corresponding element of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] < rB[7:0] ||rA[15:8] < rB[15:8] ||rA[23:16] < rB[23:16] ||rA[31:24] < rB[31:24] ||rA[39:32] < rB[39:32] ||rA[47:40] < rB[47:40] ||rA[55:48] < rB[55:48] ||rA[63:56] < rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_lt.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if any element of rA is less than the corresponding element of rB; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] < rB[15:0] ||rA[31:16] < rB[31:16] ||rA[47:32] < rB[47:32] ||rA[63:48] < rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_ne.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. The compare flag is set if any two corresponding elements are not equal; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[7:0] != rB[7:0] ||rA[15:8] != rB[15:8] ||rA[23:16] != rB[23:16] ||rA[31:24] != rB[31:24] ||rA[39:32] != rB[39:32] ||rA[47:40] != rB[47:40] ||rA[55:48] != rB[55:48] ||rA[63:56] != rB[63:56]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.any_ne.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. The compare flag is set if any two corresponding elements are not equal; otherwise the compare flag is cleared. The compare flag is replicated into all bit positions of general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
flag < - rA[15:0] != rB[15:0] ||rA[31:16] != rB[31:16] ||rA[47:32] != rB[47:32] ||rA[63:48] != rB[63:48]rD[63:0] < - repl(flag) 
Exceptions: 
None 

Format: 
lv.avg.b�rD,rA,rB 
Description: 
The byte elements of general-purpose register rA are added to the byte elements of general-purpose register rB, and the sum is shifted right by one to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - (rA[7:0] + rB[7:0]) >> 1rD[15:8] < - (rA[15:8] + rB[15:8]) >> 1rD[23:16] < - (rA[23:16] + rB[23:16]) >> 1rD[31:24] < - (rA[31:24] + rB[31:24]) >> 1rD[39:32] < - (rA[39:32] + rB[39:32]) >> 1rD[47:40] < - (rA[47:40] + rB[47:40]) >> 1rD[55:48] < - (rA[55:48] + rB[55:48]) >> 1rD[63:56] < - (rA[63:56] + rB[63:56]) >> 1 
Exceptions: 
None 

Format: 
lv.avg.h�rD,rA,rB 
Description: 
The half-word elements of general-purpose register rA are added to the half-word elements of general-purpose register rB, and the sum is shifted right by one to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - (rA[15:0] + rB[15:0]) >> 1rD[31:16] < - (rA[31:16] + rB[31:16]) >> 1rD[47:32] < - (rA[47:32] + rB[47:32]) >> 1rD[63:48] < - (rA[63:48] + rB[63:48]) >> 1
Exceptions: 
None 

Format: 
lv.cmp_eq.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the two corresponding compared elements are equal; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - repl(rA[7:0] == rB[7:0]rD[15:8] < - repl(rA[15:8] == rB[15:8]rD[23:16] < - repl(rA[23:16] == rB[23:16]rD[31:24] < - repl(rA[31:24] == rB[31:24]rD[39:32] < - repl(rA[39:32] == rB[39:32]rD[47:40] < - repl(rA[47:40] == rB[47:40]rD[55:48] < - repl(rA[55:48] == rB[55:48]rD[63:56] < - repl(rA[63:56] == rB[63:56]
Exceptions: 
None 

Format: 
lv.cmp_eq.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the two corresponding compared elements are equal; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - repl(rA[7:0] == rB[7:0]rD[31:16] < - repl(rA[23:16] == rB[23:16]rD[47:32] < - repl(rA[39:32] == rB[39:32]rD[63:48] < - repl(rA[55:48] == rB[55:48]
Exceptions: 
None 

Format: 
lv.cmp_ge.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the element in rA is greater than or equal to the element in rB; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - repl(rA[7:0] >= rB[7:0]rD[15:8] < - repl(rA[15:8] >= rB[15:8]rD[23:16] < - repl(rA[23:16] >= rB[23:16]rD[31:24] < - repl(rA[31:24] >= rB[31:24]rD[39:32] < - repl(rA[39:32] >= rB[39:32]rD[47:40] < - repl(rA[47:40] >= rB[47:40]rD[55:48] < - repl(rA[55:48] >= rB[55:48]rD[63:56] < - repl(rA[63:56] >= rB[63:56]
Exceptions: 
None 

Format: 
lv.cmp_ge.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the element in rA is greater than or equal to the element in rB; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - repl(rA[7:0] >= rB[7:0]rD[31:16] < - repl(rA[23:16] >= rB[23:16]rD[47:32] < - repl(rA[39:32] >= rB[39:32]rD[63:48] < - repl(rA[55:48] >= rB[55:48]
Exceptions: 
None 

Format: 
lv.cmp_gt.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the element in rA is greater than the element in rB; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - repl(rA[7:0] > rB[7:0]rD[15:8] < - repl(rA[15:8] > rB[15:8]rD[23:16] < - repl(rA[23:16] > rB[23:16]rD[31:24] < - repl(rA[31:24] > rB[31:24]rD[39:32] < - repl(rA[39:32] > rB[39:32]rD[47:40] < - repl(rA[47:40] > rB[47:40]rD[55:48] < - repl(rA[55:48] > rB[55:48]rD[63:56] < - repl(rA[63:56] > rB[63:56]
Exceptions: 
None 

Format: 
lv.cmp_gt.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the element in rA is greater than the element in rB; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - repl(rA[7:0] > rB[7:0]rD[31:16] < - repl(rA[23:16] > rB[23:16]rD[47:32] < - repl(rA[39:32] > rB[39:32]rD[63:48] < - repl(rA[55:48] > rB[55:48]
Exceptions: 
None 

Format: 
lv.cmp_le.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the element in rA is less than or equal to the element in rB; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - repl(rA[7:0] < = rB[7:0]rD[15:8] < - repl(rA[15:8] < = rB[15:8]rD[23:16] < - repl(rA[23:16] < = rB[23:16]rD[31:24] < - repl(rA[31:24] < = rB[31:24]rD[39:32] < - repl(rA[39:32] < = rB[39:32]rD[47:40] < - repl(rA[47:40] < = rB[47:40]rD[55:48] < - repl(rA[55:48] < = rB[55:48]rD[63:56] < - repl(rA[63:56] < = rB[63:56]
Exceptions: 
None 

Format: 
lv.cmp_le.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the element in rA is less than or equal to the element in rB; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - repl(rA[7:0] < = rB[7:0]rD[31:16] < - repl(rA[23:16] < = rB[23:16]rD[47:32] < - repl(rA[39:32] < = rB[39:32]rD[63:48] < - repl(rA[55:48] < = rB[55:48]
Exceptions: 
None 

Format: 
lv.cmp_lt.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the element in rA is less than the element in rB; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - repl(rA[7:0] < = rB[7:0]rD[15:8] < - repl(rA[15:8] < = rB[15:8]rD[23:16] < - repl(rA[23:16] < = rB[23:16]rD[31:24] < - repl(rA[31:24] < = rB[31:24]rD[39:32] < - repl(rA[39:32] < = rB[39:32]rD[47:40] < - repl(rA[47:40] < = rB[47:40]rD[55:48] < - repl(rA[55:48] < = rB[55:48]rD[63:56] < - repl(rA[63:56] < = rB[63:56]
Exceptions: 
None 

Format: 
lv.cmp_lt.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the element in rA is less than the element in rB; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - repl(rA[7:0] < = rB[7:0]rD[31:16] < - repl(rA[23:16] < = rB[23:16]rD[47:32] < - repl(rA[39:32] < = rB[39:32]rD[63:48] < - repl(rA[55:48] < = rB[55:48]
Exceptions: 
None 

Format: 
lv.cmp_ne.b�rD,rA,rB 
Description: 
All byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the two corresponding compared elements are not equal; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - repl(rA[7:0] != rB[7:0])rD[15:8] < - repl(rA[15:8] != rB[15:8])rD[23:16] < - repl(rA[23:16] != rB[23:16])rD[31:24] < - repl(rA[31:24] != rB[31:24])rD[39:32] < - repl(rA[39:32] != rB[39:32])rD[47:40] < - repl(rA[47:40] != rB[47:40])rD[55:48] < - repl(rA[55:48] != rB[55:48])rD[63:56] < - repl(rA[63:56] != rB[63:56])
Exceptions: 
None 

Format: 
lv.cmp_ne.h�rD,rA,rB 
Description: 
All half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB. Bits of the element in general-purpose register rD are set if the two corresponding compared elements are not equal; otherwise the element bits are cleared. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - repl(rA[7:0] != rB[7:0])rD[31:16] < - repl(rA[23:16] != rB[23:16])rD[47:32] < - repl(rA[39:32] != rB[39:32])rD[63:48] < - repl(rA[55:48] != rB[55:48])
Exceptions: 
None 

Format: 
lv.cust1� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but instead by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
lv.cust2� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but instead by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
lv.cust3� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but instead by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
lv.cust4� 
Description: 
This fake instruction only allocates instruction set space for custom instructions. Custom instructions are those that are not defined by the architecture but instead by the implementation itself. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
N/A 
Exceptions: 
N/A 

Format: 
lv.madds.h�rD,rA,rB 
Description: 
The signed half-word elements of general-purpose register rA are multiplied by the signed half-word elements of general-purpose register rB to form intermediate results. They are then added to the signed half-word VMAC elements to form the final results that are placed again in the VMAC registers. The intermediate result is placed into general-purpose register rD. If any of the final results exceeds the min/max value, it is saturated. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - sat32s(rA[15:0] * rB[15:0] + VMACLO[31:0])rD[31:16] < - sat32s(rA[31:16] * rB[31:16] + VMACLO[63:32])rD[47:32] < - sat32s(rA[47:32] * rB[47:32] + VMACHI[31:0])rD[63:48] < - sat32s(rA[63:48] * rB[63:48] + VMACHI[63:32])
Exceptions: 
None 

Format: 
lv.max.b�rD,rA,rB 
Description: 
The byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB, and the larger elements are selected to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] > rB[7:0] ? rA[7:0] : vrfB[7:0]rD[15:8] < - rA[15:8] > rB[15:8] ? rA[15:8] : vrfB[15:8]rD[23:16] < - rA[23:16] > rB[23:16] ? rA[23:16] : vrfB[23:16]rD[31:24] < - rA[31:24] > rB[31:24] ? rA[31:24] : vrfB[31:24]rD[39:32] < - rA[39:32] > rB[39:32] ? rA[39:32] : vrfB[39:32]rD[47:40] < - rA[47:40] > rB[47:40] ? rA[47:40] : vrfB[47:40]rD[55:48] < - rA[55:48] > rB[55:48] ? rA[55:48] : vrfB[55:48]rD[63:56] < - rA[63:56] > rB[63:56] ? rA[63:56] : vrfB[63:56] 
Exceptions: 
None 

Format: 
lv.max.h�rD,rA,rB 
Description: 
The half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB, and the larger elements are selected to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] > rB[15:0] ? rA[15:0] : vrfB[15:0]rD[31:16] < - rA[31:16] > rB[31:16] ? rA[31:16] : vrfB[31:16]rD[47:32] < - rA[47:32] > rB[47:32] ? rA[47:32] : vrfB[47:32]rD[63:48] < - rA[63:48] > rB[63:48] ? rA[63:48] : vrfB[63:48]
Exceptions: 
None 

Format: 
lv.merge.b�rD,rA,rB 
Description: 
The byte elements of the lower half of the general-purpose register rA are combined with the byte elements of the lower half of general-purpose register rB in such a way that the lowest element is from rB, the second element from rA, the third again from rB etc. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rB[7:0]rD[15:8] < - rA[15:8]rD[23:16] < - rB[23:16]rD[31:24] < - rA[31:24]rD[39:32] < - rB[39:32]rD[47:40] < - rA[47:40]rD[55:48] < - rB[55:48]rD[63:56] < - rA[63:56] 
Exceptions: 
None 

Format: 
lv.merge.h�rD,rA,rB 
Description: 
The half-word elements of the lower half of the general-purpose register rA are combined with the half-word elements of the lower half of general-purpose register rB in such a way that the lowest element is from rB, the second element from rA, the third again from rB etc. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rB[15:0]rD[31:16] < - rA[31:16]rD[47:32] < - rB[47:32]rD[63:48] < - rA[63:48] 
Exceptions: 
None 

Format: 
lv.min.b�rD,rA,rB 
Description: 
The byte elements of general-purpose register rA are compared to the byte elements of general-purpose register rB, and the smaller elements are selected to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] < rB[7:0] ? rA[7:0] : vrfB[7:0]rD[15:8] < - rA[15:8] < rB[15:8] ? rA[15:8] : vrfB[15:8]rD[23:16] < - rA[23:16] < rB[23:16] ? rA[23:16] : vrfB[23:16]rD[31:24] < - rA[31:24] < rB[31:24] ? rA[31:24] : vrfB[31:24]rD[39:32] < - rA[39:32] < rB[39:32] ? rA[39:32] : vrfB[39:32]rD[47:40] < - rA[47:40] < rB[47:40] ? rA[47:40] : vrfB[47:40]rD[55:48] < - rA[55:48] < rB[55:48] ? rA[55:48] : vrfB[55:48]rD[63:56] < - rA[63:56] < rB[63:56] ? rA[63:56] : vrfB[63:56] 
Exceptions: 
None 

Format: 
lv.min.h�rD,rA,rB 
Description: 
The half-word elements of general-purpose register rA are compared to the half-word elements of general-purpose register rB, and the smaller elements are selected to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] < rB[15:0] ? rA[15:0] : vrfB[15:0]rD[31:16] < - rA[31:16] < rB[31:16] ? rA[31:16] : vrfB[31:16]rD[47:32] < - rA[47:32] < rB[47:32] ? rA[47:32] : vrfB[47:32]rD[63:48] < - rA[63:48] < rB[63:48] ? rA[63:48] : vrfB[63:48]
Exceptions: 
None 

Format: 
lv.msubs.h�rD,rA,rB 
Description: 
The signed half-word elements of general-purpose register rA are multiplied by the signed half-word elements of general-purpose register rB to form intermediate results. They are then subtracted from the signed half-word VMAC elements to form the final results that are placed again in the VMAC registers. The intermediate result is placed into general-purpose register rD. If any of the final results exceeds the min/max value, it is saturated. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - sat32s(VMACLO[31:0] - rA[15:0] * rB[15:0])rD[31:16] < - sat32s(VMACLO[63:32] - rA[31:16] * rB[31:16])rD[47:32] < - sat32s(VMACHI[31:0] - rA[47:32] * rB[47:32])rD[63:48] < - sat32s(VMACHI[63:32] - rA[63:48] * rB[63:48])
Exceptions: 
None 

Format: 
lv.muls.h�rD,rA,rB 
Description: 
The signed half-word elements of general-purpose register rA are multiplied by the signed half-word elements of general-purpose register rB to form the results. The result is placed into general-purpose register rD. If any of the final results exceeds the min/max value, it is saturated. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - sat32s(rA[15:0] * rB[15:0])rD[31:16] < - sat32s(rA[31:16] * rB[31:16])rD[47:32] < - sat32s(rA[47:32] * rB[47:32])rD[63:48] < - sat32s(rA[63:48] * rB[63:48])
Exceptions: 
None 

Format: 
lv.nand�rD,rA,rB 
Description: 
The contents of general-purpose register rA are combined with the contents of general-purpose register rB in a bit-wise logical NAND operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] NAND rB[63:0] 
Exceptions: 
None 

Format: 
lv.nor�rD,rA,rB 
Description: 
The contents of general-purpose register rA are combined with the contents of general-purpose register rB in a bit-wise logical NOR operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] NOR rB[63:0] 
Exceptions: 
None 

Format: 
lv.or�rD,rA,rB 
Description: 
The contents of general-purpose register rA are combined with the contents of general-purpose register rB in a bit-wise logical OR operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] OR rB[63:0] 
Exceptions: 
None 

Format: 
lv.pack.b�rD,rA,rB 
Description: 
The lower half of the byte elements of the general-purpose register rA are truncated and combined with the lower half of the byte truncated elements of the general-purpose register rB in such a way that the lowest elements are from rB, and the highest elements from rA. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[3:0] < - rB[3:0]rD[7:4] < - rB[11:8]rD[11:8] < - rB[19:16]rD[15:12] < - rB[27:24]rD[19:16] < - rB[35:32]rD[23:20] < - rB[43:40]rD[27:24] < - rB[51:48]rD[31:28] < - rB[59:56]rD[35:32] < - rA[3:0]rD[39:36] < - rA[11:8]rD[43:40] < - rA[19:16]rD[47:44] < - rA[27:24]rD[51:48] < - rA[35:32]rD[55:52] < - rA[43:40]rD[59:56] < - rA[51:48]rD[63:60] < - rA[59:56] 
Exceptions: 
None 

Format: 
lv.pack.h�rD,rA,rB 
Description: 
The lower half of the half-word elements of the general-purpose register rA are truncated and combined with the lower half of the half-word truncated elements of the general-purpose register rB in such a way that the lowest elements are from rB, and the highest elements from rA. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rB[15:0]rD[15:8] < - rB[31:16]rD[23:16] < - rB[47:32]rD[31:24] < - rB[63:48]rD[39:32] < - rA[15:0]rD[47:40] < - rA[31:16]rD[55:48] < - rA[47:32]rD[63:56] < - rA[63:48]
Exceptions: 
None 

Format: 
lv.packs.b�rD,rA,rB 
Description: 
The lower half of the signed byte elements of the general-purpose register rA are truncated and combined with the lower half of the signed byte truncated elements of the general-purpose register rB in such a way that the lowest elements are from rB, and the highest elements from rA. If any truncated element exceeds a signed 4-bit value, it is saturated. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[3:0] < - sat4s(rB[7:0]rD[7:4] < - sat4s(rB[15:8]rD[11:8] < - sat4s(rB[23:16]rD[15:12] < - sat4s(rB[31:24]rD[19:16] < - sat4s(rB[39:32]rD[23:20] < - sat4s(rB[47:40]rD[27:24] < - sat4s(rB[55:48]rD[31:28] < - sat4s(rB[63:56]rD[35:32] < - sat4s(rA[7:0]rD[39:36] < - sat4s(rA[15:8]rD[43:40] < - sat4s(rA[23:16]rD[47:44] < - sat4s(rA[31:24]rD[51:48] < - sat4s(rA[39:32]rD[55:52] < - sat4s(rA[47:40]rD[59:56] < - sat4s(rA[55:48]rD[63:60] < - sat4s(rA[63:56] 
Exceptions: 
None 

Format: 
lv.packs.h�rD,rA,rB 
Description: 
The lower half of the signed halfword elements of the general-purpose register rA are truncated and combined with the lower half of the signed half-word truncated elements of the general-purpose register rB in such a way that the lowest elements are from rB, and the highest elements from rA. If any truncated element exceeds a signed 8-bit value, it is saturated. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - sat8s(rB[15:0])rD[15:8] < - sat8s(rB[31:16])rD[23:16] < - sat8s(rB[47:32])rD[31:24] < - sat8s(rB[63:48])rD[39:32] < - sat8s(rA[15:0])rD[47:40] < - sat8s(rA[31:16])rD[55:48] < - sat8s(rA[47:32])rD[63:56] < - sat8s(rA[63:48])
Exceptions: 
None 

Format: 
lv.packus.b�rD,rA,rB 
Description: 
The lower half of the unsigned byte elements of the general-purpose register rA are truncated and combined with the lower half of the unsigned byte truncated elements of the general-purpose register rB in such a way that the lowest elements are from rB, and the highest elements from rA. If any truncated element exceeds an unsigned 4-bit value, it is saturated. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[3:0] < - sat4u(rB[7:0]rD[7:4] < - sat4u(rB[15:8]rD[11:8] < - sat4u(rB[23:16]rD[15:12] < - sat4u(rB[31:24]rD[19:16] < - sat4u(rB[39:32]rD[23:20] < - sat4u(rB[47:40]rD[27:24] < - sat4u(rB[55:48]rD[31:28] < - sat4u(rB[63:56]rD[35:32] < - sat4u(rA[7:0]rD[39:36] < - sat4u(rA[15:8]rD[43:40] < - sat4u(rA[23:16]rD[47:44] < - sat4u(rA[31:24]rD[51:48] < - sat4u(rA[39:32]rD[55:52] < - sat4u(rA[47:40]rD[59:56] < - sat4u(rA[55:48]rD[63:60] < - sat4u(rA[63:56] 
Exceptions: 
None 

Format: 
lv.packus.h�rD,rA,rB 
Description: 
The lower half of the unsigned halfword elements of the general-purpose register rA are truncated and combined with the lower half of the unsigned half-word truncated elements of the general-purpose register rB in such a way that the lowest elements are from rB, and the highest elements from rA. If any truncated element exceeds an unsigned 8-bit value, it is saturated. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - sat8u(rB[15:0])rD[15:8] < - sat8u(rB[31:16])rD[23:16] < - sat8u(rB[47:32])rD[31:24] < - sat8u(rB[63:48])rD[39:32] < - sat8u(rA[15:0])rD[47:40] < - sat8u(rA[31:16])rD[55:48] < - sat8u(rA[47:32])rD[63:56] < - sat8u(rA[63:48])
Exceptions: 
None 

Format: 
lv.perm.n�rD,rA,rB 
Description: 
The 4-bit elements of general-purpose register rA are permuted according to the corresponding 4-bit values in general-purpose register rB. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[3:0] < - rA[rB[3:0]*4+3:rB[3:0]*4]rD[7:4] < - rA[rB[7:4]*4+3:rB[7:4]*4]rD[11:8] < - rA[rB[11:8]*4+3:rB[11:8]*4]rD[15:12] < - rA[rB[15:12]*4+3:rB[15:12]*4]rD[19:16] < - rA[rB[19:16]*4+3:rB[19:16]*4]rD[23:20] < - rA[rB[23:20]*4+3:rB[23:20]*4]rD[27:24] < - rA[rB[27:24]*4+3:rB[27:24]*4]rD[31:28] < - rA[rB[31:28]*4+3:rB[31:28]*4]rD[35:32] < - rA[rB[35:32]*4+3:rB[35:32]*4]rD[39:36] < - rA[rB[39:36]*4+3:rB[39:36]*4]rD[43:40] < - rA[rB[43:40]*4+3:rB[43:40]*4]rD[47:44] < - rA[rB[47:44]*4+3:rB[47:44]*4]rD[51:48] < - rA[rB[51:48]*4+3:rB[51:48]*4]rD[55:52] < - rA[rB[55:52]*4+3:rB[55:52]*4]rD[59:56] < - rA[rB[59:56]*4+3:rB[59:56]*4]rD[63:60] < - rA[rB[63:60]*4+3:rB[63:60]*4] 
Exceptions: 
None 

Format: 
lv.rl.b�rD,rA,rB 
Description: 
The contents of byte elements of general-purpose register rA are rotated left by the number of bits specified in the lower 3 bits in each byte element of general-purpose register rB. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] rl rB[2:0]rD[15:8] < - rA[15:8] rl rB[10:8]rD[23:16] < - rA[23:16] rl rB[18:16]rD[31:24] < - rA[31:24] rl rB[26:24]rD[39:32] < - rA[39:32] rl rB[34:32]rD[47:40] < - rA[47:40] rl rB[42:40]rD[55:48] < - rA[55:48] rl rB[50:48]rD[63:56] < - rA[63:56] rl rB[58:56] 
Exceptions: 
None 

Format: 
lv.rl.h�rD,rA,rB 
Description: 
The contents of half-word elements of general-purpose register rA are rotated left by the number of bits specified in the lower 4 bits in each half-word element of general-purpose register rB. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] rl rB[3:0]rD[31:16] < - rA[31:16] rl rB[19:16]rD[47:32] < - rA[47:32] rl rB[35:32]rD[63:48] < - rA[63:48] rl rB[51:48]
Exceptions: 
None 

Format: 
lv.sll�rD,rA,rB 
Description: 
The contents of general-purpose register rA are shifted left by the number of bits specified in the lower 4 bits in each byte element of general-purpose register rB, inserting zeros into the low-order bits of rD. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] < < rB[2:0] 
Exceptions: 
None 

Format: 
lv.sll.b�rD,rA,rB 
Description: 
The contents of byte elements of general-purpose register rA are shifted left by the number of bits specified in the lower 3 bits in each byte element of general-purpose register rB, inserting zeros into the low-order bits. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] < < rB[2:0]rD[15:8] < - rA[15:8] < < rB[10:8]rD[23:16] < - rA[23:16] < < rB[18:16]rD[31:24] < - rA[31:24] < < rB[26:24]rD[39:32] < - rA[39:32] < < rB[34:32]rD[47:40] < - rA[47:40] < < rB[42:40]rD[55:48] < - rA[55:48] < < rB[50:48]rD[63:56] < - rA[63:56] < < rB[58:56] 
Exceptions: 
None 

Format: 
lv.sll.h�rD,rA,rB 
Description: 
The contents of half-word elements of general-purpose register rA are shifted left by the number of bits specified in the lower 4 bits in each half-word element of general-purpose register rB, inserting zeros into the low-order bits. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] < < rB[3:0]rD[31:16] < - rA[31:16] < < rB[19:16]rD[47:32] < - rA[47:32] < < rB[35:32]rD[63:48] < - rA[63:48] < < rB[51:48]
Exceptions: 
None 

Format: 
lv.sra.b�rD,rA,rB 
Description: 
The contents of byte elements of general-purpose register rA are shifted right by the number of bits specified in the lower 3 bits in each byte element of general-purpose register rB, inserting the most significant bit of each element into the high-order bits. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] sra rB[2:0]rD[15:8] < - rA[15:8] sra rB[10:8]rD[23:16] < - rA[23:16] sra rB[18:16]rD[31:24] < - rA[31:24] sra rB[26:24]rD[39:32] < - rA[39:32] sra rB[34:32]rD[47:40] < - rA[47:40] sra rB[42:40]rD[55:48] < - rA[55:48] sra rB[50:48]rD[63:56] < - rA[63:56] sra rB[58:56] 
Exceptions: 
None 

Format: 
lv.sra.h�rD,rA,rB 
Description: 
The contents of half-word elements of general-purpose register rA are shifted right by the number of bits specified in the lower 4 bits in each half-word element of general-purpose register rB, inserting the most significant bit of each element into the high-order bits. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] sra rB[3:0]rD[31:16] < - rA[31:16] sra rB[19:16]rD[47:32] < - rA[47:32] sra rB[35:32]rD[63:48] < - rA[63:48] sra rB[51:48]
Exceptions: 
None 

Format: 
lv.srl�rD,rA,rB 
Description: 
The contents of general-purpose register rA are shifted right by the number of bits specified in the lower 4 bits in each byte element of general-purpose register rB, inserting zeros into the high-order bits of rD. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] >> rB[2:0] 
Exceptions: 
None 

Format: 
lv.srl.b�rD,rA,rB 
Description: 
The contents of byte elements of general-purpose register rA are shifted right by the number of bits specified in the lower 3 bits in each byte element of general-purpose register rB, inserting zeros into the high-order bits. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] >> rB[2:0]rD[15:8] < - rA[15:8] >> rB[10:8]rD[23:16] < - rA[23:16] >> rB[18:16]rD[31:24] < - rA[31:24] >> rB[26:24]rD[39:32] < - rA[39:32] >> rB[34:32]rD[47:40] < - rA[47:40] >> rB[42:40]rD[55:48] < - rA[55:48] >> rB[50:48]rD[63:56] < - rA[63:56] >> rB[58:56] 
Exceptions: 
None 

Format: 
lv.srl.h�rD,rA,rB 
Description: 
The contents of half-word elements of general-purpose register rA are shifted right by the number of bits specified in the lower 4 bits in each half-word element of general-purpose register rB, inserting zeros into the high-order bits. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] >> rB[3:0]rD[31:16] < - rA[31:16] >> rB[19:16]rD[47:32] < - rA[47:32] >> rB[35:32]rD[63:48] < - rA[63:48] >> rB[51:48]
Exceptions: 
None 

Format: 
lv.sub.b�rD,rA,rB 
Description: 
The byte elements of general-purpose register rB are subtracted from the byte elements of general-purpose register rA to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] - rB[7:0]rD[15:8] < - rA[15:8] - rB[15:8]rD[23:16] < - rA[23:16] - rB[23:16]rD[31:24] < - rA[31:24] - rB[31:24]rD[39:32] < - rA[39:32] - rB[39:32]rD[47:40] < - rA[47:40] - rB[47:40]rD[55:48] < - rA[55:48] - rB[55:48]rD[63:56] < - rA[63:56] - rB[63:56] 
Exceptions: 
None 

Format: 
lv.sub.h�rD,rA,rB 
Description: 
The half-word elements of general-purpose register rB are subtracted from the half-word elements of general-purpose register rA to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] - rB[15:0]rD[31:16] < - rA[31:16] - rB[31:16]rD[47:32] < - rA[47:32] - rB[47:32]rD[63:48] < - rA[63:48] - rB[63:48]
Exceptions: 
None 

Format: 
lv.subs.b�rD,rA,rB 
Description: 
The byte elements of general-purpose register rB are subtracted from the byte elements of general-purpose register rA to form the result elements. If the result exceeds the min/max value for the destination data type, it is saturated to the min/max value and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - sat8s(rA[7:0] + rB[7:0])rD[15:8] < - sat8s(rA[15:8] + rB[15:8])rD[23:16] < - sat8s(rA[23:16] + rB[23:16])rD[31:24] < - sat8s(rA[31:24] + rB[31:24])rD[39:32] < - sat8s(rA[39:32] + rB[39:32])rD[47:40] < - sat8s(rA[47:40] + rB[47:40])rD[55:48] < - sat8s(rA[55:48] + rB[55:48])rD[63:56] < - sat8s(rA[63:56] + rB[63:56]) 
Exceptions: 
None 

Format: 
lv.subs.h�rD,rA,rB 
Description: 
The half-word elements of general-purpose register rB are subtracted from the half-word elements of general-purpose register rA to form the result elements. If the result exceeds the min/max value for the destination data type, it is saturated to the min/max value and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - sat16s(rA[15:0] - rB[15:0])rD[31:16] < - sat16s(rA[31:16] - rB[31:16])rD[47:32] < - sat16s(rA[47:32] - rB[47:32])rD[63:48] < - sat16s(rA[63:48] - rB[63:48]) 
Exceptions: 
None 

Format: 
lv.subu.b�rD,rA,rB 
Description: 
The unsigned byte elements of general-purpose register rB are subtracted from the unsigned byte elements of general-purpose register rA to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - rA[7:0] - rB[7:0]rD[15:8] < - rA[15:8] - rB[15:8]rD[23:16] < - rA[23:16] - rB[23:16]rD[31:24] < - rA[31:24] - rB[31:24]rD[39:32] < - rA[39:32] - rB[39:32]rD[47:40] < - rA[47:40] - rB[47:40]rD[55:48] < - rA[55:48] - rB[55:48]rD[63:56] < - rA[63:56] - rB[63:56] 
Exceptions: 
None 

Format: 
lv.subu.h�rD,rA,rB 
Description: 
The unsigned half-word elements of general-purpose register rB are subtracted from the unsigned half-word elements of general-purpose register rA to form the result elements. The result elements are placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - rA[15:0] - rB[15:0]rD[31:16] < - rA[31:16] - rB[31:16]rD[47:32] < - rA[47:32] - rB[47:32]rD[63:48] < - rA[63:48] - rB[63:48]
Exceptions: 
None 

Format: 
lv.subus.b�rD,rA,rB 
Description: 
The unsigned byte elements of general-purpose register rB are subtracted from the unsigned byte elements of general-purpose register rA to form the result elements. If the result exceeds the min/max value for the destination data type, it is saturated to the min/max value and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - sat8u(rA[7:0] + rB[7:0])rD[15:8] < - sat8u(rA[15:8] + rB[15:8])rD[23:16] < - sat8u(rA[23:16] + rB[23:16])rD[31:24] < - sat8u(rA[31:24] + rB[31:24])rD[39:32] < - sat8u(rA[39:32] + rB[39:32])rD[47:40] < - sat8u(rA[47:40] + rB[47:40])rD[55:48] < - sat8u(rA[55:48] + rB[55:48])rD[63:56] < - sat8u(rA[63:56] + rB[63:56]) 
Exceptions: 
None 

Format: 
lv.subus.h�rD,rA,rB 
Description: 
The unsigned half-word elements of general-purpose register rB are subtracted from the unsigned half-word elements of general-purpose register rA to form the result elements. If the result exceeds the min/max value for the destination data type, it is saturated to the min/max value and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - sat16u(rA[15:0] - rB[15:0])rD[31:16] < - sat16u(rA[31:16] - rB[31:16])rD[47:32] < - sat16u(rA[47:32] - rB[47:32])rD[63:48] < - sat16u(rA[63:48] - rB[63:48]) 
Exceptions: 
None 

Format: 
lv.unpack.b�rD,rA,rB 
Description: 
The lower half of the 4-bit elements in general-purpose register rA are sign-extended and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[7:0] < - exts(rA[3:0])rD[15:8] < - exts(rA[7:4])rD[23:16] < - exts(rA[11:8])rD[31:24] < - exts(rA[15:12])rD[39:32] < - exts(rA[19:16])rD[47:40] < - exts(rA[23:20])rD[55:48] < - exts(rA[27:24])rD[63:56] < - exts(rA[31:28]) 
Exceptions: 
None 

Format: 
lv.unpack.h�rD,rA,rB 
Description: 
The lower half of the 8-bit elements in general-purpose register rA are sign-extended and placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[15:0] < - exts(rA[7:0])rD[31:16] < - exts(rA[15:8])rD[47:32] < - exts(rA[23:16])rD[63:48] < - exts(rA[31:24])
Exceptions: 
None 

Format: 
lv.xor�rD,rA,rB 
Description: 
The contents of general-purpose register rA are combined with the contents of general-purpose register rB in a bit-wise logical XOR operation. The result is placed into general-purpose register rD. 
32-bit Implementation: 
N/A 
64-bit Implementation: 
rD[63:0] < - rA[63:0] XOR rB[63:0] 
Exceptions: 
None 
Exception Model
This chapter describes the various exception types and their handling.

Introduction
The exception mechanism allows the processor to change to supervisor state as a result of external signals, errors, or unusual conditions arising in the execution of instructions. When exceptions occur, information about the state of the processor is saved to certain registers and the processor begins execution at the address predetermined for each exception. Processing of exceptions begins in supervisor mode.
The OpenRISC 1000 arcitecture has special support for fast exception processing � also called fast context switch support. This allows very rapid interrupt processing. It is achieved with shadowing general-purpose and some special registers.
The architecture requires that all exceptions be handled in strict order with respect to the instruction stream. When an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the instruction stream are required to complete before the exception is taken.
Exceptions can occur while an exception handler routine is executing, and multiple exceptions can become nested. Support for fast exceptions allows fast nesting of exceptions until all shadowed registers are used. If context switching is not implemented, nested exceptions should not occur.

Exception Classes
All exceptions can be described as precise or imprecise and either synchronous or asynchronous. Synchronous exceptions are caused by instructions and asynchronous exceptions are caused by events external to the processor.

TypeExceptionAsynchronous/nonmaskableBus Error, ResetAsynchronous/maskableExternal Interrupt, Tick Timer Synchronous/preciseInstruction-caused exceptionsSynchronous/impreciseNoneTable  STYLEREF 1 \s 6 SEQ Table \* ARABIC \s 1 1. Exception Classes

Whenever an exception occurs, current PC is saved to current EPCR and new PC is set with the vector address according to  REF _Ref510799607 \h 
Table 62.

Exception TypeVector OffsetCausal ConditionsReset0x100Caused by software or hardware reset.Bus Error0x200The causes are implementation-specific, but typically they are related to bus errors and attempts to access invalid physical address.Data Page Fault0x300No matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400No matching PTE found in page tables or page protection violation for instruction fetch.Tick Timer0x500Tick timer interrupt asserted.Alignment0x600Load/store access to naturally not aligned location.Illegal Instruction0x700Illegal instruction in the instruction stream.External Interrupt0x800External interrupt asserted.D-TLB Miss0x900No matching entry in DTLB (DTLB miss).I-TLB Miss0xA00No matching entry in ITLB (ITLB miss).Range0xB00If programmed in the SR, the setting of certain flags, like SR[OV], causes a range exception. On OpenRISC implementations with less than 32 GPRs when accessing unimplemented architectural GPRs. On all implementations if SR[CID] had to go out of range in order to process next exception.System Call0xC00System call initiated by software.Floating Point0xD00Caused by floating point instructions when FPCSR status flags are set by FPU and FPCSR[FPEE] is setTrap0xE00Caused by the l.trap instruction or by debug unit.Reserved0xF00 � 0x1400Reserved for future use.Reserved0x1500 � 0x1800Reserved for implementation-specific exceptions.Reserved0x1900 � 0x1F00Reserved for custom exceptions.Table  STYLEREF 1 \s 6 SEQ Table \* ARABIC \s 1 2. Exception Types and Causal Conditions

Exception Processing
Whenever an exception occurs, the current/next PC is saved to the current EPCR except if the current instruction is in the delay slot. If the PC points to the delay slot instruction, PC-4 is saved to the current EPCR and SR[DSX] is set.  REF _Ref76123883 \h 
Table 63 defines what are current/next PC and effective address.
The SR is saved to the current ESR.
Current EPCR/ESR are identified by SR[CID]. If fast context switching is not implemented then current EPCR/ESR are always EPCR0/ESR0.
In addition, the current EEAR is set with the effective address in question if one of the following exceptions occurs: Bus Error, IMMU page fault, DMMU page fault, Alignment, I-TLB miss, D-TLB miss.

ExceptionPriorityEPCR(no delay slot)EPCR(delay slot)EEARReset1---Bus Error4 (insn)
9 (data)Address of instruction that caused exceptionAddress of jump instruction before the instruction that caused exceptionLoad/
store/fetch virtual EAData Page Fault8Address of instruction that caused exceptionAddress of jump instruction before the instruction that caused exceptionLoad/store virtual EAInstruction Page Fault3Address of instruction that caused exceptionAddress of jump instruction before the instruction that caused exceptionInstruction fetch virtual EATick Timer12Address of next not executed instructionAddress of just executed jump instruction-Alignment6Address of instruction that caused exceptionAddress of jump instruction before the instruction that caused exceptionLoad/store virtual EAIllegal Instruction5Address of instruction that caused exceptionAddress of jump instruction before the instruction that caused exceptionInstruction fetch virtual EAExternal Interrupt12Address of next not executed instructionAddress of just executed jump instruction-D-TLB Miss7Address of instruction that caused exceptionAddress of jump instruction before the instruction that caused exceptionLoad/store virtual EAI-TLB Miss2Address of instruction that caused exceptionAddress of jump instruction before the instruction that caused exceptionInstruction fetch virtual EARange10Address of instruction that caused exceptionAddress of jump instruction before the instruction that caused exception-System Call7Address of next not executed instructionAddress of just executed jump instruction-Floating Point11Address of next not executed instructionAddress of just executed jump instruction-Trap7Address of instruction that caused exceptionAddress of jump instruction before the instruction that caused exception-Table  STYLEREF 1 \s 6 SEQ Table \* ARABIC \s 1 3. Values of EPCR and EEAR After Exception

If fast context switching is used, SR[CID] is incremented with each new exception so that a new set of shadowed registers is used. If SR[CID] will overflow with the current exception, a range exception is invoked.
However, if SR[CE] is not set, fast context switching is not enabled. In this case all registers that will be modified by exception handler routine must first be saved.
All exceptions set a new SR where both MMUs are disabled (address translation disabled), supervisor mode is turned on, and tick timer exceptions and interrupts are disabled. (SR[DME]=0, SR[IME]=0, SR[SM]=1, SR[IEE]=0 and SR[TEE]=0).
When enough machine state information has been saved by the exception handler, SR[TTE] and SR[IEE] can be re-enabled so that tick timer and external interrupts are not blocked.
When returning from an exception handler with l.rfe, SR and PC are restored. If SR[CE] is set, CID will be automatically decremented and the previous machine state will be restored; otherwise, general-purpose registers previously saved by exception handler need to be restored as well.

Fast Context Switching (Optional)
Fast context switching is a technique that reduces register storing to stack when exceptions occur. Only one type of exception can be handled, so it is up to the software to figure out what caused it. Using software, both interrupt handler invokation and thread switching can be handled very quickly. The hardware should be capable of switching between contexts in only one cycle.
Context can also be switched during an exception or by using a supervisor register CXR (context register) available only in supervisor mode. CXR is the same for all contexts.

Changing Context in Supervisor Mode
The read/write register CXR consists of two parts: the lower 16 bits represents the current context register set. The upper 16 bits represent the current CID. CCID cannot be accessed in user mode. Writing to CCID causes an immediate context change. Reading from CCID returns the running (current) context ID. The context where CID=0 is also called the main context.
 
BIT31-1615-0IdentifierCCIDCCRSReset00
CCRS has two functions:
When an exception occurs, it holds the previous CID.
It is used to access other context's registers.

Context Switch Caused by Exception
When an exception occurs and fast context switching is enabled, the CCID is copied to CCRS and then set to zero, thus switching to main context.
Functions of the main context are:
Switching between threads
Handling exceptions
Preparing, loading, saving, and releasing context identifiers to/from the CID table

CXR should be stored in a general-purpose register as soon as possible, to allow further exception nesting.
The following table shows an example how the CID table could be used. Generally, there is no need that free exception contexts are equal.

CIDFunction7Exception contexts654Thread contexts3210Main context
 Four thread contexts are loaded, and software can switch between them freely using main context, running in supervisor mode. When an exception occurs, first need to be determined what caused it and switch to the next free exception context. Since exceptions can be nested, more free contexts may have to be available. Some of the contexts thus need to be stored to memory in order to switch to a new exception.
The algorithm used in the main context to handle context saving/restoring and switching can be kept as simple as possible. It should have enough (of its own) registers to store information such as:
Current running CID
Next exception
Thread cycling info
Pointers to context table in memory
Copy of CXR

If the number of interrupts is significant, some sort of defered interrupts calls mechanism can be used. The main context algorithm should store just I/O information passed by the interrupt for further execution and return from main context as soon as possible.

Accessing Other Contexts� Registers
This operation can be done only in supervisor mode. In the basic instruction set we have the l.mtspr and l.mfspr instructions that are used to access shadowed registers.

Memory Model
This chapter describes the OpenRISC 1000 weakly ordered memory model.

Memory
Memory is byte-addressed with halfword accesses aligned on 2-byte boundaries, singleword accesses aligned on 4-byte boundaries, and doubleword accesses aligned on 8-byte boundaries.

Memory Access Ordering
The OpenRISC 1000 architecture specifies a weakly ordered memory model for uniprocessor and shared memory multiprocessor systems. This model has the advantage of a higher-performance memory system but places the responsibility for strict access ordering on the programmer.
The order in which the processor performs memory access, the order in which those accesses complete in memory, and the order in which those accesses are viewed by another processor may all be different. Two means of enforcing memory access ordering are provided to allow programs in uniprocessor and multiprocessor system to share memory.
An OpenRISC 1000 processor implementation may also implement a more restrictive, strongly ordered memory model. Programs written for the weakly ordered memory model will automatically work on processors with strongly ordered memory model.

Memory Synchronize Instruction
The l.msync instruction permits the program to control the order in which load and store operations are performed. This synchronization is accomplished by requiring programs to indicate explicitly in the instruction stream, by inserting a memory sync instruction, that synchronization is required. The memory sync instruction ensures that all memory accesses initiated by a program have been performed before the next instruction is executed.
OpenRISC 1000 processor implementations, that implement the strongly-ordered memory model instead of the weakly-ordered one, can execute memory synchronization instruction as a no-operation instruction.

Pages Designated as Weakly-Ordered-Memory
When a memory page is designated as a Weakly-Ordered-Memory (WOM) page, instructions and data can be accessed out-of-order and with prefetching. When a page is designated as not WOM, instruction fetches and load/store operations are performed in-order without any prefetching.
OpenRISC 1000 scalar processor implementations, that implement strongly-ordered memory model instead of the weakly-ordered one and perform load and store operations in-order, are not required to implement the WOM bit in the MMU.

Memory Management
This chapter describes the virtual memory and access protection mechanisms for memory management within the OpenRISC 1000 architecture.
Note that this chapter describes the address translation mechanism from the perspective of the programming model. As such, it describes the structure of the page tables, the MMU conditions that cause MMU related exceptions and the MMU registers. The hardware implementation details that are invisible to the OpenRISC 1000 programming model, such as MMU organization and TLB size, are not contained in the architectural definition.

MMU Features
The OpenRISC 1000 memory management unit includes the following principal features:
Support for effective address (EA) of 32 bits and 64 bits
Support for implementation specific size of physical address spaces up to 35 address bits (32 GByte)
Three different page sizes:
Level 0 pages (32 Gbyte; only with 64-bit EA) translated with D/I Area Translation Buffer (ATB)
Level 1 pages (16 MByte) translated with D/I Area Translation Buffer (ATB)
Level 2 pages (8 Kbyte) translated with D/I Translation Lookaside Buffer (TLB)
Address translation using one-, two- or three-level page tables
Powerful page based access protection with support for demand-paged virtual memory
Support for simultaneous multi-threading (SMT)

MMU Overview
The primary functions of the MMU in an OpenRISC 1000 processor are to translate effective addresses to physical addresses for memory accesses. In addition, the MMU provides various levels of access protection on a page-by-page basis. Note that this chapter describes the conceptual model of the OpenRISC 1000 MMU and implementations may differ in the specific hardware used to implement this model.
Two general types of accesses generated by OpenRISC 1000 processors require address translation � instruction accesses generated by the instruction fetch unit, and data accesses generated by the load and store unit. Generally, the address translation mechanism is defined in terms of page tables used by OpenRISC 1000 processors to locate the effective to physical address mapping for instruction and data accesses.
The definition of page table data structures provides significant flexibility for the implementation of performance enhancement features in a wide range of processors. Therefore, the performance enhancements used to the page table information on-chip vary from implementation to implementation.
Translation lookaside buffers (TLBs) are commonly implemented in OpenRISC 1000 processors to keep recently-used page address translations on-chip. Although their exact implementation is not specified, the general concepts that are pertinent to the system software are described.

 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 1. Translation of Effective to Physical Address � Simplified block diagram for 32-bit processor implementations

Large areas can be translated with optional facility called Area Translation Buffer (ATB). ATBs translate 16MB and 32GB pages. If xTLB and xATB have a match on the same virtual address, xTLB is used.
The MMU, together with the exception processing mechanism, provides the necessary support for the operating system to implement a paged virtual memory environment and for enforcing protection of designated memory areas.

MMU Exceptions
To complete any memory access, the effective address must be translated to a physical address. An MMU exception occurs if this translation fails.
TLB miss exceptions can happen only on OpenRISC 1000 processor implementations that do TLB reload in software.
The page fault exceptions that are caused by missing PTE in page table or page access protection can happen on any OpenRISC 1000 processor implementations.

EXCEPTION NAMEVECTOR OFFSETCAUSING CONDITIONSData Page Fault0x300No matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400No matching PTE found in page tables or page protection violation for instruction fetch.DTLB Miss0x900No matching entry in DTLB.ITLB Miss0xA00No matching entry in ITLB.Table  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 1. MMU Exceptions

The state saved by the processor for each of the exceptions in Table 9-2 contains information that identifies the address of the failing instruction. Refer to the chapter entitled � REF _Ref511467420 \h Error! Reference source not found.� on page  PAGEREF _Ref511467449 \h Error! Bookmark not defined. for a more detailed description of exception processing.

MMU Special-Purpose Registers
 REF _Ref511467796 \h 
Table 82 summarizes the registers that the operating system uses to program the MMU. These registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode only.
 REF _Ref511467796 \h 
Table 82 does not show two configuration registers that are implemented if implementation implements configuration registers. DMMUCFGR and IMMUCFGR describe capability of DMMU and IMMU.

Grp #Reg #Reg NameUSERMODESUPVMODEDescription10DMMUCR�R/WData MMU Control register11DMMUPR�R/WData MMU Protection Register12DTLBEIR�WData TLB Entry Invalidate register14-7DATBMR0-DATBMR3�R/WData ATB Match registers18-11DATBTR0-DATBTR3�R/WData ATB Translate registers1512-639DTLBW0MR0-DTLBW0MR127�R/WData TLB Match registers Way 01640-767DTLBW0TR0-DTLBW0TR127�R/WData TLB Translate registers Way 01768-895DTLBW1MR0-DTLBW1MR127�R/WData TLB Match registers Way 11896-1023DTLBW1TR0-DTLBW1TR127�R/WData TLB Translate registers Way 111024-1151DTLBW2MR0-DTLBW2MR127�R/WData TLB Match registers Way 211152-1279DTLBW2TR0-DTLBW2TR127�R/WData TLB Translate registers Way 211280-1407DTLBW3MR0-DTLBW3MR127�R/WData TLB Match registers Way 311408-1535DTLBW3TR0-DTLBW3TR127�R/WData TLB Translate registers Way 320IMMUCR�R/WInstruction MMU Control register21IMMUPR�R/WInstruction MMU Protection Register22ITLBEIR�WInstruction TLB Entry Invalidate register24-7IATBMR0-IATBMR3�R/WInstruction ATB Match registers28-11IATBTR0-IATBTR3�R/WInstruction ATB Translate registers2512-639ITLBW0MR0-ITLBW0MR127�R/WInstruction TLB Match registers Way 02640-767ITLBW0TR0-ITLBW0TR127�R/WInstruction TLB Translate registers Way 02768-895ITLBW1MR0-ITLBW1MR127�R/WInstruction TLB Match registers Way 12896-1023ITLBW1TR0-ITLBW1TR127�R/WInstruction TLB Translate registers Way 121024-1151ITLBW2MR0-ITLBW2MR127�R/WInstruction TLB Match registers Way 221152-1279ITLBW2TR0-
ITLBW2TR127�R/WInstruction TLB Translate registers Way 221280-1407ITLBW3MR0-ITLBW3MR127�R/WInstruction TLB Match registers Way 321408-1535ITLBW3TR0-ITLBW3TR127�R/WInstruction TLB Translate registers Way 3Table  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 2. List of MMU Special-Purpose Registers

As TLBs are noncoherent caches of PTEs, software that changes the page tables in any way must perform the appropriate TLB invalidate operations to keep the on-chip TLBs coherent with respect to the page tables in memory.

Data MMU Control Register (DMMUCR)
The DMMUCR is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It provides general control of the DMMU.

Bit31-109-10IdentifierPTBPReservedDTFReset0X0R/WR/WRR/W
DTFDTLB Flush
0 DTLB ready for operation
1 DTLB flush request/statusPTBPPage Table Base Pointer
N 22-bit pointer to the base of page directory/table Table  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 3. DMMUCR Field Descriptions

The PTBP field in the DMMUCR is required only in implementations with hardware PTE reload support. Implementations that use software TLB reload are not required to implement this field because the page table base pointer is stored in a TLB miss exception handler�s variable.
The DTF is optional and when implemented it flushes entire DTLB.

Data MMU Protection Register (DMMUPR)
The DMMUPR is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It defines 7 protection groups indexed by PPI fields in PTEs.

Bit31-2827262524IdentifierReservedUWE7URE7SWE7SRE7ResetX0000R/WRR/WR/WR/WR/W
Bit2322212019181716IdentifierUWE6URE6SWE6SRE6UWE5URE5SWE5SRE5Reset00000000R/WR/WR/WR/WR/WR/WR/WR/WR/W
Bit15141312111098IdentifierUWE4URE4SWE4SRE4UWE3URE3SWE3SRE3Reset00000000R/WR/WR/WR/WR/WR/WR/WR/WR/W
Bit76543210IdentifierUWE2URE2SWE2SRE2UWE1URE1SWE1SRE1Reset00000000R/WR/WR/WR/WR/WR/WR/WR/WR/W
SRExSupervisor Read Enable x
0 Load operation in supervisor mode not permitted
1 Load operation in supervisor mode permittedSWExSupervisor Write Enable x
0 Store operation in supervisor mode not permitted
1 Store operation in supervisor mode permittedURExUser Read Enable x
0 Load operation in user mode not permitted
1 Load operation in user mode permittedUWExUser Write Enable x
0 Store operation in user mode not permitted
1 Store operation in user mode permittedTable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 4. DMMUPR Field Descriptions

A DMMUPR is required only in implementations with hardware PTE reload support. Implementations that use software TLB reload are not required to implement this register; instead a TLB miss handler should have a software variable as replacement for the DMMUPR and it should do a software look-up operation and set DTLBWyTRx protection bits accordingly.

Instruction MMU Control Register (IMMUCR)
The IMMUCR is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It provides general control of the IMMU.

Bit31-109-10IdentifierPTBPReservedITFReset0X0R/WR/WRR/W
ITFITLB Flush
0 ITLB ready for operation
1 ITLB flush request/statusPTBPPage Table Base Pointer
N 22-bit pointer to the base of page directory/table Table  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 5. IMMUCR Field Descriptions

The PTBP field in xMMUCR is required only in implementations with hardware PTE reload support. Implementations that use software TLB reload are not required to implement this field because the page table base pointer is stored in a TLB miss exception handler�s variable.
The ITF is optional and when implemented it flushes entire ITLB.

Instruction MMU Protection Register (IMMUPR)

The IMMUP register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It defines 7 protection groups indexed by PPI fields in PTEs.

Bit31-141312111098IdentifierReservedUXE7SXE7UXE6SXE6UXE5SXE5ResetX000000R/WRR/WR/WR/WR/WR/WR/W
Bit76543210IdentifierUXE4SXE4UXE3SXE3UXE2SXE2UXE1SXE1Reset00000000R/WR/WR/WR/WR/WR/WR/WR/WR/W
SXExSupervisor Execute Enable x
0 Instruction fetch in supervisor mode not permitted
1 Instruction fetch in supervisor mode permittedUXExUser Execute Enable x
0 Instruction fetch in user mode not permitted
1 Instruction fetch in user mode permittedTable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 6. IMMUPR Field Descriptions

The IMMUPR is required only in implementations with hardware PTE reload support. Implementations that use software TLB reload are not required to implement this register; instead the TLB miss handler should have a software variable as replacement for the IMMUPR register and it should do a software look-up operation and set ITLBWyTRx protection bits accordingly.

Instruction/Data TLB Entry Invalidate Registers(xTLBEIR)
The instruction/data TLB entry invalidate registers are special-purpose registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode. They are 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementation.
The xTLBEIR is written with the effective address. The corresponding xTLB entry is invalidated in the local processor.

Bit31-0IdentifierEAReset0R/WWrite Only
EAEffective Address
EA that targets TLB entry inside TLBTable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 7. xTLBEIR Field Descriptions

Instruction/Data Translation Lookaside BufferWay y Match Registers(xTLBWyMR0-xTLBWyMR127)
The xTLBWyMR registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
Together with the xTLBWyTR registers they cache translation entries used for translating virtual to physical address. A virtual address is formed from the EA generated during instruction fetch or load/store operation, and the SR[CID] field. xTLBWyMR registers hold a tag that is compared with the current virtual address generated by the CPU core. Together with the xTLBWyTR registers and match logic they form a core part of the xMMU.

Bit31-12IdentifierVPNResetXR/WR/W
Bit11-87-65-210IdentifierReservedLRUCIDPL1VResetX0X00R/WRR/WR/WR/WR/W
VValid
0 TLB entry invalid
1 TLB entry validPL1Page Level 1
0 Page level is 2
1 Page level is 1CIDContext ID
0-15 TLB entry translates for CIDLRULast Recently used
0-3 Index in LRU queue (lower the number, more recent access)VPNVirtual Page Number
0-N Number of the virtual frame that must match EATable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 8. xTLBMR Field Descriptions

The CID bits can be hardwired to zero if the implementation does not support fast context switching and SR[CID] bits.
Data Translation Lookaside Buffer Way yTranslate Registers(DTLBWyTR0-DTLBWyTR127)
The DTLBWyTR registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
Together with the DTLBWyMR registers they cache translation entries used for translating virtual to physical address. A virtual address is formed from the EA generated during a load/store operation, and the SR[CID] field. Together with the DTLBWyMR registers and match logic they form a core of the DMMU.

Bit31-1211-10987IdentifierPPNReservedSWESREUWEResetXXXXXR/WR/WRR/WR/WR/W
Bit6543210IdentifierUREDAWOMWBCCICCResetXXXXXXXR/WR/WR/WR/WR/WR/WR/WR/W
CCCache Coherency
0 Data cache coherency is not enforced for this page
1 Data cache coherency is enforced for this pageCICache Inhibit
0 Cache is enabled for this page
1 Cache is disabled for this pageWBCWrite-Back Cache
0 Data cache uses write-through strategy for data from this page
1 Data cache uses write-back strategy for data from this pageWOMWeakly-Ordered Memory
0 Strongly-ordered memory model for this page
1 Weakly-ordered memory model for this pageAAccessed
0 Page was not accessed
1 Page was accessedDDirty
0 Page was not modified
1 Page was modifiedUREUser Read Enable x
0 Load operation in supervisor mode not permitted
1 Load operation in supervisor mode permittedUWEUser Write Enable x
0 Store operation in supervisor mode not permitted
1 Store operation in supervisor mode permittedSRESupervisor Read Enable x
0 Load operation in user mode not permitted
1 Load operation in user mode permittedSWESupervisor Write Enable x
0 Store operation in user mode not permitted
1 Store operation in user mode permittedPPNPhysical Page Number
0-N Number of the physical frame in memoryTable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 9. DTLBTR Field Descriptions

Instruction Translation Lookaside Buffer Way yTranslate Registers(ITLBWyTR0-ITLBWyTR127)
The ITLBWyTR registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode. 
Together with the ITLBWyMR registers they cache translation entries used for translating virtual to physical address. A virtual address is formed from the EA generated during an instruction fetch operation, and the SR[CID] field. Together with the ITLBWyMR registers and match logic they form a core part of the IMMU.

Bit31-1211-87IdentifierPPNReservedUXEResetXXXR/WR/WR/WR/W
Bit6543210IdentifierSXEDAWOMWBCCICCResetXXXXXXXR/WR/WR/WR/WR/WR/WR/WR/W
CCCache Coherency
0 Data cache coherency is not enforced for this page
1 Data cache coherency is enforced for this pageCICache Inhibit
0 Cache is enabled for this page
1 Cache is disabled for this pageWBCWrite-Back Cache
0 Data cache uses write-through strategy for data from this page
1 Data cache uses write-back strategy for data from this pageWOMWeakly-Ordered Memory
0 Strongly-ordered memory model for this page
1 Weakly-ordered memory model for this pageAAccessed
0 Page was not accessed
1 Page was accessedDDirty
0 Page was not modified
1 Page was modifiedSXESupervisor Execute Enable x
0 Instruction fetch operation in supervisor mode not permitted
1 Instruction fetch operation in supervisor mode permittedUXEUser Execute Enable x
0 Instruction fetch operation in user mode not permitted
1 Instruction fetch operation in user mode permittedPPNPhysical Page Number
0-N Number of the physical frame in memoryTable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 10. ITLBWyTR Field Descriptions

Instruction/Data Area Translation Buffer MatchRegisters (xATBMR0-xATBMR3)
The xATBMR registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
Together with the xATBTR registers they cache translation entries used for translating virtual to physical address of large address space areas. A virtual address is formed from the EA generated during an instruction fetch or load/store operation, and the SR[CID] field. xATBMR registers hold a tag that is compared with the current virtual address generated by the CPU core. Together with the xATBTR registers and match logic they form a core part of the xMMU.

Bit31-10IdentifierVPNResetXR/WR/W
Bit9-554-10IdentifierReservedPSCIDVResetX000R/WRR/WR/WR/W
VValid
0 TLB entry invalid
1 TLB entry validCIDContext ID
0-15 TLB entry translates for CIDPSPage Size
0 16 Mbyte page
1 32 Gbyte pageVPNVirtual Page Number
0-N Number of the virtual frame that must match EATable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 11. xATBMR Field Descriptions

The CID bits can be hardwired to zero if the implementation does not support fast context switching and SR[CID] bits.

Data Area Translation Buffer TranslateRegisters (DATBTR0-DATBTR3)
The DATBTR registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
Together with the DATBMR registers they cache translation entries used for translating virtual to physical address. A virtual address is formed from the EA generated during a load/store operation, and the SR[CID] field. Together with the DATBMR registers and match logic they form a core part of the DMMU.

Bit31-10987IdentifierPPNUWEURESWEResetXXXXR/WR/WR/WR/WR/W
Bit6543210IdentifierSREDAWOMWBCCICCResetXXXXXXXR/WR/WR/WR/WR/WR/WR/WR/W
CCCache Coherency
0 Data cache coherency is not enforced for this page
1 Data cache coherency is enforced for this pageCICache Inhibit
0 Cache is enabled for this page
1 Cache is disabled for this pageWBCWrite-Back Cache
0 Data cache uses write-through strategy for data from this page
1 Data cache uses write-back strategy for data from this pageWOMWeakly-Ordered Memory
0 Strongly-ordered memory model for this page
1 Weakly-ordered memory model for this pageAAccessed
0 Page was not accessed
1 Page was accessedDDirty
0 Page was not modified
1 Page was modifiedSRESupervisor Read Enable x
0 Load operation in supervisor mode not permitted
1 Load operation in supervisor mode permittedSWESupervisor Write Enable x
0 Store operation in supervisor mode not permitted
1 Store operation in supervisor mode permittedUREUser Read Enable x
0 Load operation in user mode not permitted
1 Load operation in user mode permittedUWEUser Write Enable x
0 Store operation in user mode not permitted
1 Store operation in user mode permittedPPNPhysical Page Number
0-N Number of the physical frame in memoryTable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 12. DATBTR Field Descriptions

Instruction Area Translation Buffer Translate Registers (IATBTR0-IATBTR3)
The IATBTR registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode. 
Together with the IATBMR registers they cache translation entries used for translating virtual to physical address. A virtual address is formed from the EA generated during an instruction fetch operation, and the SR[CID] field. Together with the IATBMR registers and match logic they form a core part of the IMMU.

Bit31-109-87IdentifierPPNReservedUXEResetXXXR/WR/WR/WR/W
Bit6543210IdentifierSXEDAWOMWBCCICCResetXXXXXXXR/WR/WR/WR/WR/WR/WR/WR/W
CCCache Coherency
0 Data cache coherency is not enforced for this page
1 Data cache coherency is enforced for this pageCICache Inhibit
0 Cache is enabled for this page
1 Cache is disabled for this pageWBCWrite-Back Cache
0 Data cache uses write-through strategy for data from this page
1 Data cache uses write-back strategy for data from this pageWOMWeakly-Ordered Memory
0 Strongly-ordered memory model for this page
1 Weakly-ordered memory model for this pageAAccessed
0 Page was not accessed
1 Page was accessedDDirty
0 Page was not modified
1 Page was modifiedSXESupervisor Execute Enable x
0 Instruction fetch operation in supervisor mode not permitted
1 Instruction fetch operation in supervisor mode permittedUXEUser Execute Enable x
0 Instruction fetch operation in user mode not permitted
1 Instruction fetch operation in user mode permittedPPNPhysical Page Number
0-N Number of the physical frame in memoryTable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 13. IATBTR Field Descriptions

Address Translation Mechanism in 32-bit Implementations
Memory in an OpenRISC 1000 implementation with 32-bit effective addresses (EA) is divided into level 1 and level 2 pages. Translation is therefore based on two-level page table. However for virtual memory areas that do not need the smallest 8KB page granularity, only one level can be used.

 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 2. Memory Divided Into L1 and L2 pages

The first step in page address translation is to append the current SR[CID] bits as most significant bits to the 32-bit effective address, combining them into a 36-bit virtual address. This virtual address is then used to locate the correct page table entry (PTE) in the page tables in the memory. The physical page number is then extracted from the PTE and used in the physical address. Note that for increased performance, most processors implement on-chip translation lookaside buffers (TLBs) to cache copies of the recently-used PTEs.

 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 3. Address Translation Mechanism using Two-Level Page Table

 REF _Ref511937688 \h 
Figure 83 shows an overview of the two-level page table translation of a virtual address to a physical address:
Bits 35..32 of the virtual address select the page tables for the current context (process)
Bits 31..24 of the virtual address correspond to the level 1 page number within the current context�s virtual space. The L1 page index is used to index the L1 page directory and to retrieve the PTE from it, or together with the L2 page index to match for the PTE in on-chip TLBs.
Bits 23..13 of the virtual address correspond to the level 2 page number within the current context�s virtual space. The L2 page index is used to index the L2 page table and to retrieve the PTE from it, or together with the L1 page index to match for the PTE in on-chip TLBs.
Bits 12..0 of the virtual address are the byte offset within the page; these are concatenated with the PPN field of the PTE to form the physical address used to access memory

The OpenRISC 1000 two-level page table translation also allows implementation of segments with only one level of translation. This greatly reduces memory requirements for the page tables since large areas of unused virtual address space can be covered only by level 1 PTEs.

 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 4. Address Translation Mechanism using only L1 Page Table

 REF _Ref511937658 \h 
Figure 84 shows an overview of the one-level page table translation of a virtual address to physical address:
Bits 35..32 of the virtual address select the page tables for the current context (process)
Bits 31..24 of the virtual address correspond to the level 1 page number within the current context�s virtual space. The L1 page index is used to index the L1 page table and to retrieve the PTE from it, or to match for the PTE in on-chip TLBs.
Bits 23..0 of the virtual address are the byte offset within the page; these are concatenated with the truncated PPN field of the PTE to form the physical address used to access memory

Address Translation Mechanism in 64-bit Implementations
Memory in OpenRISC 1000 implementations with 64-bit effective addresses (EA) is divided into level 0, level 1 and level 2 pages. Translation is therefore based on three-level page table. However for virtual memory areas that do not need the smallest page granularity of 8KB, two level translation can be used.

 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 5. Memory Divided Into L0, L1 and L2 pages

The first step in page address translation is truncation of the 64-bit effective address into a 46-bit address. Then the current SR[CID] bits are appended as most significant bits. The 50-bit virtual address thus formed is then used to locate the correct page table entry (PTE) in the page tables in the memory. The physical page number is then extracted from the PTE and used in the physical address. Note that for increased performance, most processors implement on-chip translation lookaside buffers (TLBs) to cache copies of the recently-used PTEs.


 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 6. Address Translation Mechanism using Three-Level Page Table

 REF _Ref511937609 \h 
Figure 86 shows an overview of the three-level page table translation of a virtual address to physical address:
Bits 49..46 of the virtual address select the page tables for the current context (process)
Bits 45..35 of the virtual address correspond to the level 0 page number within current context�s virtual space. The L0 page index is used to index the L0 page directory and to retrieve the PTE from it, or together with the L1 and L2 page indexes to match for the PTE in on-chip TLBs.
Bits 34..24 of the virtual address correspond to the level 1 page number within the current context�s virtual space. The L1 page index is used to index the L1 page directory and to retrieve the PTE from it, or together with the L0 and L2 page indexes to match for the PTE in on-chip TLBs.
Bits 23..13 of the virtual address correspond to the level 2 page number within the current context�s virtual space. The L2 page index is used to index the L2 page table and to retrieve the PTE from it, or together with the L0 and L1 page indexes to match for the PTE in on-chip TLBs.
Bits 12..0 of the virtual address are the byte offset within the page; these are concatenated with the truncated PPN field of the PTE to form the physical address used to access memory

The OpenRISC 1000 three-level page table translation also allows implementation of large segments with two levels of translation. This greatly reduces memory requirements for the page tables since large areas of unused virtual address space can be covered only by level 1 PTEs.

 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 7. Address Translation Mechanism using Two-Level Page Table

 REF _Ref511472644 \h 
Figure 87 shows an overview of the two-level page table translation of a virtual address to physical address:
Bits 49..46 of the virtual address select the page tables for the current context (process)
Bits 45..35 of the virtual address correspond to the level 0 page number within the current context�s virtual space. The L0 page index is used to index the L0 page directory and to retrieve the PTE from it, or together with the L1 page index to match for the PTE in on-chip TLBs.
Bits 34..24 of the virtual address correspond to the level 1 page number within the current context�s virtual space. The L1 page index is used to index the L1 page table and to retrieve the PTE from it, or together with the L0 page index to match for the PTE in on-chip TLBs.
Bits 23..0 of the virtual address are the byte offset within the page; these are concatenated with the truncated PPN field of the PTE to form the physical address used to access memory

Memory Protection Mechanism
After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, a page fault exception is generated.
The memory protection mechanism allows selectively granting read access, write access or execute access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningDMMUPR[SREx]Enable load operations in supervisor mode to the page.DMMUPR[SWEx]Enable store operations in supervisor mode to the page.IMMUPR[SXEx]Enable execution in supervisor mode of the page.DMMUPR[UREx]Enable load operations in user mode to the page.DMMUPR[UWEx]Enable store operations in user mode to the page.IMMUPR[UXEx]Enable execution in user mode of the page.Table  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 14. Protection Attributes

 REF _Ref511930719 \h 
Table 814 lists page protection attributes defined in MMU protection registers. For the individual page the appropriate strategy out of seven possible strategies programmed in MMU protection registers is selected with the PPI field of the PTE.
In OpenRISC 1000 processors that do not implement TLB/ATB reload in hardware, protection registers are not needed.

 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 8. Selection of Page Protection Attributes for Data Accesses

 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 9. Selection of Page Protection Attributes for Instruction Fetch Accesses

Page Table Entry Definition
Page table entries (PTEs) are generated and placed in page tables in memory by the operating system. A PTE is 32 bits wide and is the same for 32-bit and 64-bit OpenRISC 1000 processor implementations.
A PTE translates a virtual memory area into a physical memory area. How much virtual memory is translated depends on which level the PTE resides. PTEs are either in page directories with L bit zeroed or in page tables with L bit set. PTEs in page directories point to next level page directory or to final page table that containts PTEs for actual address translation.

 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 8 SEQ Figure \* ARABIC \s 1 10. Page Table Entry Format

CCCache Coherency
0 Data cache coherency is not enforced for this page
1 Data cache coherency is enforced for this pageCICache Inhibit
0 Cache is enabled for this page
1 Cache is disabled for this pageWBCWrite-Back Cache
0 Data cache uses write-through strategy for data from this page
1 Data cache uses write-back strategy for data from this pageWOMWeakly-Ordered Memory
0 Strongly-ordered memory model for this page
1 Weakly-ordered memory model for this pageAAccessed
0 Page was not accessed
1 Page was accessedDDirty
0 Page was not modified
1 Page was modifiedPPIPage Protection Index
0 PTE is invalid
1-7 Selects a group of six bits from a set of seven protection attribute groups in xMMUCRLLast
0 PTE from page directory pointing to next page directory/table
1 Last PTE in a linked form of PTEs (describing the actual page)PPNPhysical Page Number
0-N Number of the physical frame in memoryTable  STYLEREF 1 \s 8 SEQ Table \* ARABIC \s 1 15. PTE Field Descriptions

Page Table Search Operation
An implementation may choose to implement the page table search operation in either hardware or software. For all page table search operations data addresses are untranslated (i.e. the effective and physical base address of the page table are the same).
When implemented in software, two TLB miss exceptions are used to handle TLB reload operations. Also, the software is responsible for maintaining accessed and dirty bits in the page tables.

Page History Recording
The accessed (A) and dirty (D) bits reside in each PTE and keep information about the history of the page. The operating system uses this information to determine which areas of the main memory to swap to the disk and which areas of the memory to load back to the main memory (demand-paging).
The accessed (A) bit resides both in the PTE in page table and in the copy of PTE in the TLB. Each time the page is accessed by a load, store or instruction fetch operation, the accessed bit is set.
If the TLB reload is performed in software, then the software must also write back the accessed bit from the TLB to the page table.
In cases when access operation to the page fails, it is not defined whether the accessed bit should be set or not. Since the accessed bit is merely a hint to the operating system, it is up to the implementation to decide.
It is up to the operating system to determine when to explicitly clear the accessed bit for a given page.
The dirty (D) bit resides in both the PTE in page table and in the copy of PTE in the TLB. Each time the page is modified by a store operation, the dirty bit is set.
If TLB reload is performed in software, then the software must also write back the dirty bit from the TLB to the page table.
In cases when access operation to the page fails, it is not defined whether the dirty bit should be set or not. Since the dirty bit is merely a hint to the operating system, it is up to the implementation to decide. However implementation or TLB reload software must check whether page is actually writable before setting the dirty bit.
It is up to the operating system to determine when to explicitly clear the dirty bit for a given page.

Page Table Updates
Updates to the page tables include operations like adding a PTE, deleting a PTE and modifying a PTE. On multiprocessor systems exclusive access to the page table must be assured before it is modified.
TLBs are noncoherent caches of the page tables and must be maintained accordingly. Explicit software syncronization between TLB and page tables is required so that page tables and TLBs remain coherent.
Since the processor reloads PTEs even during updates of the page table, special care must be taken when updating page tables so that the processor does not accidently use half modified page table entries.
Cache Model &Cache Coherency
This chapter describes the OpenRISC 1000 cache model and architectural control to maintain cache coherency in multiprocessor environment.
Note that this chapter describes the cache model and cache coherency mechanism from the perspective of the programming model. As such, it describes the cache management principles, the cache coherency mechanisms and the cache control registers. The hardware implementation details that are invisible to the OpenRISC 1000 programming model, such as cache organization and size, are not contained in the architectural definition.
The function of the cache management registers depends on the implementation of the cache(s) and the setting of the memory/cache access attributes. For a program to execute properly on all OpenRISC 1000 processor implementations, software should assume a Harvard cache model. In cases where a processor is implemented without a cache, the architecture guarantees that writing to cache registers will not halt execution. For example a processor without cache should simply ignore writes to cache management registers. A processor with a Stanford cache model should simply ignore writes to instruction cache management registers. In this manner, programs written for separate instruction and data caches will run on all compliant implementations.

Cache Special-Purpose Registers
 REF _Ref511312139 \h 
Table 91 summarizes the registers that the operating system uses to manage the cache(s).
For implementations that have unified cache, registers that control the data and instruction caches are merged and available at the same time both as data and intruction cache registers.

GRP #REG #REG NAMEUSERMODESUPVMODEDESCRIPTION30DCCR�R/WData Cache Control Register31DCBPRWWData Cache Block Prefetch Register32DCBFRWWData Cache Block Flush Register33DCBIR�WData Cache Block Invalidate Register34DCBWRWWData Cache Block Write-back Register35DCBLR-WData Cache Block Lock Register40ICCR�R/WInstruction Cache Control Register41ICBPRWWInstruction Cache Block PreFetch Register42ICBIRWWInstruction Cache Block Invalidate Register43ICBLR-WInstruction Cache Block Lock RegisterTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 1. Cache Registers

Data Cache Control Register
The data cache control register is a 32-bit special-purpose register accessible with the l.mtspr/l.mfspr instructions in supervisor mode. 
The DCCR controls the operation of the data cache.

Bit31-87-0IdentifierReservedEWResetX0R/WRR/W
EWEnable Ways
0000 0000 All ways disabled/locked
�
1111 1111 All ways enabled/unlockedTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 2. DCCR Field Descriptions

If data cache does not implement way locking, the DCCR is not required to be implemented.

Instruction Cache Control Register
The instruction cache control register is a 32-bit special-purpose register accessible with the l.mtspr/l.mfspr instructions in supervisor mode. 
The ICCR controls the operation of the instruction cache.

Bit31-87-0IdentifierReservedEWResetX0R/WRR/W
EWEnable Ways
0000 0000 All ways disabled/locked
�
1111 1111 All ways enabled/unlockedTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 3. ICCR Field Descriptions

If the instruction cache does not implement way locking, the ICCR is not required to be implemented.

Cache Management
This section describes special-purpose cache management registers for both data and instruction caches.
Memory accesses caused by cache management are not recorded (unlike load or store instructions) and cannot invoke any exception.
Instruction caches do not need to be coherent with the memory or caches of other processors. Software must make the instruction cache coherent with modified instructions in the memory. A typical way to accomplish this is:
Data cache block write-back (update of the memory)
l.csync (wait for update to finish)
Instruction cache block invalidate (clear instruction cache block)
Flush pipeline

Data Cache Block Prefetch (Optional)
The data cache block prefetch register is an optional special-purpose register accessible with the l.mtspr/l.mfspr instructions in both user and supervisor modes. It is 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementations. An implementation may choose not to implement this register and ignore all writes to this register.
The DCBPR is written with the effective address and the corresponding block from memory is prefetched into the cache. Memory accesses are not recorded (unlike load or store instructions) and cannot invoke any exception.
A data cache block prefetch is used strictly for improving performance.

Bit31-0IdentifierEAReset0R/WWrite Only
EAEffective Address
EA that targets byte inside cache blockTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 4. DCBPR Field Descriptions

Data Cache Block Flush
The data cache block flush register is a special-purpose register accessible with the l.mtspr/l.mfspr instructions in both user and supervisor modes. It is 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementations.
The DCBFR is written with the effective address. If coherency is required then the corresponding:
Unmodified data cache block is invalidated in all processors.
Modified data cache block is written back to the memory and invalidated in all processors.
Missing data cache block in the local processor causes that modified data cache block in other processor is written back to the memory and invalidated. If other processors have unmodified data cache block, it is just invalidated in all processors.

If coherency is not required then the corresponding:
Unmodified data cache block in the local processor is invalidated.
Modified data cache block is written back to the memory and invalidated in local processor.
Missing cache block in the local processor does not cause any action.

Bit31-0IdentifierEAReset0R/WWrite only
EAEffective Address
EA that targets byte inside cache blockTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 5. DCBFR Field Descriptions

Data Cache Block Invalidate
The data cache block invalidate register is a special-purpose register accessible with the l.mtspr/l.mfspr instructions in supervisor mode. It is 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementations.
The DCBIR is written with the effective address. If coherency is required then the corresponding:
Unmodified data cache block is invalidated in all processors.
Modified data cache block is invalidated in all processors.
Missing data cache block in the local processor causes that data cache blocks in other processors are invalidated. 

If coherency is not required then corresponding:
Unmodified data cache block in the local processor is invalidated.
Modified data cache block in the local processor is invalidated.
Missing cache block in the local processor does not cause any action.

Bit31-0IdentifierEAReset0R/WWrite Only
EAEffective Address
EA that targets byte inside cache blockTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 6. DCBIR Field Descriptions

Data Cache Block Write-Back
The data cache block write-back register is a special-purpose register accessible with the l.mtspr/l.mfspr instructions in both user and supervisor modes. It is 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementations.
The DCBWR is written with the effective address. If coherency is required then the corresponding data cache block in any of the processors is written back to memory if it was modified. If coherency is not required then the corresponding data cache block in the local processor is written back to memory if it was modified.

Bit31-0IdentifierEAReset0R/WWrite Only
EAEffective Address
EA that targets byte inside cache blockTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 7. DCBWR Field Descriptions

Data Cache Block Lock (Optional)
The data cache block lock register is an optional special-purpose register accessible with the l.mtspr/l.mfspr instructions in both user and supervisor modes. It is 32 bits wide in a 32-bit implementation and 64 bits wide in a 64-bit implementation.
The DCBLR is written with the effective address. The corresponding data cache block in the local processor is locked.
If all blocks of the same set in all cache ways are locked, then the cache refill may automatically unlock the least-recently used block.

Bit31-0IdentifierEAReset0R/WWrite Only
EAEffective Address
EA that targets byte inside cache blockTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 8. DCBLR Field Descriptions

Instruction Cache Block Prefetch (Optional)
The instruction cache block prefetch register is an optional special-purpose register accessible with the l.mtspr/l.mfspr instructions in both user and supervisor modes. It is 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementations. An implementation may choose not to implement this register and ignore all writes to this register.
The ICBPR is written with the effective address and the corresponding block from memory is prefetched into the instruction cache. 
Instruction cache block prefetch is used strictly for improving performance.

Bit31-0IdentifierEAReset0R/WWrite Only
EAEffective Address
EA that targets byte inside cache blockTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 9. ICBPR Field Descriptions

Instruction Cache Block Invalidate
The instruction cache block invalidate register is a special-purpose register accessible with the l.mtspr/l.mfspr instructions in both user and supervisor modes. It is 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementations.
The ICBIR is written with the effective address. If coherency is required then the corresponding instruction cache blocks in all processors are invalidated. If coherency is not required then the corresponding instruction cache block is invalidated in the local processor.

Bit31-0IdentifierEAReset0R/WWrite Only
EAEffective Address
EA that targets byte inside cache blockTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 10. ICBIR Field Descriptions

Instruction Cache Block Lock (Optional)
The instruction cache block lock register is an optional special-purpose register accessible with the l.mtspr/l.mfspr instructions in both user and supervisor modes. It is 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementations.
The ICBLR is written with the effective address. The corresponding instruction cache block in the local processor is locked.
If all blocks of the same set in all cache ways are locked, then the cache refill may automatically unlock the least-recently used block.
Missing cache block in the local processor does not cause any action.

Bit31-0IdentifierEAReset0R/WWrite Only
EAEffective Address
EA that targets byte inside cache blockTable  STYLEREF 1 \s 9 SEQ Table \* ARABIC \s 1 11. ICBLR Field Descriptions

Cache/Memory Coherency
The primary role of the cache coherency system is to synchronize cache content with other caches and with the memory and to provide the same image of the memory to all devices using the memory.
The architecture provides several features to implement cache coherency. In systems that do not provide cache coherency with the PTE attributes (because they do not implement a memory management unit), it may be provided through explicit cache management.
Cache coherency in systems with virtual memory can be provided on a page-by-page basis with PTE attributes. The attributes are:
Cache Coherent (CC Attribute)
Caching-Inhibited (CI Attribute)
Write-Back Cache (WBC Attribute)

When the memory/cache attributes are changed, it is imperative that the cache contents should reflect the new attribute settings. This usually means that cache blocks must be flushed or invalidated.

Pages Designated as Cache Coherent Pages
This attribute improves performance of the systems where cache coherency is performed with hardware and is relatively slow. Memory pages that do not need cache coherency are marked with CC=0 and only memory pages that need cache coherency are marked with CC=1. When an access to shared resource is made, the local processor will assert some kind of cache coherency signal and other processors will respond if they have a copy of the target location in their caches.
To improve performance of uniprocessor systems, memory pages should not be designated as CC=1.

Pages Designated as Caching-Inhibited Pages
Memory accesses to memory pages designated with CI=1 are always performed directly into the main memory, bypassing all caches. Memory pages designated with CI=1 are not loaded into the cache and the target content should never be available in the cache. To prevent any accident copy of the target location in the cache, whenever the operating system sets a memory page to be caching-inhibited, it should flush the corresponding cache blocks.
Multiple accesses may be merged into combined accesses except when individual accesses are separated by l.msync or l.csync or l.psync.

Pages Designated as Write-Back Cache Pages
Store accesses to memory pages designated with WBC=0 are performed both in data cache and memory. If a system uses multilevel hierarchy caches, a store must be performed to at least the depth in the memory hierarchy seen by other processors and devices.
Multiple stores may be merged into combined stores except when individual stores are separated by l.msync or l.sync or l.psync. A store operation may cause any part of the cache block to be written back to main memory.
Store accesses to memory pages designated with WBC=1 are performed only to the local data cache. Data from the local data cache can be copied to other caches and to main memory when copy-back operation is required. WBC=1 improves system performance, however it requires cache snooping hardware support in data cache controllers to gurantee cache coherency.
Debug Unit (Optional)
This chapter describes the OpenRISC 1000 debug facility. The debug unit assists software developers in debugging their systems. It provides support for watchpoints, breakpoints and program-flow control registers.
Watchpoints and breakpoint are events triggered by program- or data-flow matching the conditions programmed in the debug registers. Watchpoints do not interfere with the execution of the program-flow except indirectly when they cause a breakpoint. Watchpoints can be counted by Performance Counters Unit.
Breakpoint, unlike watchpoints, also suspends execution of the current program-flow and start trap exception processing. Breakpoint is optional consequence of watchpoints.

Features
The OpenRISC 1000 architecture defines eight sets of debug registers. Additional debug register sets can be defined by the implementation itself. The debug unit is optional and the presence of an implementation is indicated by the UPR[DUP] bit.
Optional implementation
Eight architecture defined sets of debug value/compare registers
Match signed/unsigned conditions on instruction fetch EA, load/store EA and load/store data
Combining match conditions for complex watchpoints
Watchpoints can be counted by Performance Counters Unit
Watchpoints can generate a breakpoint (trap exception)
Counting watchpoints for generation of additional watchpoints

DVR/DCR pairs are used to compare instruction fetch or load/store EA and load/store data to the value stored in DVRs. Matches can be combined into more complex matches and used for generation of watchpoints. Watchpoints can be counted and reported as breakpoint.
 EMBED Visio.Drawing.6  


Figure  STYLEREF 1 \s 10 SEQ Figure \* ARABIC \s 1 1. Block Diagram of Debug Support

Debug Value Registers (DVR0-DVR7)
The debug value registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
The DVRs are programmed with the watchpoint addresses or data by the resident debug software or by the development interface. Their value is compared to the fetch or load/store EA or to the load/store data according to the corresponding DCR. Based on the settings of the corresponding DCR a watchpoint is generated.

Bit31-0IdentifierVALUEReset0R/WR/W
VALUEWatchpoint/Breakpoint Address/DataTable  STYLEREF 1 \s 10 SEQ Table \* ARABIC \s 1 1. DVR Field Descriptions

Debug Control Registers (DCR0-DCR7)
The debug control registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
The DCRs are programmed with the watchpoint settings that define how DVRs are compared to the instruction fetch or load/store EA or to the load/store data.

Bit31-87-543-10IdentifierReservedCTSCCCDPResetX0000R/WRR/WR/WR/WR
DPDVR/DCR Present
0 Corresponding DVR/DCR pair is not present
1 Corresponding DVR/DCR pair is presentCCCompare Condition
000 Masked
001 Equal
010 Less than
011 Less than or equal
100 Greater than
101 Greater than or equal
110 Not equal
111 ReservedSCSigned Comparison
0 Compare using unsigned integers
1 Compare using signed integersCTCompare To
000 Comparison disabled
001 Instruction fetch EA
010 Load EA
011 Store EA
100 Load data
101 Store data
110 Load/Store EA
111 Load/Store dataTable  STYLEREF 1 \s 10 SEQ Table \* ARABIC \s 1 2. DCR Field Descriptions

Debug Mode Register 1 (DMR1)
The debug mode register 1 is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
The DMR1 is programmed with the watchpoint/breakpoint settings that define how DVR/DCR pairs operate and is set by the resident debug software or by the development interface.

Bit31-25232221-2019-1817-16IdentifierReservedBTSTResCW9CW8ResetX00000R/WRR/WR/WR/WR/WR/W
Bit15-1413-1211-109-87-65-43-21-0IdentifierCW7CW6CW5CW4CW3CW2CW1CW0Reset00000000R/WR/WR/WR/WR/WR/WR/WR/WR/W
CW0Chain Watchpoint 0
00 Watchpoint 0 = Match 0
01 Watchpoint 0 = Match 0 & External Watchpoint
10 Watchpoint 0 = Match 0 | External Watchpoint
11 ReservedCW1Chain Watchpoint 1
00 Watchpoint 1 = Match 1
01 Watchpoint 1 = Match 1 & Watchpoint 0
10 Watchpoint 1 = Match 1 | Watchpoint 0
11 ReservedCW2Chain Watchpoint 2
00 Watchpoint 2 = Match 2
01 Watchpoint 2 = Match 2 & Watchpoint 1
10 Watchpoint 2 = Match 2 | Watchpoint 1
11 ReservedCW3Chain Watchpoint 3
00 Watchpoint 3 = Match 3
01 Watchpoint 3 = Match 3 & Watchpoint 2
10 Watchpoint 3 = Match 3 | Watchpoint 2
11 ReservedCW4Chain Watchpoint 4
00 Watchpoint 4 = Match 4
01 Watchpoint 4 = Match 4 & External Watchpoint
10 Watchpoint 4 = Match 4 | External Watchpoint
11 ReservedCW5Chain Watchpoint 5
00 Watchpoint 5 = Match 5
01 Watchpoint 5 = Match 5 & Watchpoint 4
10 Watchpoint 5 = Match 5 | Watchpoint 4
11 ReservedCW6Chain Watchpoint 6
00 Watchpoint 6 = Match 6
01 Watchpoint 6 = Match 6 & Watchpoint 5
10 Watchpoint 6 = Match 6 | Watchpoint 5
11 ReservedCW7Chain Watchpoint 7
00 Watchpoint 7 = Match 7
01 Watchpoint 7 = Match 7 & Watchpoint 6
10 Watchpoint 7 = Match 7 | Watchpoint 6
11 ReservedCW8Chain Watchpoint 8
00 Watchpoint 8 = Watchpoint counter 0 match
01 Watchpoint 8 = Watchpoint counter 0 match & Watchpoint 3
10 Watchpoint 8 = Watchpoint counter 0 match | Watchpoint 3
11 ReservedCW9Chain Watchpoint 9
00 Watchpoint 9 = Watchpoint counter 1 match
01 Watchpoint 9 = Watchpoint counter 1 match & Watchpoint 7
10 Watchpoint 9 = Watchpoint counter 1 match | Watchpoint 7
11 ReservedSTSingle-step Trace
0 Single-step trace disabled
1 Every executed instruction causes trap exceptionBTBranch Trace
0 Branch trace disabled
1 Every executed branch instruction causes trap exceptionTable  STYLEREF 1 \s 10 SEQ Table \* ARABIC \s 1 3. DMR1 Field Descriptions

Debug Mode Register 2(DMR2)
The debug mode register 2 is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode. 
The DMR2 is programmed with the watchpoint/breakpoint settings that define which watchpoints generate a breakpoint and which watchpoint counters are enabled. When a breakpoint happens WBS provides information which watchpoint or several watchpoints caused breakpoint condition. WBS bits are sticky and should be cleared by writing 0 ot them every time a breakpoint condition is processed. DMR2 is set by the resident debug software or by the development interface.

Bit31-2221-1211-210IdentifierWBSWGBAWTCWCE1WCE0Reset00000R/WRR/WR/WR/WR/W
WCE0Watchpoint Counter Enable 0
0 Counter 0 disabled
1 Counter 0 enabledWCE1Watchpoint Counter Enable 1
0 Counter 1 disabled
1 Counter 1 enabledAWTCAssign Watchpoints to Counter
00 0000 0000 All Watchpoints increment counter 0
00 0000 0001 Watchpoint 0 increments counter 1
�
00 0000 1111 First four watchpoints increment counter 1, rest increment counter 0
�
11 1111 1111 All watchpoints increment counter 1WGBWatchpoints Generating Breakpoint (trap exception)
00 0000 0000 Breakpoint disabled
00 0000 0001 Watchpoint 0 generates breakpoint 
�
01 0000 0000 Watchpoint counter 0 generates breakpoint
�
11 1111 1111 All watchpoints generate breakpointWBSWatchpoints Breakpoint Status
00 0000 0000 No watchpoint caused breakpoint
00 0000 0001 Watchpoint 0 caused breakpoint 
�
01 0000 0000 Watchpoint counter 0 caused breakpoint
�
11 1111 1111 Any watchpoint could have caused breakpointTable  STYLEREF 1 \s 10 SEQ Table \* ARABIC \s 1 4. DMR2 Field Descriptions

Debug Watchpoint Counter Register (DWCR0-DWCR1)
The debug watchpoint counter registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
The DWCRs contain 16-bit counters that count watchpoints programmed in the DMR. The value in a DWCR can be accessed by the resident debug software or by the development interface. DWCRs also contain match values. When a counter reaches the match value, a watchpoint is generated.

Bit31-1615-0IdentifierMATCHCOUNTReset00R/WR/WR/W
COUNTNumber of watchpoints programmed in DMR
N 16-bit counter of generated watchpoints assigned to this counterMATCHN 16-bit value that when matched generates a watchpointTable  STYLEREF 1 \s 10 SEQ Table \* ARABIC \s 1 5. DWCR Field Descriptions

Debug Stop Register (DSR)
The debug stop register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
The DSR specifies which exceptions cause the core to stop the execution of the exception handler and turn over control to development interface. It can be programmed by the resident debug software or by the development interface. 

Bit31-141312111098IdentifierReservedTEFPESCEREIMEDMEResetX000000R/WRR/WR/WR/WR/WR/WR/W
Bit76543210IdentifierINTEIIEAETTEIPFEDPFEBUSEERSTEReset00000000R/WR/WR/WR/WR/WR/WR/WR/WR/W
RSTEReset Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceBUSEEBus Error Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceDPFEData Page Fault Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceIPFEInstruction Page Fault Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceTTETick Timer Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceAEAlignment Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceIIEIllegal Instruction Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceINTEInterrupt Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceDMEDTLB Miss Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceIMEITLB Miss Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceRERange Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceSCESystem Call Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceFPEFloating Point Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceTETrap Exception
0 This exception does not transfer control to the development I/F
1 This exception transfers control to the development interfaceTable  STYLEREF 1 \s 10 SEQ Table \* ARABIC \s 1 6. DSR Field Descriptions

Debug Reason Register (DRR)
The debug reason register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
The DRR specifies which event caused the core to stop the execution of program flow and turned control over to the development interface. It should be cleared by the resident debug software or by the development interface.

Bit31-141312111098IdentifierReservedTEFPESCEREIMEDMEResetX000000R/WRR/WR/WR/WR/WR/WR/W
Bit76543210IdentifierINTEIIEAETTEIPFEDPFEBUSEERSTEReset00000000R/WR/WR/WR/WR/WR/WR/WR/WR/W
RSTEReset Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceBUSEEBus Error Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceDPFEData Page Fault Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceIPFEInstruction Page Fault Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceTTETick Timer Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceAEAlignment Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceIIEIllegal Instruction Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceINTEInterrupt Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceDMEDTLB Miss Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceIMEITLB Miss Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceRERange Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceSCESystem Call Exception
0 This exception did not transfer control to the development I/F
1 This exception transfered control to the development interfaceFPEFloating Point Exception
0 This exception did not transfer control to the development I/F
1 This exception transferred control to the development interfaceTETrap Exception
0 This exception did not transfer control to the development I/F
1 This exception transferred control to the development interfaceTable  STYLEREF 1 \s 10 SEQ Table \* ARABIC \s 1 7. DRR Field Descriptions

Performance Counters Unit (Optional)
This chapter describes the OpenRISC 1000 performance counters facility. Performance counters can be used to count predefined events such as L1 instruction or data cache misses, branch instructions, pipeline stalls etc.
Data from the Performance Counters Unit can be used for the following:
To improve performance by developing better application level algorithms, better optimized operating system routines and for improvements in the hardware architecture of these systems (e.g. memory subsystems).
To improve future OpenRISC implementations and add future enhancements to the OpenRISC architecture.
To help system developers debug and test their systems.

Features
The OpenRISC 1000 architecture defines eight performance counters. Additional performance counters can be defined by the implementation itself. The Performance Counters Unit is optional and the presence of an implementation is indicated by the UPR[PCUP] bit.
Optional implementation.
Eight architecture defined performance counters
Eight custom performance counters
Programmable counting conditions.

Performance Counters Count Registers (PCCR0-PCCR7)
The performance counters count registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode. Read access in user mode is possible, if it is enabled in SR[SUMRA].
They are counters of the events programmed in the PCMR registers.

Bit31-0IdentifierCOUNTReset0R/WR/W
COUNTEvent counterTable  STYLEREF 1 \s 11 SEQ Table \* ARABIC \s 1 1. PCCR0 Field Descriptions

Performance Counters Mode Registers (PCMR0-PCMR7)
The performance counters mode registers are 32-bit special-purpose supervisor-level registers accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
They define which events the performance counters unit counts.

Bit31-2625-151413121110IdentifierReservedWPEDDSITLBMDTLBMBSLSUSResetX000000R/WRead OnlyR/WR/WR/WR/WR/WR/W
Bit9876543210IdentifierIFSICMDCMIFSALACIUMCISMReservedCPReset0000000001R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR
CPCounter Present
0 Counter not present
1 Counter presentCISMCount in Supervisor Mode
0 Counter disabled in supervisor mode
1 Counter counts events in supervisor modeCIUMCount in User Mode
0 Counter disabled in user mode
1 Counter counts events in user modeLALoad Access event
0 Event ignored
1 Count load accessesSAStore Access event
0 Event ignored
1 Count store accessesIFInstruction Fetch event
0 Event ignored
1 Count instruction fetchesDCMData Cache Miss event
0 Event ignored
1 Count data cache missedICMInstruction Cache Miss event
0 Event ignored
1 Count instruction cache missesIFSInstruction Fetch Stall event
0 Event ignored
1 Count instruction fetch stallsLSUSLSU Stall event
0 Event ignored
1 Count LSU stallsBSBranch Stalls event
0 Event ignored
1 Count branch stallsDTLBMDTLB Miss event
0 Event ignored
1 Count DTLB missesITLBMITLB Miss event
0 Event ignored
1 Count ITLB missesDDSData Dependency Stalls event
0 Event ignored
1 Count data dependency stallsWPEWatchpoint Events
000 0000 0000 All watchpoint events ignored
000 0000 0001 Watchpoint 0 counted
�
111 1111 1111 All watchpoints countedTable  STYLEREF 1 \s 11 SEQ Table \* ARABIC \s 1 2. PCMR Field Descriptions

Power Management (Optional)
This chapter describes the OpenRISC 1000 power management facility. The power management facility is optional and implementation may choose which features to implement, and which not. UPR[PMP] indicates whether power management is implemented or not.
Note that this chapter describes the architectural control of power management from the perspective of the programming model. As such, it does not describe technology specific optimizations or implementation techniques.

Features
The OpenRISC 1000 architecture defines five architectural features for minimizing power consumption:
slow down feature
doze mode
sleep mode
suspend mode
dynamic clock gating feature

The slow down feature takes advantage of the low-power dividers in external clock generation circuitry to enable full functionality, but at a lower frequency so that power consumption is reduced.
The slow down feature is software controlled with the 4-bit value in PMR[SDF]. A lower value specifies higher expected performance from the processor core. Whether this value controls a processor clock frequency or some other implementation specific feature is irrelevant to the controlling software. Usually PMR[SDF] is dynamically set by the operating system�s idle routine, that monitors the usage of the processor core.
When software initiates the doze mode, software processing on the core suspends. The clocks to the processor internal units are disabled except to the internal tick timer and programmable interrupt controller. However other on-chip blocks (outside of the processor block) can continue to function as normal.
The processor should leave doze mode and enter normal mode when a pending interrupt occurs.
In sleep mode, all processor internal units are disabled and clocks gated. Optionally, an implementation may choose to lower the operating voltage of the processor core.
The processor should leave sleep mode and enter normal mode when a pending interrupt occurs.
In suspend mode, all processor internal units are disabled and clocks gated. Optionally, an implementation may choose to lower the operating voltage of the processor core.
The processor enters normal mode when it is reset. Software may implement a reset exception handler that refreshes system memory and updates the RISC with the state prior to the suspension.
If enabled, the clock-gating feature automatically disables clock subtrees to major processor internal units on a clock cycle basis. These blocks are usually the CPU, FPU/VU, IC, DC, IMMU and DMMU. This feature can be used in a combination with other power management features and low-power modes.
Cache or MMU blocks that are already disabled when software enables this feature, have completely disabled clock subtrees until clock gating is disabled or until the blocks are again enabled.

Power Management Register (PMR)
The power management register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
PMR is used to enable or disable power management features and modes.

Bit31-776543-0IdentifierReservedSUMEDCGESMEDMESDFResetX00000R/WRR/WR/WR/WR/WR/W
SDFSlow Down Factor
0 Full speed
1-15 Logarithmic clock frequency reductionDMEDoze Mode Enable
0 Doze mode not enabled
1 Doze mode enabledSMESleep Mode Enable
0 Sleep mode not enabled
1 Sleep mode enabledDCGEDynamic Clock Gating Enable
0 Dynamic clock gating not enabled
1 Dynamic clock gating enabledSUMESuspend Mode Enable
0 Suspend mode not enabled
1 Suspend mode enabledTable  STYLEREF 1 \s 12 SEQ Table \* ARABIC \s 1 1. PMR Field Descriptions
Programmable Interrupt Controller (Optional)
This chapter describes the OpenRISC 1000 level one programmable interrupt controller. The interrupt controller facility is optional and an implementation may chose whether or not to implement it. If it is not implemented, interrupt input is directly connected to interrupt exception inputs. UPR[PICP] specifies whether the programmable interrupt controller is implemented or not.
The Programmable Interrupt Controller has two special-purpose registers and 32 maskable interrupt inputs. If implementation requires permanent unmasked interrupt inputs, it can use interrupt inputs [1:0] and PICMR[1:0] should be fixed to one.

Features
The OpenRISC 1000 architecture defines an interrupt controller facility with up to 32 interrupt inputs:

 EMBED Visio.Drawing.6  


Figure  STYLEREF 1 \s 13 SEQ Figure \* ARABIC \s 1 1. Programmable Interrupt Controller Block Diagram

PIC Mask Register (PICMR)
The interrupt controller mask register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
PICMR is used to mask or unmask 32 programmable interrupt sources.

Bit31-0IdentifierIUMReset0R/WR/W
IUMInterrupt UnMask
0x00000000 All interrupts are masked
0x00000001 Interrupt input 0 is enabled, all others are masked
�
0xFFFFFFFF All interrupt inputs are enabledTable  STYLEREF 1 \s 13 SEQ Table \* ARABIC \s 1 1. PICMR Field Descriptions

PIC Status Register (PICSR)
The interrupt controller status register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
PICSR is used to determine the status of each PIC interrupt input. PIC can support level-triggered interrupts or combination of level-triggered and edge-triggered. Most implementations today only support level-triggered interrupts. 
For level-triggered implementations bits in PICSR simply represent level of interrupt inputs. Interrupts are cleared by taking appropriate action at the device to negate the source of the interrupt.Writing a '1' or a '0' to bits in the PICSR that reflect a level-triggered source must have no effect on PICSR content. 
The atomic way to clear an interrupt source which is edge-triggered is by writing a '1' to the corresponding bit in the PICSR. This will clear the underlying latch for the edge-triggered source. Writing a '0' to the corresponding bit in the PICSR has no effect on the underlying latch. 

Bit31-0IdentifierISReset0R/WR/(W*)
ISInterrupt Status
0x00000000 All interrupts are inactive
0x00000001 Interrupt input 0 is pending
�
0xFFFFFFFF All interrupts are pendingTable  STYLEREF 1 \s 13 SEQ Table \* ARABIC \s 1 2. PICSR Field Descriptions

Tick Timer Facility (Optional)
This chapter describes the OpenRISC 1000 tick timer facility. It is optional and an implementation may chose whether or not to implement it. UPR[TTP] specifies whether or not the tick timer facility is present.
The Tick Timer is used to schedule operating system and user tasks on regular time basis or as a high precision time reference.
The Tick Timer facility is enabled with TTMR[M]. TTCR is incremented with each clock cycle and a tick timer interrupt can be asserted whenever the lower 28 bits of TTCR match TTMR[TP] and TTMR[IE] is set.
TTCR restarts counting from zero when a match event happens and TTMR[M] is 0x1. If TTMR[M] is 0x2, TTCR is stoped when match event happens and TTCR must be changed to start counting again. When TTMR[M] is 0x3, TTCR keeps counting even when  match event happens.

Features
The OpenRISC 1000 architecture defines a tick timer facility with the following features:
Maximum timer count of 2^32 clock cycles
Maximum time period of 2^28 clock cycles between interrupts
Maskable tick timer interrupt
Single run, restartable counter, or continues counter
 EMBED Visio.Drawing.6  

Figure  STYLEREF 1 \s 14 SEQ Figure \* ARABIC \s 1 1. Tick Timer Block Diagram

Timer interrupts
A timer interrupt will happen everytime TTMR[IE] bit is set and TTMR[TP]matches the lower 28-bits of the TTCR SPR, the top 4 bits are ignored for the comparison. When an interrupt is pending the TTMR[IP] bit will be set and the interrupt will be asserted to the cpu core until it is cleared by writting a 0 to the TTMR[IP] bit. However, if the TTMR[IE] bit was not set when a match condition occured no interrupt will be asserted and the TTMR[IP] bit won't be set unless it has not been cleared from a previous interrupt. The TTMR[IE] bit is not meant as a mask bit, SR[TEE] is provided for that purpose.

Timer modes
It is up to the programmer to ensure that the TTCR SPR is set to a sane value before the timer mode is programmed. When the timing mode is programmed into the timer by setting TTMR[M], the TTCR SPR is not preset to any predefined value, including 0. If the lower 28-bits of the TTCR SPR is numerically greater than what was programmed into TTMR[TP] then the timer will only assert the timer interrupt when the lower 28-bits of the TTCR SPR have wrapped around to 0 and counted up to the match value programmed into TTMR[TP].
Disabled timer
In this mode the timer does not increment the TTCR spr. Though note that the timer interrupt is independent from the timer mode and as such the timer interrupt is not disabled when the timer is disabled.
Auto-restart timer
When the timer is set to auto-restart mode, the timer will reset the TTCR spr to 0 as soon as the lower 28-bits of the TTCR spr match TTMR[TP] and the timer interrupt will be asserted to the cpu core if the TTMR[IE] bit has been set.
One-shot timer
In one-shot timeing mode, the timer stops counting as soon as a match condition has been reached. Although the timer has in effect been disabled (and can't be restarted by writting to the TTCR spr) the TTMR[M] bits shall still indicate that the timer is in one-shot mode and not that it has been disabled. Care should be taken that the timer interrupt has been masked (or disabled) after the match condition has been reached, or else the cpu core will get a spurious timer interrupt.
Continuous timer
In the event that a match condition has been reached, the counter does not stop but rather keeps counting from the value of the TTCR spr and the timer interrupt will be asserted if the TTMR[IE] bit has been set.

Tick Timer Mode Register (TTMR)
The tick timer mode register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
The TTMR is programmed with the time period of the tick timer as well as with the mode bits that control operation of the tick timer.

Bit31-30292827-0IdentifierMIEIPTPReset000XR/WR/WR/WRR/W
TPTime Period
0x0000000 Shortest comparison time period
�
0xFFFFFFF Longest comparison time periodIPInterrupt Pending
0 Tick timer interrupt is not pending
1 Tick timer interrupt pending (write �0� to clear it)IEInterrupt Enable
0 Tick timer does not generate tick timer interrupt
1 Tick timer generates tick timer interrupt when TTMR[TP] matches TTCR[27:0]MMode
00 Tick timer is disabled
01 Timer is restarted when TTMR[TP] matches TTCR[27:0]
10 Timer stops when TTMR[TP] matches TTCR[27:0] (change TTCR to resume counting)
11 Timer does not stop when TTMR[TP] matches TTCR[27:0]Table  STYLEREF 1 \s 14 SEQ Table \* ARABIC \s 1 1. TTMR Field Descriptions

Tick Timer Count Register (TTCR)
The tick timer count register is a 32-bit special-purpose register accessible with the l.mtspr/l.mfspr instructions in supervisor mode and as read-only register in user mode if enabled in SR[SUMRA].
TTCR holds the current value of the timer.




Bit31-0IdentifierCNTReset0R/WR/W
CNTCount
32-bit incrementing counterTable  STYLEREF 1 \s 14 SEQ Table \* ARABIC \s 1 2. TTCR Field Descriptions
OpenRISC 1000 Implementations
Overview
Implementations of the OpenRISC 1000 architecture come in different configurations and version releases.
Version and unit present registers both identify the version/release and its configuration. Detailed configuration for some units is available in configuration registers.
An operating system should read VR, UPR and the configuration registers, and adjust its own operation accordingly. Operating systems ported on a particular OpenRISC version should run on different configurations of this version without modifications.

Version Register (VR)
The version register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It identifies the version (model) and revision level of the OpenRISC 1000 processor. It also specifies the possible template on which this implementation is based.
`
Bit31-2423-1615-65-0IdentifierVERCFGReservedREVReset--X-R/WRRRR
REVRevision
0..63 A 6-bit number that identifies various releases of a particular version. This number is changed for each revision of the device.CFGConfiguration Template
0..99 An 8-bit number that identifies particular configuration. However this is just for operating systems that do not use information provided by configuration registers and thus are not truly portable across different configurations of one implementation version.
Configurations that do implement configuration registers must have their CFG smaller than 50 and configurations that do not implement configuration registers must have their CFG 50 or bigger.VERVersion
0x10..0x19 An 8-bit number that identifies a particular processor version and version of the OpenRISC architecture. Values below 0x10 and above 0x19 are illegal for OpenRISC 1000 processor implementations.Table  STYLEREF 1 \s 15 SEQ Table \* ARABIC \s 1 1. VR Field Descriptions

Unit Present Register (UPR)
The unit present register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It identifies the present units in the processor. It has a bit for each possible unit or functionality. The lower sixteen bits identify the presence of units defined in the OpenRISC 1000 architecture. The upper sixteen bits define the presence of custom units.

Bit31-2423-1110987IdentifierCUPReservedTTPPMPPICPPCUPReset------R/WRRRRRR
Bit6543210IdentifierDUPMPIMPDMPICPDCPUPReset-------R/WRRRRRRR
UPUPR Present
0 UPR is not present
1 UPR is presentDCPData Cache Present
0 Unit is not present
1 Unit is presentICPInstruction Cache Present
0 Unit is not present
1 Unit is presentDMPData MMU Present
0 Unit is not present
1 Unit is presentIMPInstruction MMU Present
0 Unit is not present
1 Unit is presentMPMAC Present
0 Unit is not present
1 Unit is presentDUPDebug Unit Present
0 Unit is not present
1 Unit is presentPCUPPerformance Counters Unit Present
0 Unit is not present
1 Unit is presentPMPPower Management Present
0 Unit is not present
1 Unit is presentPICPProgrammable Interrupt Controller Present
0 Unit is not present
1 Unit is presentTTPTick Timer Present
0 Unit is not present
1 Unit is presentCUPCustom Units PresentTable  STYLEREF 1 \s 15 SEQ Table \* ARABIC \s 1 2. UPR Field Descriptions

CPU Configuration Register (CPUCFGR)
The CPU configuration register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It specifies CPU capabilities and configuration.

Bit31-10IdentifierReservedReset-R/WR
Bit9876543-0IdentifierOV64SOF64SOF32SOB64SOB32SCGFNSGFReset-------R/WRRRRRRR
NSGFNumber of Shadow GPR Files
0 Zero shadow GPR files
15 Fifteen shadow GPR FilesCGFCustom GPR File
0 GPR file has 32 registers
1 GPR file has less than 32 registersOB32SORBIS32 Supported
0 Not supported
1 SupportedOB64SORBIS64 Supported
0 Not supported
1 SupportedOF32SORFPX32 Supported
0 Not supported
1 SupportedOF64SORFP64P Supported
0 Not supported
1 SupportedOV64SORVDX64 Supported
0 Not supported
1 SupportedTable  STYLEREF 1 \s 15 SEQ Table \* ARABIC \s 1 3. CPUCFGR Field Descriptions

DMMU Configuration Register (DMMUCFGR)
The DMMU configuration register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It specifies the DMMU capabilities and configuration.

Bit31-12IdentifierReservedReset-R/WR
Bit1110987-54-21-0IdentifierHTRTEIRIPRICRINAENTSNTWReset-------R/WRRRRRRR
NTWNumber of TLB Ways
0 DTLB has one way
�
3 DTLB has four waysNTSNumber of TLB Sets (entries per way)
0 DTLB has one set (entries per way)
�
7 DTLB has 128 sets (entries per way)NAENumber of ATB Entries
0 DATB does not exist
1 DATB has one entry
�
4 DATB has four entries
5..7 Invalid valuesCRIControl Register Implemented
0 DMMUCR not implemented
1 DMMUCR implementedPRIProtection Register Implemented
0 DMMUPR not implemented
1 DMMUPR implementedTEIRITLB Entry Invalidate Register Implemented
0 DTLBEIR not implemented
1 DTLBEIR implementedHTRHardware TLB Reload
0 TLB Entry reloaded in software
1 TLB Entry reloaded in hardwareTable  STYLEREF 1 \s 15 SEQ Table \* ARABIC \s 1 4. DMMUCFGR Field Descriptions

IMMU Configuration Register (IMMUCFGR)
The IMMU configuration register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It specifies IMMU capabilities and configuration.

Bit31-12IdentifierReservedReset-R/WR
Bit1110987-54-21-0IdentifierHTRTEIRIPRICRINAENTSNTWReset-------R/WRRRRRRR
NTWNumber of TLB Ways
0 ITLB has one way
�
3 ITLB has four waysNTSNumber of TLB Sets (entries per way)
0 ITLB has one set (entries per way)
�
7 ITLB has 128 sets (entries per way)NAENumber of ATB Entries
0 IATB does not exist
1 IATB has one entry
�
4 IATB has four entries
5..7 Invalid valuesCRIControl Register Implemented
0 IMMUCR not implemented
1 IMMUCR implementedPRIProtection Register Implemented
0 IMMUPR not implemented
1 IMMUPR implementedTEIRITLB Entry Invalidate Register Implemented
0 ITLBEIR not implemented
1 ITLBEIR implementedHTRHardware TLB Reload
0 ITLB Entry reloaded in software
1 ITLB Entry reloaded in hardwareTable  STYLEREF 1 \s 15 SEQ Table \* ARABIC \s 1 5. IMMUCFGR Field Descriptions

DC Configuration Register (DCCFGR)
The DC configuration register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It specifies data cache capabilities and configuration.

Bit31-15141312IdentifierReservedCBWBRICBFRICBLRIReset----R/WRRRR
Bit11109876-32-0IdentifierCBPRICBIRICCRICWSCBSNCSNCWReset-------R/WRRRRRRR
NCWNumber of Cache Ways
0 DC has one way
�
5 DC has thirty-two waysNCSNumber of Cache Sets (cache blocks per way)
0 DC has one set (cache blocks per way)
�
10 DC has 1024 sets (cache blocks per way)BSCache Block Size
0 Cache block size 16 bytes
1 Cache block size 32 bytesCWSCache Write Strategy
0 Cache write-through
1 Cache write-backCCRICache Control Register Implemented
0 Register is not implemented
1 Register is implementedCBIRICache Block Invalidate Register Implemented
0 Register is not implemented
1 Register is implementedCBPRICache Block Prefetch Register Implemented
0 Register is not implemented
1 Register is implementedCBLRICache Block Lock Register Implemented
0 Register is not implemented
1 Register is implementedCBFRICache Block Flush Register Implemented
0 Register is not implemented
1 Register is implementedCBWBRICache Block Write-Back Register Implemented
0 Register is not implemented
1 Register is implementedTable  STYLEREF 1 \s 15 SEQ Table \* ARABIC \s 1 6. DCCFGR Field Descriptions

IC Configuration Register (ICCFGR)
The IC configuration register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It specifies instruction cache capabilities and configuration.

Bit31-1312IdentifierReservedCBLRIReset--R/WRR
Bit11109876-32-0IdentifierCBPRICBIRICCRIResCBSNCSNCWReset-------R/WRRRRRRR
NCWNumber of Cache Ways
0 IC has one way
�
5 IC has thirty-two waysNCSNumber of Cache Sets (cache blocks per way)
0 IC has one set (cache blocks per way)
�
10 IC has 1024 sets (cache blocks per way)BSCache Block Size
0 Cache block size 16 bytes
1 Cache block size 32 bytesCCRICache Control Register Implemented
0 Register is not implemented
1 Register is implementedCBIRICache Block Invalidate Register Implemented
0 Register is not implemented
1 Register is implementedCBPRICache Block Prefetch Register Implemented
0 Register is not implemented
1 Register is implementedCBLRICache Block Lock Register Implemented
0 Register is not implemented
1 Register is implementedTable  STYLEREF 1 \s 15 SEQ Table \* ARABIC \s 1 7. ICCFGR Field Descriptions

Debug Configuration Register (DCFGR)
The debug configuration register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It specifies debug unit capabilities and configuration.

Bit31-432-0IdentifierReservedWPCINDPReset---R/WRRR
NDPNumber of Debug Pairs
0 Debug unit has one DCR/DVR pair
�
7 Debug unit has eight DCR/DVR pairsWPCIWatchpoint Counters Implemented
0 Watchpoint counters not implemented
1 Watchpoint counters implementedTable  STYLEREF 1 \s 15 SEQ Table \* ARABIC \s 1 8. DCFGR Field Descriptions

Performance Counters Configuration Register (PCCFGR)
The performance counters configuration register is a 32-bit special-purpose supervisor-level register accessible with the l.mtspr/l.mfspr instructions in supervisor mode.
It specifies performance counters unit capabilities and configuration.

Bit31-32-0IdentifierReservedNPCReset--R/WRR
NPCNumber of Performance Counters
0 One performance counter
�
7 Eight performance countersTable  STYLEREF 1 \s 15 SEQ Table \* ARABIC \s 1 9. PCCFGR Field Descriptions
Application Binary Interface
Data Representation
Fundamental Types
Scalar types in the ISO/ANSI C language are based on memory operands definitions from the chapter entitled � REF _Ref506743342 \h 
Addressing Modes andOperand Conventions� on page  PAGEREF _Ref506743465 \h 
17. Similar relations between architecture and language types can be used for any other language.

TypeC TYPESIZEOFALIGNMENT (BYTES)OPENRISC EQUIVALENTIntegralChar
Signed char1
1
Signed byteUnsigned char11Unsigned byteShort
Signed short22Signed halfwordUnsigned short22Unsigned halfwordInt
Signed int
Long
Signed long
Enum44Signed singlewordUnsigned int44Unsigned singlewordLong long
Signed long long88Signed doublewordUnsigned long long88Unsigned doublewordPointerAny-type *
Any-type (*) ()44Unsigned singlewordFloating-pointFloat44Single precision floatDouble88Double precision floatTable  STYLEREF 1 \s 16 SEQ Table \* ARABIC \s 1 1.  Scalar Types

A null pointer of any type must be zero. All floating-point types are IEEE-754 compliant.
The OpenRISC programming model introduces a set of fundamental vector data types, as described by  REF _Ref506742914 \h 
Table 162. For vector assignments both side of assignment must be of the same vector type.

VECTOR TYPESIZEOFALIGNMENT (BYTES)OPENRISC EQUIVALENTVector char
Vector signed char8
8
Vector of signed bytesVector unsigned char88Vector of unsigned bytesVector short
Vector signed short88Vector of signed halfwordsVector unsigned short88Vector of unsigned halfwordsVector int
Vector signed int
Vector long
Vector signed long88Vector of signed singlewordsVector unsigned int88Vector of unsigned singlewordsVector float88Vector of single-precisionsTable  STYLEREF 1 \s 16 SEQ Table \* ARABIC \s 1 2.  Vector Types

For alignment restrictions of all types see the chapter entitled � REF _Ref506743342 \h 
Addressing Modes andOperand Conventions� on page  PAGEREF _Ref506743385 \h 
19.

Aggregates and Unions
Aggregates (structures and arrays) and unions assume the alignment of their most strictly aligned element.
An array uses the alignment of its elements.
Structures and unions can require padding to meet alignment restrictions. Each element is assigned to the lowest aligned address.

CFigure  STYLEREF 1 \s 16 SEQ Figure \* ARABIC \s 1 1. Byte aligned, sizeof is 1


CDSNFigure  STYLEREF 1 \s 16 SEQ Figure \* ARABIC \s 1 2. No padding, sizeof is 8


CPadPadSSSFigure  STYLEREF 1 \s 16 SEQ Figure \* ARABIC \s 1 3. Padding, sizeof is 18

Bit-fields
C structure and union definitions can have elements defined by a specified number of bits.  REF _Ref506746357 \h 
Table 163 describes valid bit-field types and their ranges.

Bit-field TypeWidth w [bits]RangeSigned char
Char
Unsigned char1 to 8-2w-1 to 2w-1-1
0 to 2w-1
0 to 2w-1Signed short
Short
Unsigned short1 to 16-2w-1 to 2w-1-1
0 to 2w-1
0 to 2w-1Signed int
Int
Enum
Unsigned int
Signed long
Long
Unsigned long1 to 32-2w-1 to 2w-1-1
0 to 2w-1
0 to 2w-1
0 to 2w-1
-2w-1 to 2w-1-1
0 to 2w-1
0 to 2w-1Table  STYLEREF 1 \s 16 SEQ Table \* ARABIC \s 1 3.  Bit-Field Types and Ranges

Bit-fields follow the same alignment rules as aggregates and unions, with the following additions:
Bit-fields are allocated from most to least significant (from left to right)
A bit-field must entirely reside in a storage unit appropriate for its declared type.
Bit-fields may share a storage unit with other struct/union elements, including elements that are not bit-fields. Struct elements occupy different parts of the storage unit.
Unnamed bit-fields� types do not affect the alignment of a structure or union


S(9)J (9)Pad (6)C (8)T(9)Pad (7)U (9)Pad (7)D(8)Pad (24)


Figure  STYLEREF 1 \s 16 SEQ Figure \* ARABIC \s 1 4. Storage unit sharingand alignment padding, sizeof is 12

Function Calling Sequence
This section describes the standard function calling sequence, including stack frame layout, register usage, parameter passing, and so on. The standard calling sequence requirements apply only to global functions, however it is recommended that all functions use the standard calling sequence.

Register Usage
The OpenRISC 1000 architecture defines 32 general-purpose registers. These registers are 32 bits wide in 32-bit implementations and 64 bits wide in 64-bit implementations.

RegisterPreserved across function callsUsageR31NoTemporary registerR30YesCallee-saved registerR29NoTemporary registerR28YesCallee-saved registerR27NoTemporary registerR26YesCallee-saved registerR25NoTemporary registerR24YesCallee-saved registerR23NoTemporary registerR22YesCallee-saved registerR21NoTemporary registerR20YesCallee-saved registerR19NoTemporary registerR18YesCallee-saved registerR17NoTemporary registerR16YesCallee-saved registerR15NoTemporary registerR14YesCallee-saved registerR13NoTemporary registerR12NoTemporary register (RVH - Return value high 32 bits of 64-bit value on 32-bit system)R11NoRV � Return valueR10YesCallee-saved registerR9YesLR � Link address registerR8NoFunction parameter number 5R7NoFunction parameter number 4R6NoFunction parameter number 3R5NoFunction parameter number 2 R4NoFunction parameter number 1R3NoFunction parameter number 0R2YesFP - Frame pointerR1YesSP - Stack pointerR0-Fixed to zeroTable  STYLEREF 1 \s 16 SEQ Table \* ARABIC \s 1 4. General-Purpose Registers

Some registers have assigned roles:
R0 [Zero]Always fixed to zero. Even if it is writable in some embedded implementations, the software shouldn�t modify it.R1 [SP]The stack pointer holds the limit of the current stack frame. The stack contents below the stack pointer are undefined. Stack pointer must be double word aligned at all times.R2 [FP]The frame pointer holds the address of the previous stack frame. Incoming function parameters reside in the previous stack frame and can be accessed at positive offsets from FP.R3 through R8General-purpose parameters use up to 6 general-purpose registers. Parameters beyond the sixth parameter appear on the stack.R9 [LR]Link address is the location of the function call instruction and is used to calculate where program execution should return after function completion. R11 [RV]Return value of the function. For void functions a value is not defined. For functions returning a union or structure, a pointer to the result is placed into return value register.R12 [RVH]Return value high of the function. For functions returning 32-bit values this register can be considered temporary register.
Furthermore, an OpenRISC 1000 implementation might have several sets of shadowed general-purpose registers. These shadowed registers are used for fast context switching and sets can be switched only by the operating system.

The Stack Frame
In addition to registers, each function has a frame on the run-time stack. This stack grows downward from high addresses.  REF _Ref31399889 \h 
Table 165 shows the stack frame organization.

PositionContentsFrameFP + 4N
�
FP + 0Parameter N
�
Parameter 0PreviousFP � 4Function variablesCurrentFP � 8SP + 4Previous FP valueSP + 0Return addressSP � 4
SP � 2096For use by leaf functions w/o function prologue/epilogueFutureSP � 2100
SP � 2536For use by exception handlersTable  STYLEREF 1 \s 16 SEQ Table \* ARABIC \s 1 5. Stack Frame

The stack pointer always points to the end of the latest allocated stack frame. All frames must be double word aligned. In code compiled for 32-bit implementations, upper halves of all double words are zero.
The first 2092 bytes below the current stack frame are reserved for leaf functions that do not need to modify their stack pointer. Exception handlers must guarantee that they will not use this area.

Parameter Passing
Functions receive their first 6 arguments in general-purpose parameter registers. If there are more than six arguments, the remaining arguments are passed on the stack. Structure and union arguments are passed as pointers.
All 64-bit arguments in a 32-bit system are passed using a pair of registers. 64-bit arguments are not aligned. For example long long arg1, long arg2, long long arg3 are be passed in the following way: arg1 in r3&r4, arg2 in r5, arg3 in r6&r7.

Functions Returning Scalars or No Value
A function that returns an integral, pointer or vector/floating-point value places its result in the general-purpose RV register. Void functions put no particular value in GPR[RV] register.

Functions Returning Structures or Unions
A function that returns a structure or union places the address of the structure or union in the general-purpose RV register.

Operating System Interface
Exception Interface
The OpenRISC 1000 exception mechanism allows the processor to change to supervisor mode as a result of external signals, errors or execution of certain instructions. When an exception occurs the following events happen:
The address of the interrupted instruction and the machine state are saved
The machine mode is changed to supervisor mode
The execution resumes from a predefined exception vector address which is different for every exception

Exception TypeVector OffsetSIGNALExampleReset0x100NoneResetBus Error0x200SIGBUSUnexisting physical location, bus parity error.Data Page Fault0x300SIGSEGVUnammaped data location or protection violation.Instruction Page Fault0x400SIGSEGV
	Unmapped instruction location or protection violationTick Timer Interrupt0x500NoneProcess schedulingAlignment0x600SIGBUSUnaligned dataIllegal Instruction0x700SIGILLIllegal/unimplemented instructionExternal Interrupt0x800NoneDevice has asserted an interruptD-TLB Miss0x900NoneDTLB software reload neededI-TLB Miss0xA00NoneITLB software reload neededRange0xB00SIGSEGVArithmetic overflowSystem Call0xC00NoneInstruction l.sysTrap0xE00SIGTRAPInstruction l.trap or debug unit exception.Table  STYLEREF 1 \s 16 SEQ Table \* ARABIC \s 1 6. Hardware Exceptions and Signals

The operating system handles an exception either by completing the faulting exception in a manner transparent to the application, if possible, or by delivering a signal to the application.  REF _Ref515294855 \h 
Table 166 shows how hardware exceptions can be mapped to signals if the operating system cannot complete the faulting exception.

Virtual Address Space
For user programs to execute in virtual address space, the memory management unit (MMU) must be enabled. The MMU translates virtual address generated by the running process into physical address. This allows the process to run anywhere in the physical memory and additionally page to a secondary storage.
Processes typically begin with three logical segments, commonly referred as �text�, �data� and �stack�. Additional segments may exist or can be created by the operating system.

Page Size
Memory is organized into pages, which are the system�s smallest units of memory allocation. The basic page size is 8KB with some implementations supporting 16MB and 32GB pages.

Virtual Address Assignments
Processes have full access to the entire virtual address space. However the size of a process can be limited by several factors such as a process size limit parameter, available physical memory and secondary storage.

0xFFFF_FFFF
Reserved system area
Start of Stack
Growing DownStackGrowing Up
Heap
.bssStart of Data Segments.dataStart of Program Code.text

Start of Dynamic Segment Area
Shared Objects
0x0000_2000

0x0000_0000
Unmapped
Table  STYLEREF 1 \s 16 SEQ Table \* ARABIC \s 1 7. Virtual Address Configuration

Page at location 0x0 is usually reserved to catch dereferences of NULL pointers.
Usually the beginning address of �.text�, �.data� and �.bss� segments are defined when linking the executable file. The heap is adjusted with facilities such as malloc and free. The dynamic segment area is adjusted with mmap, and the stack size is limited with setrlimit.

Stack
Every process has its own stack that is not tied to a fixed area in its address space. Since the stack can change differently for each call of a process, a process should use the stack pointer in general-purpose register r1 to access stack data.

Processor Execution Modes
The OpenRISC 1000 provides two execution modes: user and supervisor. Processes run in user mode and the operating system�s kernel runs in supervisor mode. A Process must execute the l.sys instruction to switch to supervisor mode, hence requesting service from the operating system. System calls uses same software convention model as used with function calls, except additional register r11 specifies system call id.

Position-Independent Code

ELF
The OpenRISC tools use the ELF object file formats and DWARF debugging information formats, as described in System V Application Binary Interface, from the Santa Cruz Operation, Inc. ELF and DWARF provide a suitable basis for representing the information needed for embedded applications. Other object file formats are available, such as COFF. This section describes particular fields in the ELF and DWARF formats that differ from the base standards for those formats. 

Header Convention
The e_machine member of the ELF header contains the decimal value 33906 (hexadecimal 0x8472) that is defined as the name EM_OR32.

	The e_ident member of the ELF header contains values as shown in  REF _Ref31403855 \h 
Table 168.
OR32 ELF e_ident Fieldse_ident[EI_CLASS]ELFCLASS32For all 32-bit implementationsE_ident[EI_DATA]ELFDATA2MSBFor all implementationsTable  STYLEREF 1 \s 16 SEQ Table \* ARABIC \s 1 8.  e_ident Field Values

	The e_flags member of the ELF header contains values as shown in  REF _Ref31404352 \h 
Table 169.
OR32 ELF e_flagsHAS_RELOC0x01Contains relocation entriesEXEC_P0x02Is directly executableHAS_LINENO0x04Has line number informationHAS_DEBUG0x08Has debugging informationHAS_SYMS0x10Has symbolsHAS_LOCALS0x20Has local symbolsDYNAMIC0x40Is dynamic objectWP_TEXT0x80Text section is write protectedD_PAGED0x100Is dynamically pagedTable  STYLEREF 1 \s 16 SEQ Table \* ARABIC \s 1 9.  e_flags Field Values

Sections
There are no OpenRISC section requirements beyond the base ELF standards.

Relocation
This section describes values and algorithms used for relocations. In particular, it describes values the compiler/assembler must leave in place and how the linker modifies those values.

NameValueSizeCalculationR_ OR32_NONE00NoneR_ OR32_32132AR_ OR32_16216A & 0xffffR_OR32_838A & 0xffR_ OR32_CONST416A & 0xffffR_ OR32_CONSTH516(A >> 16) & 0xffffR_ OR32_JUMPTARG628(S + A -P) >> 2
Key S indicates the final value assigned to the symbol refernced in the relocation record.  Key A is the added value specified in the relocation record. Key P indicates the address of the relocation (e.g., the address being modified).

COFF
Sections

Relocation



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 OpenCores   OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005




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31....2625...2120...1615...1110987..43..0opcode 0x38D A B reservedopcode 0x3reservedopcode 0x66 bits5 bits5 bits5 bits1 bits2 bits4 bits4bits
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OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.muliMultiply Immediate Signedl.muli
31....2625...2120...1615..............0opcode 0x2cD A I 6 bits5 bits5 bits16bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 81 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.muluMultiply Unsignedl.mulu
31....2625...2120...1615...1110987..43..0opcode 0x38D A B reservedopcode 0x3reservedopcode 0xb6 bits5 bits5 bits5 bits1 bits2 bits4 bits4bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 82 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.nopNo Operationl.nop
31......2423......1615..............0opcode 0x15reservedK 8 bits8 bits16bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 83 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.orOrl.or
31....2625...2120...1615...1110987..43..0opcode 0x38D A B reservedopcode 0x0reservedopcode 0x46 bits5 bits5 bits5 bits1 bits2 bits4 bits4bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 84 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.oriOr with Immediate Half Wordl.ori
31....2625...2120...1615..............0opcode 0x2aD A K 6 bits5 bits5 bits16bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 85 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.psyncPipeline Syncronizationl.psync
31..............................0opcode 0x2280000032bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 86 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.rfeReturn From Exceptionl.rfe
31....2625........................0opcode 0x9reserved6 bits26bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 87 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.rorRotate Rightl.ror
31....2625...2120...1615...11109..6543..0opcode 0x38D A B reservedopcode 0x3reservedopcode 0x86 bits5 bits5 bits5 bits1 bits4 bits2 bits4bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 88 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.roriRotate Right with Immediatel.rori
31....2625...2120...1615......8765....0opcode 0x2eD A reservedopcode 0x3L 6 bits5 bits5 bits8 bits2 bits6bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 89 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sbStore Bytel.sb
31....2625...2120...1615...1110.........0opcode 0x36I A B I 6 bits5 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 90 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sdStore Double Wordl.sd
31....2625...2120...1615...1110.........0opcode 0x34I A B I 6 bits5 bits5 bits5 bits11bits
Instruction ClassORBIS64 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 91 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfeqSet Flag if Equall.sfeq
31.........2120...1615...1110.........0opcode 0x720A B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 92 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfeqiSet Flag if Equal Immediatel.sfeqi
31.........2120...1615..............0opcode 0x5e0A I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 93 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfgesSet Flag if Greater or Equal Than Signedl.sfges
31.........2120...1615...1110.........0opcode 0x72bA B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 94 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfgesiSet Flag if Greater or Equal Than Immediate Signedl.sfgesi
31.........2120...1615..............0opcode 0x5ebA I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 95 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfgeuSet Flag if Greater or Equal Than Unsignedl.sfgeu
31.........2120...1615...1110.........0opcode 0x723A B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 96 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfgeuiSet Flag if Greater or Equal Than Immediate Unsignedl.sfgeui
31.........2120...1615..............0opcode 0x5e3A I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 97 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfgtsSet Flag if Greater Than Signedl.sfgts
31.........2120...1615...1110.........0opcode 0x72aA B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 98 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfgtsiSet Flag if Greater Than Immediate Signedl.sfgtsi
31.........2120...1615..............0opcode 0x5eaA I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 99 of  NUMPAGES 340 

OpenCores      OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfgtuSet Flag if Greater Than Unsignedl.sfgtu
31.........2120...1615...1110.........0opcode 0x722A B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 100 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfgtuiSet Flag if Greater Than Immediate Unsignedl.sfgtui
31.........2120...1615..............0opcode 0x5e2A I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 101 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sflesSet Flag if Less or Equal Than Signedl.sfles
31.........2120...1615...1110.........0opcode 0x72dA B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 102 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sflesiSet Flag if Less or Equal Than Immediate Signedl.sflesi
31.........2120...1615..............0opcode 0x5edA I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 103 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfleuSet Flag if Less or Equal Than Unsignedl.sfleu
31.........2120...1615...1110.........0opcode 0x725A B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 104 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfleuiSet Flag if Less or Equal Than Immediate Unsignedl.sfleui
31.........2120...1615..............0opcode 0x5e5A I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 105 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfltsSet Flag if Less Than Signedl.sflts
31.........2120...1615...1110.........0opcode 0x72cA B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 106 of  NUMPAGES 333 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfltsiSet Flag if Less Than Immediate Signedl.sfltsi
31.........2120...1615..............0opcode 0x5ecA I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 107 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfltuSet Flag if Less Than Unsignedl.sfltu
31.........2120...1615...1110.........0opcode 0x724A B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 108 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfltuiSet Flag if Less Than Immediate Unsignedl.sfltui
31.........2120...1615..............0opcode 0x5e4A I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 109 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfneSet Flag if Not Equall.sfne
31.........2120...1615...1110.........0opcode 0x721A B reserved11 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 110 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sfneiSet Flag if Not Equal Immediatel.sfnei
31.........2120...1615..............0opcode 0x5e1A I 11 bits5 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 111 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.shStore Half Wordl.sh
31....2625...2120...1615...1110.........0opcode 0x37I A B I 6 bits5 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 112 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sllShift Left Logicall.sll
31....2625...2120...1615...11109..6543..0opcode 0x38D A B reservedopcode 0x0reservedopcode 0x86 bits5 bits5 bits5 bits1 bits4 bits2 bits4bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 113 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.slliShift Left Logical with Immediatel.slli
31....2625...2120...1615......8765....0opcode 0x2eD A reservedopcode 0x0L 6 bits5 bits5 bits8 bits2 bits6bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 114 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sraShift Right Arithmeticl.sra
31....2625...2120...1615...11109..6543..0opcode 0x38D A B reservedopcode 0x2reservedopcode 0x86 bits5 bits5 bits5 bits1 bits4 bits2 bits4bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 115 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sraiShift Right Arithmetic with Immediatel.srai
31....2625...2120...1615......8765....0opcode 0x2eD A reservedopcode 0x2L 6 bits5 bits5 bits8 bits2 bits6bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 116 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.srlShift Right Logicall.srl
31....2625...2120...1615...11109..6543..0opcode 0x38D A B reservedopcode 0x1reservedopcode 0x86 bits5 bits5 bits5 bits1 bits4 bits2 bits4bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 117 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.srliShift Right Logical with Immediatel.srli
31....2625...2120...1615......8765....0opcode 0x2eD A reservedopcode 0x1L 6 bits5 bits5 bits8 bits2 bits6bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 118 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.subSubtract Signedl.sub
31....2625...2120...1615...1110987..43..0opcode 0x38D A B reservedopcode 0x0reservedopcode 0x26 bits5 bits5 bits5 bits1 bits2 bits4 bits4bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 119 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.swStore Single Wordl.sw
31....2625...2120...1615...1110.........0opcode 0x35I A B I 6 bits5 bits5 bits5 bits11bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 120 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.sysSystem Calll.sys
31..............1615..............0opcode 0x2000K 16 bits16bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 121 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.trapTrapl.trap
31..............1615..............0opcode 0x2100K 16 bits16bits
Instruction ClassORBIS32 II HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 122 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.xorExclusive Orl.xor
31....2625...2120...1615...1110987..43..0opcode 0x38D A B reservedopcode 0x0reservedopcode 0x56 bits5 bits5 bits5 bits1 bits2 bits4 bits4bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 123 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightl.xoriExclusive Or with Immediate Half Wordl.xori
31....2625...2120...1615..............0opcode 0x2bD A I 6 bits5 bits5 bits16bits
Instruction ClassORBIS32 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 124 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.add.dAdd Floating-Point Double-Precisionlf.add.d
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x106 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 125 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.add.sAdd Floating-Point Single-Precisionlf.add.s
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x06 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 126 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.cust1.dReserved for ORFPX64 Custom Instructionslf.cust1.d
31....2625...2120...1615...1110.87..43..0opcode 0x32reservedA B reservedopcode 0xereserved6 bits5 bits5 bits5 bits3 bits4 bits4bits
Instruction ClassORFPX64 II HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 127 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.cust1.sReserved for ORFPX32 Custom Instructionslf.cust1.s
31....2625...2120...1615...1110.87..43..0opcode 0x32reservedA B reservedopcode 0xdreserved6 bits5 bits5 bits5 bits3 bits4 bits4bits
Instruction ClassORFPX32 II HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 128 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.div.dDivide Floating-Point Double-Precisionlf.div.d
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x136 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 II HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 129 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.div.sDivide Floating-Point Single-Precisionlf.div.s
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x36 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 II HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 130 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.ftoi.dFloating-Point Double-Precision To Integerlf.ftoi.d
31....2625...2120...1615...1110.87......0opcode 0x32D A opcode 0x0reservedopcode 0x156 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 131 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.ftoi.sFloating-Point Single-Precision To Integerlf.ftoi.s
31....2625...2120...1615...1110.87......0opcode 0x32D A opcode 0x0reservedopcode 0x56 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 132 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.itof.dInteger To Floating-Point Double-Precisionlf.itof.d
31....2625...2120...1615...1110.87......0opcode 0x32D A opcode 0x0reservedopcode 0x146 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 133 of  NUMPAGES 333 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.itof.sInteger To Floating-Point Single-Precisionlf.itof.s
31....2625...2120...1615...1110.87......0opcode 0x32D A opcode 0x0reservedopcode 0x46 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 134 of  NUMPAGES 333 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.madd.dMultiply and Add Floating-Point Double-Precisionlf.madd.d
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x176 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 II HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 135 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.madd.sMultiply and Add Floating-Point Single-Precisionlf.madd.s
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x76 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 II HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 136 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.mul.dMultiply Floating-Point Double-Precisionlf.mul.d
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x126 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 137 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.mul.sMultiply Floating-Point Single-Precisionlf.mul.s
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x26 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 138 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.rem.dRemainder Floating-Point Double-Precisionlf.rem.d
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x166 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 II HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 139 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.rem.sRemainder Floating-Point Single-Precisionlf.rem.s
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x66 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 II HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 140 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfeq.dSet Flag if Equal Floating-Point Double-Precisionlf.sfeq.d
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0x186 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 141 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfeq.sSet Flag if Equal Floating-Point Single-Precisionlf.sfeq.s
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0x86 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 142 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfge.dSet Flag if Greater or Equal Than Floating-Point Double-Precisionlf.sfge.d
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0x1b6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 143 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfge.sSet Flag if Greater or Equal Than Floating-Point Single-Precisionlf.sfge.s
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0xb6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 144 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfgt.dSet Flag if Greater Than Floating-Point Double-Precisionlf.sfgt.d
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0x1a6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 145 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfgt.sSet Flag if Greater Than Floating-Point Single-Precisionlf.sfgt.s
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0xa6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 146 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfle.dSet Flag if Less or Equal Than Floating-Point Double-Precisionlf.sfle.d
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0x1d6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 147 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfle.sSet Flag if Less or Equal Than Floating-Point Single-Precisionlf.sfle.s
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0xd6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 148 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sflt.dSet Flag if Less Than Floating-Point Double-Precisionlf.sflt.d
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0x1c6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 149 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sflt.sSet Flag if Less Than Floating-Point Single-Precisionlf.sflt.s
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0xc6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 150 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfne.dSet Flag if Not Equal Floating-Point Double-Precisionlf.sfne.d
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0x196 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 151 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sfne.sSet Flag if Not Equal Floating-Point Single-Precisionlf.sfne.s
31....2625...2120...1615...1110.87......0opcode 0x32reservedA B reservedopcode 0x96 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 152 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sub.dSubtract Floating-Point Double-Precisionlf.sub.d
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x116 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 153 of  NUMPAGES 333 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlf.sub.sSubtract Floating-Point Single-Precisionlf.sub.s
31....2625...2120...1615...1110.87......0opcode 0x32D A B reservedopcode 0x16 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORFPX32 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 154 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.add.bVector Byte Elements Add Signedlv.add.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x306 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 155 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.add.hVector Half-Word Elements Add Signedlv.add.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x316 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 156 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.adds.bVector Byte Elements Add Signed Saturatedlv.adds.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x326 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 157 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.adds.hVector Half-Word Elements Add Signed Saturatedlv.adds.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x336 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 158 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.addu.bVector Byte Elements Add Unsignedlv.addu.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x346 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 159 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.addu.hVector Half-Word Elements Add Unsignedlv.addu.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x356 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 160 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.addus.bVector Byte Elements Add Unsigned Saturatedlv.addus.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x366 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 161 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.addus.hVector Half-Word Elements Add Unsigned Saturatedlv.addus.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x376 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 162 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_eq.bVector Byte Elements All Equallv.all_eq.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x106 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 163 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_eq.hVector Half-Word Elements All Equallv.all_eq.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x116 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 164 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_ge.bVector Byte Elements All Greater Than or Equal Tolv.all_ge.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x126 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 165 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_ge.hVector Half-Word Elements All Greater Than or Equal Tolv.all_ge.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x136 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 166 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_gt.bVector Byte Elements All Greater Thanlv.all_gt.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x146 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 167 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_gt.hVector Half-Word Elements All Greater Thanlv.all_gt.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x156 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 168 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_le.bVector Byte Elements All Less Than or Equal Tolv.all_le.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x166 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 169 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_le.hVector Half-Word Elements All Less Than or Equal Tolv.all_le.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x176 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 170 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_lt.bVector Byte Elements All Less Thanlv.all_lt.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x186 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 171 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_lt.hVector Half-Word Elements All Less Thanlv.all_lt.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x196 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 172 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_ne.bVector Byte Elements All Not Equallv.all_ne.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x1a6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 173 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.all_ne.hVector Half-Word Elements All Not Equallv.all_ne.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x1b6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 174 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.andVector Andlv.and
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x386 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 175 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_eq.bVector Byte Elements Any Equallv.any_eq.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x206 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 176 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_eq.hVector Half-Word Elements Any Equallv.any_eq.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x216 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 177 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_ge.bVector Byte Elements Any Greater Than or Equal Tolv.any_ge.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x226 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 178 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_ge.hVector Half-Word Elements Any Greater Than or Equal Tolv.any_ge.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x236 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 179 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_gt.bVector Byte Elements Any Greater Thanlv.any_gt.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x246 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 180 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_gt.hVector Half-Word Elements Any Greater Thanlv.any_gt.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x256 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 181 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_le.bVector Byte Elements Any Less Than or Equal Tolv.any_le.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x266 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 182 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_le.hVector Half-Word Elements Any Less Than or Equal Tolv.any_le.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x276 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 183 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_lt.bVector Byte Elements Any Less Thanlv.any_lt.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x286 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 184 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_lt.hVector Half-Word Elements Any Less Thanlv.any_lt.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x296 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 185 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_ne.bVector Byte Elements Any Not Equallv.any_ne.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x2a6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 186 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.any_ne.hVector Half-Word Elements Any Not Equallv.any_ne.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x2b6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 187 of  NUMPAGES 333 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.avg.bVector Byte Elements Averagelv.avg.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x396 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 188 of  NUMPAGES 333 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.avg.hVector Half-Word Elements Averagelv.avg.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x3a6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 189 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_eq.bVector Byte Elements Compare Equallv.cmp_eq.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x406 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 190 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_eq.hVector Half-Word Elements Compare Equallv.cmp_eq.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x416 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 191 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_ge.bVector Byte Elements Compare Greater Than or Equal Tolv.cmp_ge.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x426 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 192 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_ge.hVector Half-Word Elements Compare Greater Than or Equal Tolv.cmp_ge.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x436 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 193 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_gt.bVector Byte Elements Compare Greater Thanlv.cmp_gt.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x446 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 194 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_gt.hVector Half-Word Elements Compare Greater Thanlv.cmp_gt.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x456 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 195 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_le.bVector Byte Elements Compare Less Than or Equal Tolv.cmp_le.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x466 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 196 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_le.hVector Half-Word Elements Compare Less Than or Equal Tolv.cmp_le.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x476 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 197 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_lt.bVector Byte Elements Compare Less Thanlv.cmp_lt.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x486 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 198 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_lt.hVector Half-Word Elements Compare Less Thanlv.cmp_lt.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x496 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 199 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_ne.bVector Byte Elements Compare Not Equallv.cmp_ne.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x4a6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 200 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cmp_ne.hVector Half-Word Elements Compare Not Equallv.cmp_ne.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x4b6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 201 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cust1Reserved for Custom Vector Instructionslv.cust1
31....2625................87..43..0opcode 0xareservedopcode 0xcreserved6 bits18 bits4 bits4bits
Instruction ClassORVDX64 II HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 202 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cust2Reserved for Custom Vector Instructionslv.cust2
31....2625................87..43..0opcode 0xareservedopcode 0xdreserved6 bits18 bits4 bits4bits
Instruction ClassORVDX64 II HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 203 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cust3Reserved for Custom Vector Instructionslv.cust3
31....2625................87..43..0opcode 0xareservedopcode 0xereserved6 bits18 bits4 bits4bits
Instruction ClassORVDX64 II HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 204 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.cust4Reserved for Custom Vector Instructionslv.cust4
31....2625................87..43..0opcode 0xareservedopcode 0xfreserved6 bits18 bits4 bits4bits
Instruction ClassORVDX64 II HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 205 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.madds.hVector Half-Word Elements Multiply Add Signed Saturatedlv.madds.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x546 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 206 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.max.bVector Byte Elements Maximumlv.max.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x556 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 208 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.max.hVector Half-Word Elements Maximumlv.max.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x566 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 209 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.merge.bVector Byte Elements Mergelv.merge.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x576 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 210 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.merge.hVector Half-Word Elements Mergelv.merge.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x586 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 211 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.min.bVector Byte Elements Minimumlv.min.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x596 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 213 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.min.hVector Half-Word Elements Minimumlv.min.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x5a6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 214 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.msubs.hVector Half-Word Elements Multiply Subtract Signed Saturatedlv.msubs.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x5b6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 215 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.muls.hVector Half-Word Elements Multiply Signed Saturatedlv.muls.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x5c6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 II HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 216 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.nandVector Not Andlv.nand
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x5d6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 217 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.norVector Not Orlv.nor
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x5e6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 218 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.orVector Orlv.or
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x5f6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 219 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.pack.bVector Byte Elements Packlv.pack.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x606 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 221 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.pack.hVector Half-word Elements Packlv.pack.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x616 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 222 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.packs.bVector Byte Elements Pack Signed Saturatedlv.packs.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x626 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 224 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.packs.hVector Half-word Elements Pack Signed Saturatedlv.packs.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x636 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 225 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.packus.bVector Byte Elements Pack Unsigned Saturatedlv.packus.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x646 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org     Rev 1.1          PAGE 227 of  NUMPAGES 333 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.packus.hVector Half-word Elements Pack Unsigned Saturatedlv.packus.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x656 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 228 of  NUMPAGES 333 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.perm.nVector Nibble Elements Permutelv.perm.n
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x666 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 230 of  NUMPAGES 333 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.rl.bVector Byte Elements Rotate Leftlv.rl.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x676 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 231 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.rl.hVector Half-Word Elements Rotate Leftlv.rl.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x686 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 232 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.sllVector Shift Left Logicallv.sll
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x6b6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 233 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.sll.bVector Byte Elements Shift Left Logicallv.sll.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x696 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 234 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.sll.hVector Half-Word Elements Shift Left Logicallv.sll.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x6a6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 235 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.sra.bVector Byte Elements Shift Right Arithmeticlv.sra.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x6e6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org    Rev 1.1          PAGE 236 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.sra.hVector Half-Word Elements Shift Right Arithmeticlv.sra.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x6f6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 237 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.srlVector Shift Right Logicallv.srl
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x706 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 238 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.srl.bVector Byte Elements Shift Right Logicallv.srl.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x6c6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 239 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.srl.hVector Half-Word Elements Shift Right Logicallv.srl.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x6d6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 240 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.sub.bVector Byte Elements Subtract Signedlv.sub.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x716 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 241 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.sub.hVector Half-Word Elements Subtract Signedlv.sub.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x726 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 242 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.subs.bVector Byte Elements Subtract Signed Saturatedlv.subs.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x736 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 243 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.subs.hVector Half-Word Elements Subtract Signed Saturatedlv.subs.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x746 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 244 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.subu.bVector Byte Elements Subtract Unsignedlv.subu.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x756 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org       Rev 1.1          PAGE 245 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.subu.hVector Half-Word Elements Subtract Unsignedlv.subu.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x766 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org  Rev 1.1          PAGE 246 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.subus.bVector Byte Elements Subtract Unsigned Saturatedlv.subus.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x776 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org   Rev 1.1          PAGE 247 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.subus.hVector Half-Word Elements Subtract Unsigned Saturatedlv.subus.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x786 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 248 of  NUMPAGES 340 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.unpack.bVector Byte Elements Unpacklv.unpack.b
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x796 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org      Rev 1.1          PAGE 249 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.unpack.hVector Half-Word Elements Unpacklv.unpack.h
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x7a6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org Rev 1.1          PAGE 250 of  NUMPAGES 334 

OpenCores     OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" November 16, 2005
LeftMiddle Middle Middle Middle Middle Middle Middle Middle Middle Middle Rightlv.xorVector Exclusive Orlv.xor
31....2625...2120...1615...1110.87......0opcode 0xaD A B reservedopcode 0x7b6 bits5 bits5 bits5 bits3 bits8bits
Instruction ClassORVDX64 I HYPERLINK "http://www.opencores.org/" www.opencores.org        Rev 1.1          PAGE 251 of  NUMPAGES 334 



OpenCores  OpenRISC 1000 Architecture Manual        TIME \@ "MMMM d, yyyy" november 16, 2005




HYPERLINK "http://www.opencores.org/"
www.opencores.org     Rev 1.3  PAGE 340 of  NUMPAGES 340






Instruction Set


ORBIS32


ORBIS64


ORVDX64


ORFPX32


ORFPX64

struct {
  short   S:9;
  int     J:9;
  char    C;
  short   T:9;
  short   U:9;
  char    D;
};


struct {
  char   C;
  double D;
  short  S;
};


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