; Renesas M32R CPU description. -*- Scheme -*-
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; Renesas M32R CPU description. -*- Scheme -*-
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;
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;
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; Copyright 1998, 1999, 2000, 2001, 2003, 2007 Free Software Foundation, Inc.
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; Copyright 1998, 1999, 2000, 2001, 2003, 2007 Free Software Foundation, Inc.
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;
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;
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; Contributed by Red Hat Inc; developed under contract from Mitsubishi
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; Contributed by Red Hat Inc; developed under contract from Mitsubishi
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; Electric Corporation.
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; Electric Corporation.
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;
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;
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; This file is part of the GNU Binutils.
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; This file is part of the GNU Binutils.
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;
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;
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; This program is free software; you can redistribute it and/or modify
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 3 of the License, or
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; the Free Software Foundation; either version 3 of the License, or
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; (at your option) any later version.
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; (at your option) any later version.
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;
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;
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; This program is distributed in the hope that it will be useful,
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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; GNU General Public License for more details.
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;
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;
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; You should have received a copy of the GNU General Public License
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, write to the Free Software
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; along with this program; if not, write to the Free Software
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; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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; MA 02110-1301, USA.
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; MA 02110-1301, USA.
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(include "simplify.inc")
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(include "simplify.inc")
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; FIXME: Delete sign extension of accumulator results.
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; FIXME: Delete sign extension of accumulator results.
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; Sign extension is done when accumulator is read.
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; Sign extension is done when accumulator is read.
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; define-arch must appear first
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; define-arch must appear first
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(define-arch
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(define-arch
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(name m32r) ; name of cpu family
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(name m32r) ; name of cpu family
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(comment "Renesas M32R")
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(comment "Renesas M32R")
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(default-alignment aligned)
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(default-alignment aligned)
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(insn-lsb0? #f)
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(insn-lsb0? #f)
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(machs m32r m32rx m32r2)
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(machs m32r m32rx m32r2)
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(isas m32r)
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(isas m32r)
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)
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)
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; Attributes.
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; Attributes.
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; An attribute to describe which pipeline an insn runs in.
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; An attribute to describe which pipeline an insn runs in.
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; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.
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; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.
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; These instructions have O attribute for m32rx and OS attribute for m32r2.
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; These instructions have O attribute for m32rx and OS attribute for m32r2.
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(define-attr
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(define-attr
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(for insn)
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(for insn)
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(type enum)
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(type enum)
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(name PIPE)
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(name PIPE)
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(comment "parallel execution pipeline selection")
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(comment "parallel execution pipeline selection")
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(values NONE O S OS O_OS)
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(values NONE O S OS O_OS)
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)
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)
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; A derived attribute that says which insns can be executed in parallel
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; A derived attribute that says which insns can be executed in parallel
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; with others. This is a required attribute for architectures with
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; with others. This is a required attribute for architectures with
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; parallel execution.
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; parallel execution.
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(define-attr
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(define-attr
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(for insn)
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(for insn)
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(type enum)
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(type enum)
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(name PARALLEL)
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(name PARALLEL)
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(attrs META) ; do not define in any generated file for now
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(attrs META) ; do not define in any generated file for now
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(values NO YES)
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(values NO YES)
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(default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))
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(default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))
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)
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)
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; Instruction set parameters.
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; Instruction set parameters.
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(define-isa
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(define-isa
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(name m32r)
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(name m32r)
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; This is 32 because 16 bit insns always appear as pairs.
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; This is 32 because 16 bit insns always appear as pairs.
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; ??? See if this can go away. It's only used by the disassembler (right?)
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; ??? See if this can go away. It's only used by the disassembler (right?)
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; to decide how long an unknown insn is. One value isn't sufficient (e.g. if
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; to decide how long an unknown insn is. One value isn't sufficient (e.g. if
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; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)
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; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)
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(default-insn-bitsize 32)
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(default-insn-bitsize 32)
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; Number of bytes of insn we can initially fetch.
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; Number of bytes of insn we can initially fetch.
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; The M32R is tricky in that insns are either two 16-bit insns
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; The M32R is tricky in that insns are either two 16-bit insns
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; (executed sequentially or in parallel) or one 32-bit insn.
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; (executed sequentially or in parallel) or one 32-bit insn.
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; So on one hand the base insn size is 16 bits, but on another it's 32.
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; So on one hand the base insn size is 16 bits, but on another it's 32.
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; 32 is chosen because:
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; 32 is chosen because:
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; - if the chip were ever bi-endian it is believed that the byte order would
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; - if the chip were ever bi-endian it is believed that the byte order would
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; be based on 32 bit quantities
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; be based on 32 bit quantities
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; - 32 bit insns are always aligned on 32 bit boundaries
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; - 32 bit insns are always aligned on 32 bit boundaries
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; - the pc will never stop on a 16 bit (and not 32 bit) boundary
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; - the pc will never stop on a 16 bit (and not 32 bit) boundary
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; [well actually it can, but there are no branches to such places]
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; [well actually it can, but there are no branches to such places]
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(base-insn-bitsize 32)
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(base-insn-bitsize 32)
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; Used in computing bit numbers.
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; Used in computing bit numbers.
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(default-insn-word-bitsize 32)
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(default-insn-word-bitsize 32)
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; The m32r fetches 2 insns at a time.
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; The m32r fetches 2 insns at a time.
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(liw-insns 2)
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(liw-insns 2)
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; While the m32r can execute insns in parallel, the base mach can't
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; While the m32r can execute insns in parallel, the base mach can't
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; (other than nop). The base mach is greatly handicapped by this, but
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; (other than nop). The base mach is greatly handicapped by this, but
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; we still need to cleanly handle it.
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; we still need to cleanly handle it.
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(parallel-insns 2)
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(parallel-insns 2)
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; Initial bitnumbers to decode insns by.
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; Initial bitnumbers to decode insns by.
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(decode-assist (0 1 2 3 8 9 10 11))
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(decode-assist (0 1 2 3 8 9 10 11))
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; Classification of instructions that fit in the various frames.
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; Classification of instructions that fit in the various frames.
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; wip, not currently used
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; wip, not currently used
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(insn-types (long ; name
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(insn-types (long ; name
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31 ; length
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31 ; length
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(eq-attr (current-insn) LENGTH 31) ; matching insns
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(eq-attr (current-insn) LENGTH 31) ; matching insns
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(0 1 2 7 8 9 10) ; decode-assist
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(0 1 2 7 8 9 10) ; decode-assist
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)
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)
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(short
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(short
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15
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15
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(eq-attr (current-insn) LENGTH 15) ; matching insns
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(eq-attr (current-insn) LENGTH 15) ; matching insns
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(0 1 2 7 8 9 10)
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(0 1 2 7 8 9 10)
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)
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)
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)
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)
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; Instruction framing.
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; Instruction framing.
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; Each m32r insn is either one 32 bit insn, two 16 bit insns executed
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; Each m32r insn is either one 32 bit insn, two 16 bit insns executed
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; serially (left->right), or two 16 bit insns executed parallelly.
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; serially (left->right), or two 16 bit insns executed parallelly.
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; wip, not currently used
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; wip, not currently used
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(frame long32 ; name
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(frame long32 ; name
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((long)) ; list of insns in frame, plus constraint
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((long)) ; list of insns in frame, plus constraint
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"$0" ; assembler
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"$0" ; assembler
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(+ (1 1) (31 $0)) ; value
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(+ (1 1) (31 $0)) ; value
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(sequence () (execute $0)) ; action
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(sequence () (execute $0)) ; action
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)
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)
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(frame serial2x16
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(frame serial2x16
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((short)
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((short)
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(short))
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(short))
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"$0 -> $1"
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"$0 -> $1"
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(+ (1 0) (15 $0) (1 0) (15 $1))
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(+ (1 0) (15 $0) (1 0) (15 $1))
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(sequence ()
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(sequence ()
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(execute $0)
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(execute $0)
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(execute $1))
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(execute $1))
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)
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)
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(frame parallel2x16
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(frame parallel2x16
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((short (eq-attr (current-insn) PIPE "O,BOTH"))
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((short (eq-attr (current-insn) PIPE "O,BOTH"))
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(short (eq-attr (current-insn) PIPE "S,BOTH")))
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(short (eq-attr (current-insn) PIPE "S,BOTH")))
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"$0 || $1"
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"$0 || $1"
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(+ (1 0) (15 $0) (1 1) (15 $1))
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(+ (1 0) (15 $0) (1 1) (15 $1))
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(parallel ()
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(parallel ()
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(execute $0)
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(execute $0)
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(execute $1))
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(execute $1))
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)
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)
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)
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)
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; Cpu family definitions.
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; Cpu family definitions.
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; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
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; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
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; define-cpu.
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; define-cpu.
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; ??? Have define-arch provide defaults for architecture that define-cpu can
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; ??? Have define-arch provide defaults for architecture that define-cpu can
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; then override [reduces duplication in define-cpu].
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; then override [reduces duplication in define-cpu].
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; ??? Another way to go is to delete cpu-families entirely and have one mach
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; ??? Another way to go is to delete cpu-families entirely and have one mach
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; able to inherit things from another mach (would also need the ability to
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; able to inherit things from another mach (would also need the ability to
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; not only override specific inherited things but also disable some,
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; not only override specific inherited things but also disable some,
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; e.g. if an insn wasn't supported).
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; e.g. if an insn wasn't supported).
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(define-cpu
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(define-cpu
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; cpu names must be distinct from the architecture name and machine names.
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; cpu names must be distinct from the architecture name and machine names.
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; The "b" suffix stands for "base" and is the convention.
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; The "b" suffix stands for "base" and is the convention.
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; The "f" suffix stands for "family" and is the convention.
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; The "f" suffix stands for "family" and is the convention.
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(name m32rbf)
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(name m32rbf)
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(comment "Renesas M32R base family")
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(comment "Renesas M32R base family")
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(endian either)
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(endian either)
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(word-bitsize 32)
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(word-bitsize 32)
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; Override isa spec (??? keeps things simpler, though it was more true
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; Override isa spec (??? keeps things simpler, though it was more true
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; in the early days and not so much now).
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; in the early days and not so much now).
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(parallel-insns 1)
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(parallel-insns 1)
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)
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)
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(define-cpu
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(define-cpu
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(name m32rxf)
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(name m32rxf)
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(comment "Renesas M32Rx family")
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(comment "Renesas M32Rx family")
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(endian either)
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(endian either)
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(word-bitsize 32)
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(word-bitsize 32)
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; Generated files have an "x" suffix.
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; Generated files have an "x" suffix.
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(file-transform "x")
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(file-transform "x")
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)
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)
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(define-cpu
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(define-cpu
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(name m32r2f)
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(name m32r2f)
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(comment "Renesas M32R2 family")
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(comment "Renesas M32R2 family")
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(endian either)
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(endian either)
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(word-bitsize 32)
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(word-bitsize 32)
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; Generated files have an "2" suffix.
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; Generated files have an "2" suffix.
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(file-transform "2")
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(file-transform "2")
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)
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)
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(define-mach
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(define-mach
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(name m32r)
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(name m32r)
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(comment "Generic M32R cpu")
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(comment "Generic M32R cpu")
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(cpu m32rbf)
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(cpu m32rbf)
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)
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)
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(define-mach
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(define-mach
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(name m32rx)
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(name m32rx)
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(comment "M32RX cpu")
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(comment "M32RX cpu")
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(cpu m32rxf)
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(cpu m32rxf)
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)
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)
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(define-mach
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(define-mach
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(name m32r2)
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(name m32r2)
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(comment "M32R2 cpu")
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(comment "M32R2 cpu")
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(cpu m32r2f)
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(cpu m32r2f)
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)
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)
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; Model descriptions.
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; Model descriptions.
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; The meaning of this value is wip but at the moment it's intended to describe
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; The meaning of this value is wip but at the moment it's intended to describe
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; the implementation (i.e. what -mtune=foo does in sparc gcc).
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; the implementation (i.e. what -mtune=foo does in sparc gcc).
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;
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;
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; Notes while wip:
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; Notes while wip:
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; - format of pipeline entry:
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; - format of pipeline entry:
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; (pipeline name (stage1-name ...) (stage2-name ...) ...)
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; (pipeline name (stage1-name ...) (stage2-name ...) ...)
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; The contents of a stage description is wip.
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; The contents of a stage description is wip.
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; - each mach must have at least one model
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; - each mach must have at least one model
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; - the default model must be the first one
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; - the default model must be the first one
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;- maybe have `retire' support update total cycle count to handle current
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;- maybe have `retire' support update total cycle count to handle current
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; parallel insn cycle counting problems
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; parallel insn cycle counting problems
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(define-model
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(define-model
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(name m32r/d) (comment "m32r/d") (attrs)
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(name m32r/d) (comment "m32r/d") (attrs)
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(mach m32r)
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(mach m32r)
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;(prefetch)
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;(prefetch)
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;(retire)
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;(retire)
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(pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
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(pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
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(pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
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(pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
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; `state' is a list of variables for recording model state
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; `state' is a list of variables for recording model state
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(state
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(state
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; bit mask of h-gr registers, =1 means value being loaded from memory
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; bit mask of h-gr registers, =1 means value being loaded from memory
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(h-gr UINT)
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(h-gr UINT)
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)
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)
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(unit u-exec "Execution Unit" ()
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(unit u-exec "Execution Unit" ()
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1 1 ; issue done
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1 1 ; issue done
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() ; state
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() ; state
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((sr INT -1) (dr INT -1)) ; inputs
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((sr INT -1) (dr INT -1)) ; inputs
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((dr INT -1)) ; outputs
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((dr INT -1)) ; outputs
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() ; profile action (default)
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() ; profile action (default)
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)
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)
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(unit u-cmp "Compare Unit" ()
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(unit u-cmp "Compare Unit" ()
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1 1 ; issue done
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1 1 ; issue done
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() ; state
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() ; state
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((src1 INT -1) (src2 INT -1)) ; inputs
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((src1 INT -1) (src2 INT -1)) ; inputs
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() ; outputs
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() ; outputs
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() ; profile action (default)
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() ; profile action (default)
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)
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)
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(unit u-mac "Multiply/Accumulate Unit" ()
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(unit u-mac "Multiply/Accumulate Unit" ()
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1 1 ; issue done
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1 1 ; issue done
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() ; state
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() ; state
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((src1 INT -1) (src2 INT -1)) ; inputs
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((src1 INT -1) (src2 INT -1)) ; inputs
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() ; outputs
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() ; outputs
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() ; profile action (default)
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() ; profile action (default)
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)
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)
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(unit u-cti "Branch Unit" ()
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(unit u-cti "Branch Unit" ()
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1 1 ; issue done
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1 1 ; issue done
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() ; state
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() ; state
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((sr INT -1)) ; inputs
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((sr INT -1)) ; inputs
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((pc)) ; outputs
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((pc)) ; outputs
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() ; profile action (default)
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() ; profile action (default)
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)
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)
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(unit u-load "Memory Load Unit" ()
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(unit u-load "Memory Load Unit" ()
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1 1 ; issue done
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1 1 ; issue done
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() ; state
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() ; state
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((sr INT)
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((sr INT)
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;(ld-mem AI)
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;(ld-mem AI)
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) ; inputs
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) ; inputs
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((dr INT)) ; outputs
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((dr INT)) ; outputs
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() ; profile action (default)
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() ; profile action (default)
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)
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)
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(unit u-store "Memory Store Unit" ()
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(unit u-store "Memory Store Unit" ()
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1 1 ; issue done
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1 1 ; issue done
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() ; state
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() ; state
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((src1 INT) (src2 INT)) ; inputs
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((src1 INT) (src2 INT)) ; inputs
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() ; ((st-mem AI)) ; outputs
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() ; ((st-mem AI)) ; outputs
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() ; profile action (default)
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() ; profile action (default)
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)
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)
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)
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)
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|
|
(define-model
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(define-model
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(name test) (comment "test") (attrs)
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(name test) (comment "test") (attrs)
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(mach m32r)
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(mach m32r)
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(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
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(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
|
(unit u-exec "Execution Unit" ()
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(unit u-exec "Execution Unit" ()
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1 1 ; issue done
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1 1 ; issue done
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() () () ())
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() () () ())
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)
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)
|
|
|
; Each mach must have at least one model.
|
; Each mach must have at least one model.
|
|
|
(define-model
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(define-model
|
(name m32rx) (comment "m32rx") (attrs)
|
(name m32rx) (comment "m32rx") (attrs)
|
(mach m32rx)
|
(mach m32rx)
|
|
|
; ??? It's 6 stages but I forget the details right now.
|
; ??? It's 6 stages but I forget the details right now.
|
(pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
|
(pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
|
(pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
|
(pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
|
(pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
|
(pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
|
|
|
(unit u-exec "Execution Unit" ()
|
(unit u-exec "Execution Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
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() ; state
|
((sr INT -1) (dr INT -1)) ; inputs
|
((sr INT -1) (dr INT -1)) ; inputs
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((dr INT -1)) ; outputs
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((dr INT -1)) ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-cmp "Compare Unit" ()
|
(unit u-cmp "Compare Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((src1 INT -1) (src2 INT -1)) ; inputs
|
((src1 INT -1) (src2 INT -1)) ; inputs
|
() ; outputs
|
() ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-mac "Multiply/Accumulate Unit" ()
|
(unit u-mac "Multiply/Accumulate Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((src1 INT -1) (src2 INT -1)) ; inputs
|
((src1 INT -1) (src2 INT -1)) ; inputs
|
() ; outputs
|
() ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-cti "Branch Unit" ()
|
(unit u-cti "Branch Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((sr INT -1)) ; inputs
|
((sr INT -1)) ; inputs
|
((pc)) ; outputs
|
((pc)) ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-load "Memory Load Unit" ()
|
(unit u-load "Memory Load Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((sr INT)) ; inputs
|
((sr INT)) ; inputs
|
((dr INT)) ; outputs
|
((dr INT)) ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-store "Memory Store Unit" ()
|
(unit u-store "Memory Store Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((src1 INT) (src2 INT)) ; inputs
|
((src1 INT) (src2 INT)) ; inputs
|
() ; outputs
|
() ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
)
|
)
|
|
|
(define-model
|
(define-model
|
(name m32r2) (comment "m32r2") (attrs)
|
(name m32r2) (comment "m32r2") (attrs)
|
(mach m32r2)
|
(mach m32r2)
|
|
|
; ??? It's 6 stages but I forget the details right now.
|
; ??? It's 6 stages but I forget the details right now.
|
(pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
|
(pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
|
(pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
|
(pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
|
(pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
|
(pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
|
|
|
(unit u-exec "Execution Unit" ()
|
(unit u-exec "Execution Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((sr INT -1) (dr INT -1)) ; inputs
|
((sr INT -1) (dr INT -1)) ; inputs
|
((dr INT -1)) ; outputs
|
((dr INT -1)) ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-cmp "Compare Unit" ()
|
(unit u-cmp "Compare Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((src1 INT -1) (src2 INT -1)) ; inputs
|
((src1 INT -1) (src2 INT -1)) ; inputs
|
() ; outputs
|
() ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-mac "Multiply/Accumulate Unit" ()
|
(unit u-mac "Multiply/Accumulate Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((src1 INT -1) (src2 INT -1)) ; inputs
|
((src1 INT -1) (src2 INT -1)) ; inputs
|
() ; outputs
|
() ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-cti "Branch Unit" ()
|
(unit u-cti "Branch Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((sr INT -1)) ; inputs
|
((sr INT -1)) ; inputs
|
((pc)) ; outputs
|
((pc)) ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-load "Memory Load Unit" ()
|
(unit u-load "Memory Load Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((sr INT)) ; inputs
|
((sr INT)) ; inputs
|
((dr INT)) ; outputs
|
((dr INT)) ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
(unit u-store "Memory Store Unit" ()
|
(unit u-store "Memory Store Unit" ()
|
1 1 ; issue done
|
1 1 ; issue done
|
() ; state
|
() ; state
|
((src1 INT) (src2 INT)) ; inputs
|
((src1 INT) (src2 INT)) ; inputs
|
() ; outputs
|
() ; outputs
|
() ; profile action (default)
|
() ; profile action (default)
|
)
|
)
|
)
|
)
|
|
|
; The instruction fetch/execute cycle.
|
; The instruction fetch/execute cycle.
|
; This is split into two parts as sometimes more than one instruction is
|
; This is split into two parts as sometimes more than one instruction is
|
; decoded at once.
|
; decoded at once.
|
; The `const SI' argument to decode/execute is used to distinguish
|
; The `const SI' argument to decode/execute is used to distinguish
|
; multiple instructions processed at the same time (e.g. m32r).
|
; multiple instructions processed at the same time (e.g. m32r).
|
;
|
;
|
; ??? This is wip, and not currently used.
|
; ??? This is wip, and not currently used.
|
; ??? Needs to be moved to define-isa.
|
; ??? Needs to be moved to define-isa.
|
|
|
; This is how to fetch and decode an instruction.
|
; This is how to fetch and decode an instruction.
|
|
|
;(define-extract
|
;(define-extract
|
; (sequence VOID
|
; (sequence VOID
|
; (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0))
|
; (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0))
|
; (sequence VOID
|
; (sequence VOID
|
; (set-quiet USI (scratch UHI insn1) (ifetch UHI pc))
|
; (set-quiet USI (scratch UHI insn1) (ifetch UHI pc))
|
; (decode VOID pc (and UHI insn1 (const UHI #x7fff))
|
; (decode VOID pc (and UHI insn1 (const UHI #x7fff))
|
; (const SI 0)))
|
; (const SI 0)))
|
; (sequence VOID
|
; (sequence VOID
|
; (set-quiet USI (scratch USI insn) (ifetch USI pc))
|
; (set-quiet USI (scratch USI insn) (ifetch USI pc))
|
; (if VOID (ne USI (and USI insn (const USI #x80000000))
|
; (if VOID (ne USI (and USI insn (const USI #x80000000))
|
; (const USI 0))
|
; (const USI 0))
|
; (decode VOID pc (srl USI insn (const WI 16)) (const SI 0))
|
; (decode VOID pc (srl USI insn (const WI 16)) (const SI 0))
|
; (sequence VOID
|
; (sequence VOID
|
; ; ??? parallel support
|
; ; ??? parallel support
|
; (decode VOID pc (srl USI insn (const WI 16))
|
; (decode VOID pc (srl USI insn (const WI 16))
|
; (const SI 0))
|
; (const SI 0))
|
; (decode VOID (add AI pc (const AI 2))
|
; (decode VOID (add AI pc (const AI 2))
|
; (and USI insn (const WI #x7fff))
|
; (and USI insn (const WI #x7fff))
|
; (const SI 1))))))
|
; (const SI 1))))))
|
; )
|
; )
|
;)
|
;)
|
|
|
; This is how to execute a decoded instruction.
|
; This is how to execute a decoded instruction.
|
|
|
;(define-execute
|
;(define-execute
|
; (sequence VOID () ; () is empty option list
|
; (sequence VOID () ; () is empty option list
|
; ((AI new_pc))
|
; ((AI new_pc))
|
; (set AI new_pc (execute: AI (const 0)) #:quiet)
|
; (set AI new_pc (execute: AI (const 0)) #:quiet)
|
; (set AI pc new_pc #:direct)
|
; (set AI pc new_pc #:direct)
|
; )
|
; )
|
;)
|
;)
|
|
|
; FIXME: It might simplify things to separate the execute process from the
|
; FIXME: It might simplify things to separate the execute process from the
|
; one that updates the PC.
|
; one that updates the PC.
|
|
|
; Instruction fields.
|
; Instruction fields.
|
;
|
;
|
; Attributes:
|
; Attributes:
|
; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
|
; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
|
; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
|
; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
|
; RESERVED: bits are not used to decode insn, must be all 0
|
; RESERVED: bits are not used to decode insn, must be all 0
|
; RELOC: there is a relocation associated with this field (experiment)
|
; RELOC: there is a relocation associated with this field (experiment)
|
|
|
(define-attr
|
(define-attr
|
(for ifield operand)
|
(for ifield operand)
|
(type boolean)
|
(type boolean)
|
(name RELOC)
|
(name RELOC)
|
(comment "there is a reloc associated with this field (experiment)")
|
(comment "there is a reloc associated with this field (experiment)")
|
)
|
)
|
|
|
(dnf f-op1 "op1" () 0 4)
|
(dnf f-op1 "op1" () 0 4)
|
(dnf f-op2 "op2" () 8 4)
|
(dnf f-op2 "op2" () 8 4)
|
(dnf f-cond "cond" () 4 4)
|
(dnf f-cond "cond" () 4 4)
|
(dnf f-r1 "r1" () 4 4)
|
(dnf f-r1 "r1" () 4 4)
|
(dnf f-r2 "r2" () 12 4)
|
(dnf f-r2 "r2" () 12 4)
|
(df f-simm8 "simm8" () 8 8 INT #f #f)
|
(df f-simm8 "simm8" () 8 8 INT #f #f)
|
(df f-simm16 "simm16" () 16 16 INT #f #f)
|
(df f-simm16 "simm16" () 16 16 INT #f #f)
|
(dnf f-shift-op2 "shift op2" () 8 3)
|
(dnf f-shift-op2 "shift op2" () 8 3)
|
(dnf f-uimm3 "uimm3" () 5 3)
|
(dnf f-uimm3 "uimm3" () 5 3)
|
(dnf f-uimm4 "uimm4" () 12 4)
|
(dnf f-uimm4 "uimm4" () 12 4)
|
(dnf f-uimm5 "uimm5" () 11 5)
|
(dnf f-uimm5 "uimm5" () 11 5)
|
(dnf f-uimm8 "uimm8" () 8 8)
|
(dnf f-uimm8 "uimm8" () 8 8)
|
(dnf f-uimm16 "uimm16" () 16 16)
|
(dnf f-uimm16 "uimm16" () 16 16)
|
(dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24)
|
(dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24)
|
(dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16)
|
(dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16)
|
(df f-disp8 "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
|
(df f-disp8 "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
|
((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
|
((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
|
((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
|
((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
|
(df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT
|
(df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT
|
((value pc) (sra WI (sub WI value pc) (const 2)))
|
((value pc) (sra WI (sub WI value pc) (const 2)))
|
((value pc) (add WI (sll WI value (const 2)) pc)))
|
((value pc) (add WI (sll WI value (const 2)) pc)))
|
(df f-disp24 "disp24" (PCREL-ADDR RELOC) 8 24 INT
|
(df f-disp24 "disp24" (PCREL-ADDR RELOC) 8 24 INT
|
((value pc) (sra WI (sub WI value pc) (const 2)))
|
((value pc) (sra WI (sub WI value pc) (const 2)))
|
((value pc) (add WI (sll WI value (const 2)) pc)))
|
((value pc) (add WI (sll WI value (const 2)) pc)))
|
|
|
(dnf f-op23 "op2.3" () 9 3)
|
(dnf f-op23 "op2.3" () 9 3)
|
(dnf f-op3 "op3" () 14 2)
|
(dnf f-op3 "op3" () 14 2)
|
(dnf f-acc "acc" () 8 1)
|
(dnf f-acc "acc" () 8 1)
|
(dnf f-accs "accs" () 12 2)
|
(dnf f-accs "accs" () 12 2)
|
(dnf f-accd "accd" () 4 2)
|
(dnf f-accd "accd" () 4 2)
|
(dnf f-bits67 "bits67" () 6 2)
|
(dnf f-bits67 "bits67" () 6 2)
|
(dnf f-bit4 "bit4" () 4 1)
|
(dnf f-bit4 "bit4" () 4 1)
|
(dnf f-bit14 "bit14" () 14 1)
|
(dnf f-bit14 "bit14" () 14 1)
|
|
|
(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
|
(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
|
(attrs)
|
(attrs)
|
(start 15) (length 1)
|
(start 15) (length 1)
|
(encode (value pc) (sub WI value (const WI 1)))
|
(encode (value pc) (sub WI value (const WI 1)))
|
(decode (value pc) (add WI value (const WI 1)))
|
(decode (value pc) (add WI value (const WI 1)))
|
)
|
)
|
|
|
; Enums.
|
; Enums.
|
|
|
; insn-op1: bits 0-3
|
; insn-op1: bits 0-3
|
; FIXME: should use die macro or some such
|
; FIXME: should use die macro or some such
|
(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
|
(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
|
("0" "1" "2" "3" "4" "5" "6" "7"
|
("0" "1" "2" "3" "4" "5" "6" "7"
|
"8" "9" "10" "11" "12" "13" "14" "15")
|
"8" "9" "10" "11" "12" "13" "14" "15")
|
)
|
)
|
|
|
; insn-op2: bits 8-11
|
; insn-op2: bits 8-11
|
; FIXME: should use die macro or some such
|
; FIXME: should use die macro or some such
|
(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
|
(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
|
("0" "1" "2" "3" "4" "5" "6" "7"
|
("0" "1" "2" "3" "4" "5" "6" "7"
|
"8" "9" "10" "11" "12" "13" "14" "15")
|
"8" "9" "10" "11" "12" "13" "14" "15")
|
)
|
)
|
|
|
; Hardware pieces.
|
; Hardware pieces.
|
; These entries list the elements of the raw hardware.
|
; These entries list the elements of the raw hardware.
|
; They're also used to provide tables and other elements of the assembly
|
; They're also used to provide tables and other elements of the assembly
|
; language.
|
; language.
|
|
|
(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
|
(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
|
|
|
(dnh h-hi16 "high 16 bits" ()
|
(dnh h-hi16 "high 16 bits" ()
|
(immediate (UINT 16))
|
(immediate (UINT 16))
|
() () ()
|
() () ()
|
)
|
)
|
|
|
; These two aren't technically needed.
|
; These two aren't technically needed.
|
; They're here for illustration sake mostly.
|
; They're here for illustration sake mostly.
|
; Plus they cause the value to be stored in the extraction buffers to only
|
; Plus they cause the value to be stored in the extraction buffers to only
|
; be 16 bits wide (vs 32 or 64). Whoopie ding. But it's fun.
|
; be 16 bits wide (vs 32 or 64). Whoopie ding. But it's fun.
|
(dnh h-slo16 "signed low 16 bits" ()
|
(dnh h-slo16 "signed low 16 bits" ()
|
(immediate (INT 16))
|
(immediate (INT 16))
|
() () ()
|
() () ()
|
)
|
)
|
(dnh h-ulo16 "unsigned low 16 bits" ()
|
(dnh h-ulo16 "unsigned low 16 bits" ()
|
(immediate (UINT 16))
|
(immediate (UINT 16))
|
() () ()
|
() () ()
|
)
|
)
|
|
|
(define-keyword
|
(define-keyword
|
(name gr-names)
|
(name gr-names)
|
(print-name h-gr)
|
(print-name h-gr)
|
(prefix "")
|
(prefix "")
|
(values (fp 13) (lr 14) (sp 15)
|
(values (fp 13) (lr 14) (sp 15)
|
(r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
|
(r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
|
(r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
|
(r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
|
)
|
)
|
|
|
(define-hardware
|
(define-hardware
|
(name h-gr)
|
(name h-gr)
|
(comment "general registers")
|
(comment "general registers")
|
(attrs PROFILE CACHE-ADDR)
|
(attrs PROFILE CACHE-ADDR)
|
(type register WI (16))
|
(type register WI (16))
|
(indices extern-keyword gr-names)
|
(indices extern-keyword gr-names)
|
)
|
)
|
|
|
(define-keyword
|
(define-keyword
|
(name cr-names)
|
(name cr-names)
|
(print-name h-cr)
|
(print-name h-cr)
|
(prefix "")
|
(prefix "")
|
(values (psw 0) (cbr 1) (spi 2) (spu 3)
|
(values (psw 0) (cbr 1) (spi 2) (spu 3)
|
(bpc 6) (bbpsw 8) (bbpc 14) (evb 5)
|
(bpc 6) (bbpsw 8) (bbpc 14) (evb 5)
|
(cr0 0) (cr1 1) (cr2 2) (cr3 3)
|
(cr0 0) (cr1 1) (cr2 2) (cr3 3)
|
(cr4 4) (cr5 5) (cr6 6) (cr7 7)
|
(cr4 4) (cr5 5) (cr6 6) (cr7 7)
|
(cr8 8) (cr9 9) (cr10 10) (cr11 11)
|
(cr8 8) (cr9 9) (cr10 10) (cr11 11)
|
(cr12 12) (cr13 13) (cr14 14) (cr15 15))
|
(cr12 12) (cr13 13) (cr14 14) (cr15 15))
|
)
|
)
|
|
|
(define-hardware
|
(define-hardware
|
(name h-cr)
|
(name h-cr)
|
(comment "control registers")
|
(comment "control registers")
|
(type register UWI (16))
|
(type register UWI (16))
|
(indices extern-keyword cr-names)
|
(indices extern-keyword cr-names)
|
(get (index) (c-call UWI "@cpu@_h_cr_get_handler" index))
|
(get (index) (c-call UWI "@cpu@_h_cr_get_handler" index))
|
(set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval))
|
(set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval))
|
)
|
)
|
|
|
; The actual accumulator is only 56 bits.
|
; The actual accumulator is only 56 bits.
|
; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0).
|
; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0).
|
; To simplify the accumulator instructions, no attempt is made to keep the
|
; To simplify the accumulator instructions, no attempt is made to keep the
|
; top 8 bits properly sign extended (currently there's no point since they
|
; top 8 bits properly sign extended (currently there's no point since they
|
; all ignore them). When the value is read it is properly sign extended
|
; all ignore them). When the value is read it is properly sign extended
|
; [in the `get' handler].
|
; [in the `get' handler].
|
(define-hardware
|
(define-hardware
|
(name h-accum)
|
(name h-accum)
|
(comment "accumulator")
|
(comment "accumulator")
|
(type register DI)
|
(type register DI)
|
(get () (c-call DI "@cpu@_h_accum_get_handler"))
|
(get () (c-call DI "@cpu@_h_accum_get_handler"))
|
(set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval))
|
(set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval))
|
)
|
)
|
|
|
; FIXME: Revisit after sanitization can be removed. Remove h-accum.
|
; FIXME: Revisit after sanitization can be removed. Remove h-accum.
|
(define-hardware
|
(define-hardware
|
(name h-accums)
|
(name h-accums)
|
(comment "accumulators")
|
(comment "accumulators")
|
(attrs (MACH m32rx,m32r2))
|
(attrs (MACH m32rx,m32r2))
|
(type register DI (2))
|
(type register DI (2))
|
(indices keyword "" ((a0 0) (a1 1)))
|
(indices keyword "" ((a0 0) (a1 1)))
|
; get/set so a0 accesses are redirected to h-accum.
|
; get/set so a0 accesses are redirected to h-accum.
|
; They're also so reads can properly sign extend the value.
|
; They're also so reads can properly sign extend the value.
|
; FIXME: Needn't be a function call.
|
; FIXME: Needn't be a function call.
|
(get (index) (c-call DI "@cpu@_h_accums_get_handler" index))
|
(get (index) (c-call DI "@cpu@_h_accums_get_handler" index))
|
(set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval))
|
(set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval))
|
)
|
)
|
|
|
; For condbit operand. FIXME: Need to allow spec of get/set of operands.
|
; For condbit operand. FIXME: Need to allow spec of get/set of operands.
|
; Having this separate from h-psw keeps the parts that use it simpler
|
; Having this separate from h-psw keeps the parts that use it simpler
|
; [since they greatly outnumber those that use h-psw].
|
; [since they greatly outnumber those that use h-psw].
|
(dsh h-cond "condition bit" () (register BI))
|
(dsh h-cond "condition bit" () (register BI))
|
|
|
; The actual values of psw,bpsw,bbpsw are recorded here to allow access
|
; The actual values of psw,bpsw,bbpsw are recorded here to allow access
|
; to them as a unit.
|
; to them as a unit.
|
(define-hardware
|
(define-hardware
|
(name h-psw)
|
(name h-psw)
|
(comment "psw part of psw")
|
(comment "psw part of psw")
|
(type register UQI)
|
(type register UQI)
|
; get/set to handle cond bit.
|
; get/set to handle cond bit.
|
; FIXME: missing: use's and clobber's
|
; FIXME: missing: use's and clobber's
|
; FIXME: remove c-call?
|
; FIXME: remove c-call?
|
(get () (c-call UQI "@cpu@_h_psw_get_handler"))
|
(get () (c-call UQI "@cpu@_h_psw_get_handler"))
|
(set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval))
|
(set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval))
|
)
|
)
|
(dsh h-bpsw "backup psw" () (register UQI))
|
(dsh h-bpsw "backup psw" () (register UQI))
|
(dsh h-bbpsw "backup bpsw" () (register UQI))
|
(dsh h-bbpsw "backup bpsw" () (register UQI))
|
|
|
; FIXME: Later make add get/set specs and support SMP.
|
; FIXME: Later make add get/set specs and support SMP.
|
(dsh h-lock "lock" () (register BI))
|
(dsh h-lock "lock" () (register BI))
|
|
|
; Instruction Operands.
|
; Instruction Operands.
|
; These entries provide a layer between the assembler and the raw hardware
|
; These entries provide a layer between the assembler and the raw hardware
|
; description, and are used to refer to hardware elements in the semantic
|
; description, and are used to refer to hardware elements in the semantic
|
; code. Usually there's a bit of over-specification, but in more complicated
|
; code. Usually there's a bit of over-specification, but in more complicated
|
; instruction sets there isn't.
|
; instruction sets there isn't.
|
|
|
; M32R specific operand attributes:
|
; M32R specific operand attributes:
|
|
|
(define-attr
|
(define-attr
|
(for operand)
|
(for operand)
|
(type boolean)
|
(type boolean)
|
(name HASH-PREFIX)
|
(name HASH-PREFIX)
|
(comment "immediates have an optional '#' prefix")
|
(comment "immediates have an optional '#' prefix")
|
)
|
)
|
|
|
; ??? Convention says this should be o-sr, but then the insn definitions
|
; ??? Convention says this should be o-sr, but then the insn definitions
|
; should refer to o-sr which is clumsy. The "o-" could be implicit, but
|
; should refer to o-sr which is clumsy. The "o-" could be implicit, but
|
; then it should be implicit for all the symbols here, but then there would
|
; then it should be implicit for all the symbols here, but then there would
|
; be confusion between (f-)simm8 and (h-)simm8.
|
; be confusion between (f-)simm8 and (h-)simm8.
|
; So for now the rule is exactly as it appears here.
|
; So for now the rule is exactly as it appears here.
|
|
|
(dnop sr "source register" () h-gr f-r2)
|
(dnop sr "source register" () h-gr f-r2)
|
(dnop dr "destination register" () h-gr f-r1)
|
(dnop dr "destination register" () h-gr f-r1)
|
;; The assembler relies upon the fact that dr and src1 are the same field.
|
;; The assembler relies upon the fact that dr and src1 are the same field.
|
;; FIXME: Revisit.
|
;; FIXME: Revisit.
|
(dnop src1 "source register 1" () h-gr f-r1)
|
(dnop src1 "source register 1" () h-gr f-r1)
|
(dnop src2 "source register 2" () h-gr f-r2)
|
(dnop src2 "source register 2" () h-gr f-r2)
|
(dnop scr "source control register" () h-cr f-r2)
|
(dnop scr "source control register" () h-cr f-r2)
|
(dnop dcr "destination control register" () h-cr f-r1)
|
(dnop dcr "destination control register" () h-cr f-r1)
|
|
|
(dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8)
|
(dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8)
|
(dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16)
|
(dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16)
|
(dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-uint f-uimm3)
|
(dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-uint f-uimm3)
|
(dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4)
|
(dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4)
|
(dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5)
|
(dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5)
|
(dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8)
|
(dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8)
|
(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16)
|
(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16)
|
|
|
(dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1)
|
(dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1)
|
(dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd)
|
(dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd)
|
(dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs)
|
(dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs)
|
(dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc)
|
(dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc)
|
|
|
; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
|
; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
|
; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use HASH-PREFIX.
|
; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use HASH-PREFIX.
|
; Instead we create a fake operand `hash'. The m32r is an illustration port,
|
; Instead we create a fake operand `hash'. The m32r is an illustration port,
|
; so we often try out various ways of doing things.
|
; so we often try out various ways of doing things.
|
|
|
(define-operand (name hash) (comment "# prefix") (attrs)
|
(define-operand (name hash) (comment "# prefix") (attrs)
|
(type h-sint) ; doesn't really matter
|
(type h-sint) ; doesn't really matter
|
(index f-nil)
|
(index f-nil)
|
(handlers (parse "hash") (print "hash"))
|
(handlers (parse "hash") (print "hash"))
|
)
|
)
|
|
|
; For high(foo),shigh(foo).
|
; For high(foo),shigh(foo).
|
(define-operand
|
(define-operand
|
(name hi16)
|
(name hi16)
|
(comment "high 16 bit immediate, sign optional")
|
(comment "high 16 bit immediate, sign optional")
|
(attrs)
|
(attrs)
|
(type h-hi16)
|
(type h-hi16)
|
(index f-hi16)
|
(index f-hi16)
|
(handlers (parse "hi16"))
|
(handlers (parse "hi16"))
|
)
|
)
|
|
|
; For low(foo),sda(foo).
|
; For low(foo),sda(foo).
|
(define-operand
|
(define-operand
|
(name slo16)
|
(name slo16)
|
(comment "16 bit signed immediate, for low()")
|
(comment "16 bit signed immediate, for low()")
|
(attrs)
|
(attrs)
|
(type h-slo16)
|
(type h-slo16)
|
(index f-simm16)
|
(index f-simm16)
|
(handlers (parse "slo16"))
|
(handlers (parse "slo16"))
|
)
|
)
|
|
|
; For low(foo).
|
; For low(foo).
|
(define-operand
|
(define-operand
|
(name ulo16)
|
(name ulo16)
|
(comment "16 bit unsigned immediate, for low()")
|
(comment "16 bit unsigned immediate, for low()")
|
(attrs)
|
(attrs)
|
(type h-ulo16)
|
(type h-ulo16)
|
(index f-uimm16)
|
(index f-uimm16)
|
(handlers (parse "ulo16"))
|
(handlers (parse "ulo16"))
|
)
|
)
|
|
|
(dnop uimm24 "24 bit address" (HASH-PREFIX) h-addr f-uimm24)
|
(dnop uimm24 "24 bit address" (HASH-PREFIX) h-addr f-uimm24)
|
|
|
(define-operand
|
(define-operand
|
(name disp8)
|
(name disp8)
|
(comment "8 bit displacement")
|
(comment "8 bit displacement")
|
(attrs RELAX)
|
(attrs RELAX)
|
(type h-iaddr)
|
(type h-iaddr)
|
(index f-disp8)
|
(index f-disp8)
|
; ??? Early experiments had insert/extract fields here.
|
; ??? Early experiments had insert/extract fields here.
|
; Moving these to f-disp8 made things cleaner, but may wish to re-introduce
|
; Moving these to f-disp8 made things cleaner, but may wish to re-introduce
|
; fields here to handle more complicated cases.
|
; fields here to handle more complicated cases.
|
)
|
)
|
|
|
(dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
|
(dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
|
(dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)
|
(dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)
|
|
|
; These hardware elements are refered to frequently.
|
; These hardware elements are refered to frequently.
|
|
|
(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
|
(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
|
(dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)
|
(dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)
|
|
|
; Instruction definitions.
|
; Instruction definitions.
|
;
|
;
|
; Notes while wip:
|
; Notes while wip:
|
; - dni is a cover macro to the real "this is an instruction" keyword.
|
; - dni is a cover macro to the real "this is an instruction" keyword.
|
; The syntax of the real one is yet to be determined.
|
; The syntax of the real one is yet to be determined.
|
; At the lowest level (i.e. the "real" one) it will probably take a variable
|
; At the lowest level (i.e. the "real" one) it will probably take a variable
|
; list of arguments where each argument [perhaps after the standard three of
|
; list of arguments where each argument [perhaps after the standard three of
|
; name, comment, attrs] is "(keyword arg-to-keyword)". This syntax is simple
|
; name, comment, attrs] is "(keyword arg-to-keyword)". This syntax is simple
|
; and yet completely upward extensible. And given the macro facility, one
|
; and yet completely upward extensible. And given the macro facility, one
|
; needn't code at that low a level so even though it'll be more verbose than
|
; needn't code at that low a level so even though it'll be more verbose than
|
; necessary it won't matter. This same reasoning can be applied to most
|
; necessary it won't matter. This same reasoning can be applied to most
|
; types of entries in this file.
|
; types of entries in this file.
|
|
|
; M32R specific instruction attributes:
|
; M32R specific instruction attributes:
|
|
|
; FILL-SLOT: Need next insn to begin on 32 bit boundary.
|
; FILL-SLOT: Need next insn to begin on 32 bit boundary.
|
; (A "slot" as used here is a 32 bit quantity that can either be filled with
|
; (A "slot" as used here is a 32 bit quantity that can either be filled with
|
; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right
|
; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right
|
; bin" where the left bin is the one with a lower address).
|
; bin" where the left bin is the one with a lower address).
|
|
|
(define-attr
|
(define-attr
|
(for insn)
|
(for insn)
|
(type boolean)
|
(type boolean)
|
(name FILL-SLOT)
|
(name FILL-SLOT)
|
(comment "fill right bin with `nop' if insn is in left bin")
|
(comment "fill right bin with `nop' if insn is in left bin")
|
)
|
)
|
|
|
(define-attr
|
(define-attr
|
(for insn)
|
(for insn)
|
(type boolean)
|
(type boolean)
|
(name SPECIAL)
|
(name SPECIAL)
|
(comment "non-public m32rx insn")
|
(comment "non-public m32rx insn")
|
)
|
)
|
|
|
(define-attr
|
(define-attr
|
(for insn)
|
(for insn)
|
(type boolean)
|
(type boolean)
|
(name SPECIAL_M32R)
|
(name SPECIAL_M32R)
|
(comment "non-public m32r insn")
|
(comment "non-public m32r insn")
|
)
|
)
|
|
|
(define-attr
|
(define-attr
|
(for insn)
|
(for insn)
|
(type boolean)
|
(type boolean)
|
(name SPECIAL_FLOAT)
|
(name SPECIAL_FLOAT)
|
(comment "floating point insn")
|
(comment "floating point insn")
|
)
|
)
|
|
|
; IDOC attribute for instruction documentation.
|
; IDOC attribute for instruction documentation.
|
|
|
(define-attr
|
(define-attr
|
(for insn)
|
(for insn)
|
(type enum)
|
(type enum)
|
(name IDOC)
|
(name IDOC)
|
(comment "insn kind for documentation")
|
(comment "insn kind for documentation")
|
(attrs META)
|
(attrs META)
|
(values
|
(values
|
(MEM - () "Memory")
|
(MEM - () "Memory")
|
(ALU - () "ALU")
|
(ALU - () "ALU")
|
(BR - () "Branch")
|
(BR - () "Branch")
|
(ACCUM - () "Accumulator")
|
(ACCUM - () "Accumulator")
|
(MAC - () "Multiply/Accumulate")
|
(MAC - () "Multiply/Accumulate")
|
(MISC - () "Miscellaneous")
|
(MISC - () "Miscellaneous")
|
)
|
)
|
)
|
)
|
|
|
(define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm)
|
(define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm)
|
(begin
|
(begin
|
(dni mnemonic
|
(dni mnemonic
|
(.str mnemonic " reg/reg")
|
(.str mnemonic " reg/reg")
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
(.str mnemonic " $dr,$sr")
|
(.str mnemonic " $dr,$sr")
|
(+ OP1_0 op2-op dr sr)
|
(+ OP1_0 op2-op dr sr)
|
(set dr (sem-op dr sr))
|
(set dr (sem-op dr sr))
|
()
|
()
|
)
|
)
|
(dni (.sym mnemonic "3")
|
(dni (.sym mnemonic "3")
|
(.str mnemonic " reg/" imm)
|
(.str mnemonic " reg/" imm)
|
((IDOC ALU))
|
((IDOC ALU))
|
(.str mnemonic "3 $dr,$sr," imm-prefix "$" imm)
|
(.str mnemonic "3 $dr,$sr," imm-prefix "$" imm)
|
(+ OP1_8 op2-op dr sr imm)
|
(+ OP1_8 op2-op dr sr imm)
|
(set dr (sem-op sr imm))
|
(set dr (sem-op sr imm))
|
()
|
()
|
)
|
)
|
)
|
)
|
)
|
)
|
(bin-op add OP2_10 add "$hash" slo16)
|
(bin-op add OP2_10 add "$hash" slo16)
|
; sub isn't present because sub3 doesn't exist.
|
; sub isn't present because sub3 doesn't exist.
|
(bin-op and OP2_12 and "" uimm16)
|
(bin-op and OP2_12 and "" uimm16)
|
(bin-op or OP2_14 or "$hash" ulo16)
|
(bin-op or OP2_14 or "$hash" ulo16)
|
(bin-op xor OP2_13 xor "" uimm16)
|
(bin-op xor OP2_13 xor "" uimm16)
|
|
|
(dni addi "addi"
|
(dni addi "addi"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
;#.(string-append "addi " "$dr,$simm8") ; #. experiment
|
;#.(string-append "addi " "$dr,$simm8") ; #. experiment
|
"addi $dr,$simm8"
|
"addi $dr,$simm8"
|
(+ OP1_4 dr simm8)
|
(+ OP1_4 dr simm8)
|
(set dr (add dr simm8))
|
(set dr (add dr simm8))
|
((m32r/d (unit u-exec))
|
((m32r/d (unit u-exec))
|
(m32rx (unit u-exec))
|
(m32rx (unit u-exec))
|
(m32r2 (unit u-exec)))
|
(m32r2 (unit u-exec)))
|
)
|
)
|
|
|
(dni addv "addv"
|
(dni addv "addv"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"addv $dr,$sr"
|
"addv $dr,$sr"
|
(+ OP1_0 OP2_8 dr sr)
|
(+ OP1_0 OP2_8 dr sr)
|
(parallel ()
|
(parallel ()
|
(set dr (add dr sr))
|
(set dr (add dr sr))
|
(set condbit (add-oflag dr sr (const 0))))
|
(set condbit (add-oflag dr sr (const 0))))
|
()
|
()
|
)
|
)
|
|
|
(dni addv3 "addv3"
|
(dni addv3 "addv3"
|
((IDOC ALU))
|
((IDOC ALU))
|
"addv3 $dr,$sr,$simm16"
|
"addv3 $dr,$sr,$simm16"
|
(+ OP1_8 OP2_8 dr sr simm16)
|
(+ OP1_8 OP2_8 dr sr simm16)
|
(parallel ()
|
(parallel ()
|
(set dr (add sr simm16))
|
(set dr (add sr simm16))
|
(set condbit (add-oflag sr simm16 (const 0))))
|
(set condbit (add-oflag sr simm16 (const 0))))
|
()
|
()
|
)
|
)
|
|
|
(dni addx "addx"
|
(dni addx "addx"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"addx $dr,$sr"
|
"addx $dr,$sr"
|
(+ OP1_0 OP2_9 dr sr)
|
(+ OP1_0 OP2_9 dr sr)
|
(parallel ()
|
(parallel ()
|
(set dr (addc dr sr condbit))
|
(set dr (addc dr sr condbit))
|
(set condbit (add-cflag dr sr condbit)))
|
(set condbit (add-cflag dr sr condbit)))
|
()
|
()
|
)
|
)
|
|
|
(dni bc8 "bc with 8 bit displacement"
|
(dni bc8 "bc with 8 bit displacement"
|
(COND-CTI (PIPE O) (IDOC BR))
|
(COND-CTI (PIPE O) (IDOC BR))
|
"bc.s $disp8"
|
"bc.s $disp8"
|
(+ OP1_7 (f-r1 12) disp8)
|
(+ OP1_7 (f-r1 12) disp8)
|
(if condbit (set pc disp8))
|
(if condbit (set pc disp8))
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bc8r "relaxable bc8"
|
(dnmi bc8r "relaxable bc8"
|
(COND-CTI RELAXABLE (PIPE O) (IDOC BR))
|
(COND-CTI RELAXABLE (PIPE O) (IDOC BR))
|
"bc $disp8"
|
"bc $disp8"
|
(emit bc8 disp8)
|
(emit bc8 disp8)
|
)
|
)
|
|
|
(dni bc24 "bc with 24 bit displacement"
|
(dni bc24 "bc with 24 bit displacement"
|
(COND-CTI (IDOC BR))
|
(COND-CTI (IDOC BR))
|
"bc.l $disp24"
|
"bc.l $disp24"
|
(+ OP1_15 (f-r1 12) disp24)
|
(+ OP1_15 (f-r1 12) disp24)
|
(if condbit (set pc disp24))
|
(if condbit (set pc disp24))
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bc24r "relaxable bc24"
|
(dnmi bc24r "relaxable bc24"
|
(COND-CTI RELAXED (IDOC BR))
|
(COND-CTI RELAXED (IDOC BR))
|
"bc $disp24"
|
"bc $disp24"
|
(emit bc24 disp24)
|
(emit bc24 disp24)
|
)
|
)
|
|
|
(dni beq "beq"
|
(dni beq "beq"
|
(COND-CTI (IDOC BR))
|
(COND-CTI (IDOC BR))
|
"beq $src1,$src2,$disp16"
|
"beq $src1,$src2,$disp16"
|
(+ OP1_11 OP2_0 src1 src2 disp16)
|
(+ OP1_11 OP2_0 src1 src2 disp16)
|
(if (eq src1 src2) (set pc disp16))
|
(if (eq src1 src2) (set pc disp16))
|
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
|
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
|
(m32rx (unit u-cti) (unit u-cmp (cycles 0)))
|
(m32rx (unit u-cti) (unit u-cmp (cycles 0)))
|
(m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
|
(m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
|
)
|
)
|
|
|
(define-pmacro (cbranch sym comment op2-op comp-op)
|
(define-pmacro (cbranch sym comment op2-op comp-op)
|
(dni sym comment (COND-CTI (IDOC BR))
|
(dni sym comment (COND-CTI (IDOC BR))
|
(.str sym " $src2,$disp16")
|
(.str sym " $src2,$disp16")
|
(+ OP1_11 op2-op (f-r1 0) src2 disp16)
|
(+ OP1_11 op2-op (f-r1 0) src2 disp16)
|
(if (comp-op src2 (const WI 0)) (set pc disp16))
|
(if (comp-op src2 (const WI 0)) (set pc disp16))
|
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
|
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
|
(m32rx (unit u-cti) (unit u-cmp (cycles 0)))
|
(m32rx (unit u-cti) (unit u-cmp (cycles 0)))
|
(m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
|
(m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
|
)
|
)
|
)
|
)
|
(cbranch beqz "beqz" OP2_8 eq)
|
(cbranch beqz "beqz" OP2_8 eq)
|
(cbranch bgez "bgez" OP2_11 ge)
|
(cbranch bgez "bgez" OP2_11 ge)
|
(cbranch bgtz "bgtz" OP2_13 gt)
|
(cbranch bgtz "bgtz" OP2_13 gt)
|
(cbranch blez "blez" OP2_12 le)
|
(cbranch blez "blez" OP2_12 le)
|
(cbranch bltz "bltz" OP2_10 lt)
|
(cbranch bltz "bltz" OP2_10 lt)
|
(cbranch bnez "bnez" OP2_9 ne)
|
(cbranch bnez "bnez" OP2_9 ne)
|
|
|
(dni bl8 "bl with 8 bit displacement"
|
(dni bl8 "bl with 8 bit displacement"
|
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
|
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
|
"bl.s $disp8"
|
"bl.s $disp8"
|
(+ OP1_7 (f-r1 14) disp8)
|
(+ OP1_7 (f-r1 14) disp8)
|
(sequence ()
|
(sequence ()
|
(set (reg h-gr 14)
|
(set (reg h-gr 14)
|
(add (and pc (const -4)) (const 4)))
|
(add (and pc (const -4)) (const 4)))
|
(set pc disp8))
|
(set pc disp8))
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bl8r "relaxable bl8"
|
(dnmi bl8r "relaxable bl8"
|
(UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
|
(UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
|
"bl $disp8"
|
"bl $disp8"
|
(emit bl8 disp8)
|
(emit bl8 disp8)
|
)
|
)
|
|
|
(dni bl24 "bl with 24 bit displacement"
|
(dni bl24 "bl with 24 bit displacement"
|
(UNCOND-CTI (IDOC BR))
|
(UNCOND-CTI (IDOC BR))
|
"bl.l $disp24"
|
"bl.l $disp24"
|
(+ OP1_15 (f-r1 14) disp24)
|
(+ OP1_15 (f-r1 14) disp24)
|
(sequence ()
|
(sequence ()
|
(set (reg h-gr 14) (add pc (const 4)))
|
(set (reg h-gr 14) (add pc (const 4)))
|
(set pc disp24))
|
(set pc disp24))
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bl24r "relaxable bl24"
|
(dnmi bl24r "relaxable bl24"
|
(UNCOND-CTI RELAXED (IDOC BR))
|
(UNCOND-CTI RELAXED (IDOC BR))
|
"bl $disp24"
|
"bl $disp24"
|
(emit bl24 disp24)
|
(emit bl24 disp24)
|
)
|
)
|
|
|
(dni bcl8 "bcl with 8 bit displacement"
|
(dni bcl8 "bcl with 8 bit displacement"
|
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
|
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
|
"bcl.s $disp8"
|
"bcl.s $disp8"
|
(+ OP1_7 (f-r1 8) disp8)
|
(+ OP1_7 (f-r1 8) disp8)
|
(if condbit
|
(if condbit
|
(sequence ()
|
(sequence ()
|
(set (reg h-gr 14)
|
(set (reg h-gr 14)
|
(add (and pc (const -4))
|
(add (and pc (const -4))
|
(const 4)))
|
(const 4)))
|
(set pc disp8)))
|
(set pc disp8)))
|
((m32rx (unit u-cti))
|
((m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bcl8r "relaxable bcl8"
|
(dnmi bcl8r "relaxable bcl8"
|
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
|
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
|
"bcl $disp8"
|
"bcl $disp8"
|
(emit bcl8 disp8)
|
(emit bcl8 disp8)
|
)
|
)
|
|
|
(dni bcl24 "bcl with 24 bit displacement"
|
(dni bcl24 "bcl with 24 bit displacement"
|
(COND-CTI (MACH m32rx,m32r2) (IDOC BR))
|
(COND-CTI (MACH m32rx,m32r2) (IDOC BR))
|
"bcl.l $disp24"
|
"bcl.l $disp24"
|
(+ OP1_15 (f-r1 8) disp24)
|
(+ OP1_15 (f-r1 8) disp24)
|
(if condbit
|
(if condbit
|
(sequence ()
|
(sequence ()
|
(set (reg h-gr 14) (add pc (const 4)))
|
(set (reg h-gr 14) (add pc (const 4)))
|
(set pc disp24)))
|
(set pc disp24)))
|
((m32rx (unit u-cti))
|
((m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bcl24r "relaxable bcl24"
|
(dnmi bcl24r "relaxable bcl24"
|
(COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
|
(COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
|
"bcl $disp24"
|
"bcl $disp24"
|
(emit bcl24 disp24)
|
(emit bcl24 disp24)
|
)
|
)
|
|
|
(dni bnc8 "bnc with 8 bit displacement"
|
(dni bnc8 "bnc with 8 bit displacement"
|
(COND-CTI (PIPE O) (IDOC BR))
|
(COND-CTI (PIPE O) (IDOC BR))
|
"bnc.s $disp8"
|
"bnc.s $disp8"
|
(+ OP1_7 (f-r1 13) disp8)
|
(+ OP1_7 (f-r1 13) disp8)
|
(if (not condbit) (set pc disp8))
|
(if (not condbit) (set pc disp8))
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bnc8r "relaxable bnc8"
|
(dnmi bnc8r "relaxable bnc8"
|
(COND-CTI RELAXABLE (PIPE O) (IDOC BR))
|
(COND-CTI RELAXABLE (PIPE O) (IDOC BR))
|
"bnc $disp8"
|
"bnc $disp8"
|
(emit bnc8 disp8)
|
(emit bnc8 disp8)
|
)
|
)
|
|
|
(dni bnc24 "bnc with 24 bit displacement"
|
(dni bnc24 "bnc with 24 bit displacement"
|
(COND-CTI (IDOC BR))
|
(COND-CTI (IDOC BR))
|
"bnc.l $disp24"
|
"bnc.l $disp24"
|
(+ OP1_15 (f-r1 13) disp24)
|
(+ OP1_15 (f-r1 13) disp24)
|
(if (not condbit) (set pc disp24))
|
(if (not condbit) (set pc disp24))
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bnc24r "relaxable bnc24"
|
(dnmi bnc24r "relaxable bnc24"
|
(COND-CTI RELAXED (IDOC BR))
|
(COND-CTI RELAXED (IDOC BR))
|
"bnc $disp24"
|
"bnc $disp24"
|
(emit bnc24 disp24)
|
(emit bnc24 disp24)
|
)
|
)
|
|
|
(dni bne "bne"
|
(dni bne "bne"
|
(COND-CTI (IDOC BR))
|
(COND-CTI (IDOC BR))
|
"bne $src1,$src2,$disp16"
|
"bne $src1,$src2,$disp16"
|
(+ OP1_11 OP2_1 src1 src2 disp16)
|
(+ OP1_11 OP2_1 src1 src2 disp16)
|
(if (ne src1 src2) (set pc disp16))
|
(if (ne src1 src2) (set pc disp16))
|
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
|
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
|
(m32rx (unit u-cti) (unit u-cmp (cycles 0)))
|
(m32rx (unit u-cti) (unit u-cmp (cycles 0)))
|
(m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
|
(m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
|
)
|
)
|
|
|
(dni bra8 "bra with 8 bit displacement"
|
(dni bra8 "bra with 8 bit displacement"
|
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
|
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
|
"bra.s $disp8"
|
"bra.s $disp8"
|
(+ OP1_7 (f-r1 15) disp8)
|
(+ OP1_7 (f-r1 15) disp8)
|
(set pc disp8)
|
(set pc disp8)
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bra8r "relaxable bra8"
|
(dnmi bra8r "relaxable bra8"
|
(UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
|
(UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
|
"bra $disp8"
|
"bra $disp8"
|
(emit bra8 disp8)
|
(emit bra8 disp8)
|
)
|
)
|
|
|
(dni bra24 "bra with 24 displacement"
|
(dni bra24 "bra with 24 displacement"
|
(UNCOND-CTI (IDOC BR))
|
(UNCOND-CTI (IDOC BR))
|
"bra.l $disp24"
|
"bra.l $disp24"
|
(+ OP1_15 (f-r1 15) disp24)
|
(+ OP1_15 (f-r1 15) disp24)
|
(set pc disp24)
|
(set pc disp24)
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bra24r "relaxable bra24"
|
(dnmi bra24r "relaxable bra24"
|
(UNCOND-CTI RELAXED (IDOC BR))
|
(UNCOND-CTI RELAXED (IDOC BR))
|
"bra $disp24"
|
"bra $disp24"
|
(emit bra24 disp24)
|
(emit bra24 disp24)
|
)
|
)
|
|
|
(dni bncl8 "bncl with 8 bit displacement"
|
(dni bncl8 "bncl with 8 bit displacement"
|
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
|
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
|
"bncl.s $disp8"
|
"bncl.s $disp8"
|
(+ OP1_7 (f-r1 9) disp8)
|
(+ OP1_7 (f-r1 9) disp8)
|
(if (not condbit)
|
(if (not condbit)
|
(sequence ()
|
(sequence ()
|
(set (reg h-gr 14)
|
(set (reg h-gr 14)
|
(add (and pc (const -4))
|
(add (and pc (const -4))
|
(const 4)))
|
(const 4)))
|
(set pc disp8)))
|
(set pc disp8)))
|
((m32rx (unit u-cti))
|
((m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bncl8r "relaxable bncl8"
|
(dnmi bncl8r "relaxable bncl8"
|
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
|
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
|
"bncl $disp8"
|
"bncl $disp8"
|
(emit bncl8 disp8)
|
(emit bncl8 disp8)
|
)
|
)
|
|
|
(dni bncl24 "bncl with 24 bit displacement"
|
(dni bncl24 "bncl with 24 bit displacement"
|
(COND-CTI (MACH m32rx,m32r2) (IDOC BR))
|
(COND-CTI (MACH m32rx,m32r2) (IDOC BR))
|
"bncl.l $disp24"
|
"bncl.l $disp24"
|
(+ OP1_15 (f-r1 9) disp24)
|
(+ OP1_15 (f-r1 9) disp24)
|
(if (not condbit)
|
(if (not condbit)
|
(sequence ()
|
(sequence ()
|
(set (reg h-gr 14) (add pc (const 4)))
|
(set (reg h-gr 14) (add pc (const 4)))
|
(set pc disp24)))
|
(set pc disp24)))
|
((m32rx (unit u-cti))
|
((m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dnmi bncl24r "relaxable bncl24"
|
(dnmi bncl24r "relaxable bncl24"
|
(COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
|
(COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
|
"bncl $disp24"
|
"bncl $disp24"
|
(emit bncl24 disp24)
|
(emit bncl24 disp24)
|
)
|
)
|
|
|
(dni cmp "cmp"
|
(dni cmp "cmp"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"cmp $src1,$src2"
|
"cmp $src1,$src2"
|
(+ OP1_0 OP2_4 src1 src2)
|
(+ OP1_0 OP2_4 src1 src2)
|
(set condbit (lt src1 src2))
|
(set condbit (lt src1 src2))
|
((m32r/d (unit u-cmp))
|
((m32r/d (unit u-cmp))
|
(m32rx (unit u-cmp))
|
(m32rx (unit u-cmp))
|
(m32r2 (unit u-cmp)))
|
(m32r2 (unit u-cmp)))
|
)
|
)
|
|
|
(dni cmpi "cmpi"
|
(dni cmpi "cmpi"
|
((IDOC ALU))
|
((IDOC ALU))
|
"cmpi $src2,$simm16"
|
"cmpi $src2,$simm16"
|
(+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
|
(+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
|
(set condbit (lt src2 simm16))
|
(set condbit (lt src2 simm16))
|
((m32r/d (unit u-cmp))
|
((m32r/d (unit u-cmp))
|
(m32rx (unit u-cmp))
|
(m32rx (unit u-cmp))
|
(m32r2 (unit u-cmp)))
|
(m32r2 (unit u-cmp)))
|
)
|
)
|
|
|
(dni cmpu "cmpu"
|
(dni cmpu "cmpu"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"cmpu $src1,$src2"
|
"cmpu $src1,$src2"
|
(+ OP1_0 OP2_5 src1 src2)
|
(+ OP1_0 OP2_5 src1 src2)
|
(set condbit (ltu src1 src2))
|
(set condbit (ltu src1 src2))
|
((m32r/d (unit u-cmp))
|
((m32r/d (unit u-cmp))
|
(m32rx (unit u-cmp))
|
(m32rx (unit u-cmp))
|
(m32r2 (unit u-cmp)))
|
(m32r2 (unit u-cmp)))
|
)
|
)
|
|
|
(dni cmpui "cmpui"
|
(dni cmpui "cmpui"
|
((IDOC ALU))
|
((IDOC ALU))
|
"cmpui $src2,$simm16"
|
"cmpui $src2,$simm16"
|
(+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
|
(+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
|
(set condbit (ltu src2 simm16))
|
(set condbit (ltu src2 simm16))
|
((m32r/d (unit u-cmp))
|
((m32r/d (unit u-cmp))
|
(m32rx (unit u-cmp))
|
(m32rx (unit u-cmp))
|
(m32r2 (unit u-cmp)))
|
(m32r2 (unit u-cmp)))
|
)
|
)
|
|
|
(dni cmpeq "cmpeq"
|
(dni cmpeq "cmpeq"
|
((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
|
((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
|
"cmpeq $src1,$src2"
|
"cmpeq $src1,$src2"
|
(+ OP1_0 OP2_6 src1 src2)
|
(+ OP1_0 OP2_6 src1 src2)
|
(set condbit (eq src1 src2))
|
(set condbit (eq src1 src2))
|
((m32rx (unit u-cmp))
|
((m32rx (unit u-cmp))
|
(m32r2 (unit u-cmp)))
|
(m32r2 (unit u-cmp)))
|
)
|
)
|
|
|
(dni cmpz "cmpz"
|
(dni cmpz "cmpz"
|
((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
|
((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
|
"cmpz $src2"
|
"cmpz $src2"
|
(+ OP1_0 OP2_7 (f-r1 0) src2)
|
(+ OP1_0 OP2_7 (f-r1 0) src2)
|
(set condbit (eq src2 (const 0)))
|
(set condbit (eq src2 (const 0)))
|
((m32rx (unit u-cmp))
|
((m32rx (unit u-cmp))
|
(m32r2 (unit u-cmp)))
|
(m32r2 (unit u-cmp)))
|
)
|
)
|
|
|
(dni div "div"
|
(dni div "div"
|
((IDOC ALU))
|
((IDOC ALU))
|
"div $dr,$sr"
|
"div $dr,$sr"
|
(+ OP1_9 OP2_0 dr sr (f-simm16 0))
|
(+ OP1_9 OP2_0 dr sr (f-simm16 0))
|
(if (ne sr (const 0)) (set dr (div dr sr)))
|
(if (ne sr (const 0)) (set dr (div dr sr)))
|
((m32r/d (unit u-exec (cycles 37)))
|
((m32r/d (unit u-exec (cycles 37)))
|
(m32rx (unit u-exec (cycles 37)))
|
(m32rx (unit u-exec (cycles 37)))
|
(m32r2 (unit u-exec (cycles 37))))
|
(m32r2 (unit u-exec (cycles 37))))
|
)
|
)
|
|
|
(dni divu "divu"
|
(dni divu "divu"
|
((IDOC ALU))
|
((IDOC ALU))
|
"divu $dr,$sr"
|
"divu $dr,$sr"
|
(+ OP1_9 OP2_1 dr sr (f-simm16 0))
|
(+ OP1_9 OP2_1 dr sr (f-simm16 0))
|
(if (ne sr (const 0)) (set dr (udiv dr sr)))
|
(if (ne sr (const 0)) (set dr (udiv dr sr)))
|
((m32r/d (unit u-exec (cycles 37)))
|
((m32r/d (unit u-exec (cycles 37)))
|
(m32rx (unit u-exec (cycles 37)))
|
(m32rx (unit u-exec (cycles 37)))
|
(m32r2 (unit u-exec (cycles 37))))
|
(m32r2 (unit u-exec (cycles 37))))
|
)
|
)
|
|
|
(dni rem "rem"
|
(dni rem "rem"
|
((IDOC ALU))
|
((IDOC ALU))
|
"rem $dr,$sr"
|
"rem $dr,$sr"
|
(+ OP1_9 OP2_2 dr sr (f-simm16 0))
|
(+ OP1_9 OP2_2 dr sr (f-simm16 0))
|
; FIXME: Check rounding direction.
|
; FIXME: Check rounding direction.
|
(if (ne sr (const 0)) (set dr (mod dr sr)))
|
(if (ne sr (const 0)) (set dr (mod dr sr)))
|
((m32r/d (unit u-exec (cycles 37)))
|
((m32r/d (unit u-exec (cycles 37)))
|
(m32rx (unit u-exec (cycles 37)))
|
(m32rx (unit u-exec (cycles 37)))
|
(m32r2 (unit u-exec (cycles 37))))
|
(m32r2 (unit u-exec (cycles 37))))
|
)
|
)
|
|
|
(dni remu "remu"
|
(dni remu "remu"
|
((IDOC ALU))
|
((IDOC ALU))
|
"remu $dr,$sr"
|
"remu $dr,$sr"
|
(+ OP1_9 OP2_3 dr sr (f-simm16 0))
|
(+ OP1_9 OP2_3 dr sr (f-simm16 0))
|
; FIXME: Check rounding direction.
|
; FIXME: Check rounding direction.
|
(if (ne sr (const 0)) (set dr (umod dr sr)))
|
(if (ne sr (const 0)) (set dr (umod dr sr)))
|
((m32r/d (unit u-exec (cycles 37)))
|
((m32r/d (unit u-exec (cycles 37)))
|
(m32rx (unit u-exec (cycles 37)))
|
(m32rx (unit u-exec (cycles 37)))
|
(m32r2 (unit u-exec (cycles 37))))
|
(m32r2 (unit u-exec (cycles 37))))
|
)
|
)
|
|
|
(dni remh "remh"
|
(dni remh "remh"
|
((MACH m32r2))
|
((MACH m32r2))
|
"remh $dr,$sr"
|
"remh $dr,$sr"
|
(+ OP1_9 OP2_2 dr sr (f-simm16 #x10))
|
(+ OP1_9 OP2_2 dr sr (f-simm16 #x10))
|
; FIXME: Check rounding direction.
|
; FIXME: Check rounding direction.
|
(if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))
|
(if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))
|
((m32r2 (unit u-exec (cycles 21))))
|
((m32r2 (unit u-exec (cycles 21))))
|
)
|
)
|
|
|
(dni remuh "remuh"
|
(dni remuh "remuh"
|
((MACH m32r2))
|
((MACH m32r2))
|
"remuh $dr,$sr"
|
"remuh $dr,$sr"
|
(+ OP1_9 OP2_3 dr sr (f-simm16 #x10))
|
(+ OP1_9 OP2_3 dr sr (f-simm16 #x10))
|
; FIXME: Check rounding direction.
|
; FIXME: Check rounding direction.
|
(if (ne sr (const 0)) (set dr (umod dr sr)))
|
(if (ne sr (const 0)) (set dr (umod dr sr)))
|
((m32r2 (unit u-exec (cycles 21))))
|
((m32r2 (unit u-exec (cycles 21))))
|
)
|
)
|
|
|
(dni remb "remb"
|
(dni remb "remb"
|
((MACH m32r2))
|
((MACH m32r2))
|
"remb $dr,$sr"
|
"remb $dr,$sr"
|
(+ OP1_9 OP2_2 dr sr (f-simm16 #x18))
|
(+ OP1_9 OP2_2 dr sr (f-simm16 #x18))
|
; FIXME: Check rounding direction.
|
; FIXME: Check rounding direction.
|
(if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))
|
(if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))
|
((m32r2 (unit u-exec (cycles 21))))
|
((m32r2 (unit u-exec (cycles 21))))
|
)
|
)
|
|
|
(dni remub "remub"
|
(dni remub "remub"
|
((MACH m32r2))
|
((MACH m32r2))
|
"remub $dr,$sr"
|
"remub $dr,$sr"
|
(+ OP1_9 OP2_3 dr sr (f-simm16 #x18))
|
(+ OP1_9 OP2_3 dr sr (f-simm16 #x18))
|
; FIXME: Check rounding direction.
|
; FIXME: Check rounding direction.
|
(if (ne sr (const 0)) (set dr (umod dr sr)))
|
(if (ne sr (const 0)) (set dr (umod dr sr)))
|
((m32r2 (unit u-exec (cycles 21))))
|
((m32r2 (unit u-exec (cycles 21))))
|
)
|
)
|
|
|
(dni divuh "divuh"
|
(dni divuh "divuh"
|
((MACH m32r2))
|
((MACH m32r2))
|
"divuh $dr,$sr"
|
"divuh $dr,$sr"
|
(+ OP1_9 OP2_1 dr sr (f-simm16 #x10))
|
(+ OP1_9 OP2_1 dr sr (f-simm16 #x10))
|
(if (ne sr (const 0)) (set dr (udiv dr sr)))
|
(if (ne sr (const 0)) (set dr (udiv dr sr)))
|
((m32r2 (unit u-exec (cycles 21))))
|
((m32r2 (unit u-exec (cycles 21))))
|
)
|
)
|
|
|
(dni divb "divb"
|
(dni divb "divb"
|
((MACH m32r2))
|
((MACH m32r2))
|
"divb $dr,$sr"
|
"divb $dr,$sr"
|
(+ OP1_9 OP2_0 dr sr (f-simm16 #x18))
|
(+ OP1_9 OP2_0 dr sr (f-simm16 #x18))
|
(if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))
|
(if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))
|
((m32r2 (unit u-exec (cycles 21))))
|
((m32r2 (unit u-exec (cycles 21))))
|
)
|
)
|
|
|
(dni divub "divub"
|
(dni divub "divub"
|
((MACH m32r2))
|
((MACH m32r2))
|
"divub $dr,$sr"
|
"divub $dr,$sr"
|
(+ OP1_9 OP2_1 dr sr (f-simm16 #x18))
|
(+ OP1_9 OP2_1 dr sr (f-simm16 #x18))
|
(if (ne sr (const 0)) (set dr (udiv dr sr)))
|
(if (ne sr (const 0)) (set dr (udiv dr sr)))
|
((m32r2 (unit u-exec (cycles 21))))
|
((m32r2 (unit u-exec (cycles 21))))
|
)
|
)
|
|
|
(dni divh "divh"
|
(dni divh "divh"
|
((MACH m32rx,m32r2) (IDOC ALU))
|
((MACH m32rx,m32r2) (IDOC ALU))
|
"divh $dr,$sr"
|
"divh $dr,$sr"
|
(+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
|
(+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
|
(if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
|
(if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
|
((m32rx (unit u-exec (cycles 21)))
|
((m32rx (unit u-exec (cycles 21)))
|
(m32r2 (unit u-exec (cycles 21))))
|
(m32r2 (unit u-exec (cycles 21))))
|
)
|
)
|
|
|
(dni jc "jc"
|
(dni jc "jc"
|
(COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
|
(COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
|
"jc $sr"
|
"jc $sr"
|
(+ OP1_1 (f-r1 12) OP2_12 sr)
|
(+ OP1_1 (f-r1 12) OP2_12 sr)
|
(if condbit (set pc (and sr (const -4))))
|
(if condbit (set pc (and sr (const -4))))
|
((m32rx (unit u-cti))
|
((m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dni jnc "jnc"
|
(dni jnc "jnc"
|
(COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
|
(COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
|
"jnc $sr"
|
"jnc $sr"
|
(+ OP1_1 (f-r1 13) OP2_12 sr)
|
(+ OP1_1 (f-r1 13) OP2_12 sr)
|
(if (not condbit) (set pc (and sr (const -4))))
|
(if (not condbit) (set pc (and sr (const -4))))
|
((m32rx (unit u-cti))
|
((m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dni jl "jl"
|
(dni jl "jl"
|
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
|
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
|
"jl $sr"
|
"jl $sr"
|
(+ OP1_1 (f-r1 14) OP2_12 sr)
|
(+ OP1_1 (f-r1 14) OP2_12 sr)
|
(parallel ()
|
(parallel ()
|
(set (reg h-gr 14)
|
(set (reg h-gr 14)
|
(add (and pc (const -4)) (const 4)))
|
(add (and pc (const -4)) (const 4)))
|
(set pc (and sr (const -4))))
|
(set pc (and sr (const -4))))
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(dni jmp "jmp"
|
(dni jmp "jmp"
|
(UNCOND-CTI (PIPE O) (IDOC BR))
|
(UNCOND-CTI (PIPE O) (IDOC BR))
|
"jmp $sr"
|
"jmp $sr"
|
(+ OP1_1 (f-r1 15) OP2_12 sr)
|
(+ OP1_1 (f-r1 15) OP2_12 sr)
|
(set pc (and sr (const -4)))
|
(set pc (and sr (const -4)))
|
; The above works now so this kludge has been commented out.
|
; The above works now so this kludge has been commented out.
|
; It's kept around because the f-r1 reference in the semantic part
|
; It's kept around because the f-r1 reference in the semantic part
|
; should work.
|
; should work.
|
; FIXME: kludge, instruction decoding not finished.
|
; FIXME: kludge, instruction decoding not finished.
|
; But this should work, so that's another FIXME.
|
; But this should work, so that's another FIXME.
|
;(sequence VOID (if VOID (eq SI f-r1 (const SI 14))
|
;(sequence VOID (if VOID (eq SI f-r1 (const SI 14))
|
; FIXME: abuf->insn should be a macro of some sort.
|
; FIXME: abuf->insn should be a macro of some sort.
|
;(sequence VOID
|
;(sequence VOID
|
; (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)")
|
; (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)")
|
; (const SI 14))
|
; (const SI 14))
|
; (set WI (reg WI h-gr 14)
|
; (set WI (reg WI h-gr 14)
|
; (add WI (and WI pc (const WI -4)) (const WI 4))))
|
; (add WI (and WI pc (const WI -4)) (const WI 4))))
|
; (set WI pc sr))
|
; (set WI pc sr))
|
((m32r/d (unit u-cti))
|
((m32r/d (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32rx (unit u-cti))
|
(m32r2 (unit u-cti)))
|
(m32r2 (unit u-cti)))
|
)
|
)
|
|
|
(define-pmacro (no-ext-expr mode expr) expr)
|
(define-pmacro (no-ext-expr mode expr) expr)
|
(define-pmacro (ext-expr mode expr) (ext mode expr))
|
(define-pmacro (ext-expr mode expr) (ext mode expr))
|
(define-pmacro (zext-expr mode expr) (zext mode expr))
|
(define-pmacro (zext-expr mode expr) (zext mode expr))
|
|
|
(define-pmacro (load-op suffix op2-op mode ext-op)
|
(define-pmacro (load-op suffix op2-op mode ext-op)
|
(begin
|
(begin
|
(dni (.sym ld suffix) (.str "ld" suffix)
|
(dni (.sym ld suffix) (.str "ld" suffix)
|
((PIPE O) (IDOC MEM))
|
((PIPE O) (IDOC MEM))
|
(.str "ld" suffix " $dr,@$sr")
|
(.str "ld" suffix " $dr,@$sr")
|
(+ OP1_2 op2-op dr sr)
|
(+ OP1_2 op2-op dr sr)
|
(set dr (ext-op WI (mem mode sr)))
|
(set dr (ext-op WI (mem mode sr)))
|
((m32r/d (unit u-load))
|
((m32r/d (unit u-load))
|
(m32rx (unit u-load))
|
(m32rx (unit u-load))
|
(m32r2 (unit u-load)))
|
(m32r2 (unit u-load)))
|
)
|
)
|
(dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
|
(dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
|
(NO-DIS (PIPE O) (IDOC MEM))
|
(NO-DIS (PIPE O) (IDOC MEM))
|
(.str "ld" suffix " $dr,@($sr)")
|
(.str "ld" suffix " $dr,@($sr)")
|
(emit (.sym ld suffix) dr sr))
|
(emit (.sym ld suffix) dr sr))
|
(dni (.sym ld suffix -d) (.str "ld" suffix "-d")
|
(dni (.sym ld suffix -d) (.str "ld" suffix "-d")
|
((IDOC MEM))
|
((IDOC MEM))
|
(.str "ld" suffix " $dr,@($slo16,$sr)")
|
(.str "ld" suffix " $dr,@($slo16,$sr)")
|
(+ OP1_10 op2-op dr sr slo16)
|
(+ OP1_10 op2-op dr sr slo16)
|
(set dr (ext-op WI (mem mode (add sr slo16))))
|
(set dr (ext-op WI (mem mode (add sr slo16))))
|
((m32r/d (unit u-load (cycles 2)))
|
((m32r/d (unit u-load (cycles 2)))
|
(m32rx (unit u-load (cycles 2)))
|
(m32rx (unit u-load (cycles 2)))
|
(m32r2 (unit u-load (cycles 2))))
|
(m32r2 (unit u-load (cycles 2))))
|
)
|
)
|
(dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
|
(dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
|
(NO-DIS (IDOC MEM))
|
(NO-DIS (IDOC MEM))
|
(.str "ld" suffix " $dr,@($sr,$slo16)")
|
(.str "ld" suffix " $dr,@($sr,$slo16)")
|
(emit (.sym ld suffix -d) dr sr slo16))
|
(emit (.sym ld suffix -d) dr sr slo16))
|
)
|
)
|
)
|
)
|
(load-op "" OP2_12 WI no-ext-expr)
|
(load-op "" OP2_12 WI no-ext-expr)
|
(load-op b OP2_8 QI ext-expr)
|
(load-op b OP2_8 QI ext-expr)
|
(load-op h OP2_10 HI ext-expr)
|
(load-op h OP2_10 HI ext-expr)
|
(load-op ub OP2_9 QI zext-expr)
|
(load-op ub OP2_9 QI zext-expr)
|
(load-op uh OP2_11 HI zext-expr)
|
(load-op uh OP2_11 HI zext-expr)
|
|
|
(dni ld-plus "ld+"
|
(dni ld-plus "ld+"
|
((PIPE O) (IDOC MEM))
|
((PIPE O) (IDOC MEM))
|
"ld $dr,@$sr+"
|
"ld $dr,@$sr+"
|
(+ OP1_2 dr OP2_14 sr)
|
(+ OP1_2 dr OP2_14 sr)
|
(parallel ()
|
(parallel ()
|
; wip: memory addresses in profiling support
|
; wip: memory addresses in profiling support
|
;(set dr (name ld-mem (mem WI sr)))
|
;(set dr (name ld-mem (mem WI sr)))
|
(set dr (mem WI sr))
|
(set dr (mem WI sr))
|
(set sr (add sr (const 4))))
|
(set sr (add sr (const 4))))
|
; Note: `pred' is the constraint. Also useful here is (ref name)
|
; Note: `pred' is the constraint. Also useful here is (ref name)
|
; and returns true if operand was referenced
|
; and returns true if operand was referenced
|
; (where "referenced" means _read_ if input operand and _written_ if
|
; (where "referenced" means _read_ if input operand and _written_ if
|
; output operand).
|
; output operand).
|
; args to unit are "unit-name (name1 value1) ..."
|
; args to unit are "unit-name (name1 value1) ..."
|
; - cycles(done),issue,pred are also specified this way
|
; - cycles(done),issue,pred are also specified this way
|
; - if unspecified, default is used
|
; - if unspecified, default is used
|
; - for ins/outs, extra arg is passed that says what was specified
|
; - for ins/outs, extra arg is passed that says what was specified
|
; - this is AND'd with `written' for outs
|
; - this is AND'd with `written' for outs
|
((m32r/d (unit u-load (pred (const 1)))
|
((m32r/d (unit u-load (pred (const 1)))
|
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
|
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
|
(m32rx (unit u-load)
|
(m32rx (unit u-load)
|
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
|
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
|
(m32r2 (unit u-load)
|
(m32r2 (unit u-load)
|
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
|
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
|
)
|
)
|
)
|
)
|
|
|
(dnmi pop "pop"
|
(dnmi pop "pop"
|
((PIPE O) (IDOC MEM))
|
((PIPE O) (IDOC MEM))
|
"pop $dr"
|
"pop $dr"
|
(emit ld-plus dr (sr 15)) ; "ld %0,@sp+"
|
(emit ld-plus dr (sr 15)) ; "ld %0,@sp+"
|
)
|
)
|
|
|
(dni ld24 "ld24"
|
(dni ld24 "ld24"
|
((IDOC MEM))
|
((IDOC MEM))
|
"ld24 $dr,$uimm24"
|
"ld24 $dr,$uimm24"
|
(+ OP1_14 dr uimm24)
|
(+ OP1_14 dr uimm24)
|
(set dr uimm24)
|
(set dr uimm24)
|
()
|
()
|
)
|
)
|
|
|
; ldi8 appears before ldi16 so we try the shorter version first
|
; ldi8 appears before ldi16 so we try the shorter version first
|
|
|
(dni ldi8 "ldi8"
|
(dni ldi8 "ldi8"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"ldi8 $dr,$simm8"
|
"ldi8 $dr,$simm8"
|
(+ OP1_6 dr simm8)
|
(+ OP1_6 dr simm8)
|
(set dr simm8)
|
(set dr simm8)
|
()
|
()
|
)
|
)
|
|
|
(dnmi ldi8a "ldi8 alias"
|
(dnmi ldi8a "ldi8 alias"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"ldi $dr,$simm8"
|
"ldi $dr,$simm8"
|
(emit ldi8 dr simm8)
|
(emit ldi8 dr simm8)
|
)
|
)
|
|
|
(dni ldi16 "ldi16"
|
(dni ldi16 "ldi16"
|
((IDOC ALU))
|
((IDOC ALU))
|
"ldi16 $dr,$hash$slo16"
|
"ldi16 $dr,$hash$slo16"
|
(+ OP1_9 OP2_15 (f-r2 0) dr slo16)
|
(+ OP1_9 OP2_15 (f-r2 0) dr slo16)
|
(set dr slo16)
|
(set dr slo16)
|
()
|
()
|
)
|
)
|
|
|
(dnmi ldi16a "ldi16 alias"
|
(dnmi ldi16a "ldi16 alias"
|
((IDOC ALU))
|
((IDOC ALU))
|
"ldi $dr,$hash$slo16"
|
"ldi $dr,$hash$slo16"
|
(emit ldi16 dr slo16)
|
(emit ldi16 dr slo16)
|
)
|
)
|
|
|
(dni lock "lock"
|
(dni lock "lock"
|
((PIPE O) (IDOC MISC))
|
((PIPE O) (IDOC MISC))
|
"lock $dr,@$sr"
|
"lock $dr,@$sr"
|
(+ OP1_2 OP2_13 dr sr)
|
(+ OP1_2 OP2_13 dr sr)
|
(sequence ()
|
(sequence ()
|
(set (reg h-lock) (const BI 1))
|
(set (reg h-lock) (const BI 1))
|
(set dr (mem WI sr)))
|
(set dr (mem WI sr)))
|
((m32r/d (unit u-load))
|
((m32r/d (unit u-load))
|
(m32rx (unit u-load))
|
(m32rx (unit u-load))
|
(m32r2 (unit u-load)))
|
(m32r2 (unit u-load)))
|
)
|
)
|
|
|
(dni machi "machi"
|
(dni machi "machi"
|
(
|
(
|
; (MACH m32r) is a temporary hack. This insn collides with machi-a
|
; (MACH m32r) is a temporary hack. This insn collides with machi-a
|
; in the simulator so disable it for m32rx.
|
; in the simulator so disable it for m32rx.
|
(MACH m32r) (PIPE S) (IDOC MAC)
|
(MACH m32r) (PIPE S) (IDOC MAC)
|
)
|
)
|
"machi $src1,$src2"
|
"machi $src1,$src2"
|
(+ OP1_3 OP2_4 src1 src2)
|
(+ OP1_3 OP2_4 src1 src2)
|
; FIXME: TRACE_RESULT will print the wrong thing since we
|
; FIXME: TRACE_RESULT will print the wrong thing since we
|
; alter one of the arguments.
|
; alter one of the arguments.
|
(set accum
|
(set accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(add DI
|
(add DI
|
accum
|
accum
|
(mul DI
|
(mul DI
|
(ext DI (and WI src1 (const #xffff0000)))
|
(ext DI (and WI src1 (const #xffff0000)))
|
(ext DI (trunc HI (sra WI src2 (const 16))))))
|
(ext DI (trunc HI (sra WI src2 (const 16))))))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni machi-a "machi-a"
|
(dni machi-a "machi-a"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"machi $src1,$src2,$acc"
|
"machi $src1,$src2,$acc"
|
(+ OP1_3 src1 acc (f-op23 4) src2)
|
(+ OP1_3 src1 acc (f-op23 4) src2)
|
(set acc
|
(set acc
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(add DI
|
(add DI
|
acc
|
acc
|
(mul DI
|
(mul DI
|
(ext DI (and WI src1 (const #xffff0000)))
|
(ext DI (and WI src1 (const #xffff0000)))
|
(ext DI (trunc HI (sra WI src2 (const 16))))))
|
(ext DI (trunc HI (sra WI src2 (const 16))))))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dni maclo "maclo"
|
(dni maclo "maclo"
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
"maclo $src1,$src2"
|
"maclo $src1,$src2"
|
(+ OP1_3 OP2_5 src1 src2)
|
(+ OP1_3 OP2_5 src1 src2)
|
(set accum
|
(set accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(add DI
|
(add DI
|
accum
|
accum
|
(mul DI
|
(mul DI
|
(ext DI (sll WI src1 (const 16)))
|
(ext DI (sll WI src1 (const 16)))
|
(ext DI (trunc HI src2))))
|
(ext DI (trunc HI src2))))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni maclo-a "maclo-a"
|
(dni maclo-a "maclo-a"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"maclo $src1,$src2,$acc"
|
"maclo $src1,$src2,$acc"
|
(+ OP1_3 src1 acc (f-op23 5) src2)
|
(+ OP1_3 src1 acc (f-op23 5) src2)
|
(set acc
|
(set acc
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(add DI
|
(add DI
|
acc
|
acc
|
(mul DI
|
(mul DI
|
(ext DI (sll WI src1 (const 16)))
|
(ext DI (sll WI src1 (const 16)))
|
(ext DI (trunc HI src2))))
|
(ext DI (trunc HI src2))))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dni macwhi "macwhi"
|
(dni macwhi "macwhi"
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
"macwhi $src1,$src2"
|
"macwhi $src1,$src2"
|
(+ OP1_3 OP2_6 src1 src2)
|
(+ OP1_3 OP2_6 src1 src2)
|
(set accum
|
(set accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(add DI
|
(add DI
|
accum
|
accum
|
(mul DI
|
(mul DI
|
(ext DI src1)
|
(ext DI src1)
|
(ext DI (trunc HI (sra WI src2 (const 16))))))
|
(ext DI (trunc HI (sra WI src2 (const 16))))))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni macwhi-a "macwhi-a"
|
(dni macwhi-a "macwhi-a"
|
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
|
"macwhi $src1,$src2,$acc"
|
"macwhi $src1,$src2,$acc"
|
(+ OP1_3 src1 acc (f-op23 6) src2)
|
(+ OP1_3 src1 acc (f-op23 6) src2)
|
; Note that this doesn't do the sign extension, which is correct.
|
; Note that this doesn't do the sign extension, which is correct.
|
(set acc
|
(set acc
|
(add acc
|
(add acc
|
(mul (ext DI src1)
|
(mul (ext DI src1)
|
(ext DI (trunc HI (sra src2 (const 16)))))))
|
(ext DI (trunc HI (sra src2 (const 16)))))))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dni macwlo "macwlo"
|
(dni macwlo "macwlo"
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
"macwlo $src1,$src2"
|
"macwlo $src1,$src2"
|
(+ OP1_3 OP2_7 src1 src2)
|
(+ OP1_3 OP2_7 src1 src2)
|
(set accum
|
(set accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(add DI
|
(add DI
|
accum
|
accum
|
(mul DI
|
(mul DI
|
(ext DI src1)
|
(ext DI src1)
|
(ext DI (trunc HI src2))))
|
(ext DI (trunc HI src2))))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni macwlo-a "macwlo-a"
|
(dni macwlo-a "macwlo-a"
|
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
|
"macwlo $src1,$src2,$acc"
|
"macwlo $src1,$src2,$acc"
|
(+ OP1_3 src1 acc (f-op23 7) src2)
|
(+ OP1_3 src1 acc (f-op23 7) src2)
|
; Note that this doesn't do the sign extension, which is correct.
|
; Note that this doesn't do the sign extension, which is correct.
|
(set acc
|
(set acc
|
(add acc
|
(add acc
|
(mul (ext DI src1)
|
(mul (ext DI src1)
|
(ext DI (trunc HI src2)))))
|
(ext DI (trunc HI src2)))))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dni mul "mul"
|
(dni mul "mul"
|
((PIPE S) (IDOC ALU))
|
((PIPE S) (IDOC ALU))
|
"mul $dr,$sr"
|
"mul $dr,$sr"
|
(+ OP1_1 OP2_6 dr sr)
|
(+ OP1_1 OP2_6 dr sr)
|
(set dr (mul dr sr))
|
(set dr (mul dr sr))
|
((m32r/d (unit u-exec (cycles 4)))
|
((m32r/d (unit u-exec (cycles 4)))
|
(m32rx (unit u-exec (cycles 4)))
|
(m32rx (unit u-exec (cycles 4)))
|
(m32r2 (unit u-exec (cycles 4))))
|
(m32r2 (unit u-exec (cycles 4))))
|
)
|
)
|
|
|
(dni mulhi "mulhi"
|
(dni mulhi "mulhi"
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
"mulhi $src1,$src2"
|
"mulhi $src1,$src2"
|
(+ OP1_3 OP2_0 src1 src2)
|
(+ OP1_3 OP2_0 src1 src2)
|
(set accum
|
(set accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(mul DI
|
(mul DI
|
(ext DI (and WI src1 (const #xffff0000)))
|
(ext DI (and WI src1 (const #xffff0000)))
|
(ext DI (trunc HI (sra WI src2 (const 16)))))
|
(ext DI (trunc HI (sra WI src2 (const 16)))))
|
(const 16))
|
(const 16))
|
(const 16)))
|
(const 16)))
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni mulhi-a "mulhi-a"
|
(dni mulhi-a "mulhi-a"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
"mulhi $src1,$src2,$acc"
|
"mulhi $src1,$src2,$acc"
|
(+ OP1_3 (f-op23 0) src1 acc src2)
|
(+ OP1_3 (f-op23 0) src1 acc src2)
|
(set acc
|
(set acc
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(mul DI
|
(mul DI
|
(ext DI (and WI src1 (const #xffff0000)))
|
(ext DI (and WI src1 (const #xffff0000)))
|
(ext DI (trunc HI (sra WI src2 (const 16)))))
|
(ext DI (trunc HI (sra WI src2 (const 16)))))
|
(const 16))
|
(const 16))
|
(const 16)))
|
(const 16)))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dni mullo "mullo"
|
(dni mullo "mullo"
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
"mullo $src1,$src2"
|
"mullo $src1,$src2"
|
(+ OP1_3 OP2_1 src1 src2)
|
(+ OP1_3 OP2_1 src1 src2)
|
(set accum
|
(set accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(mul DI
|
(mul DI
|
(ext DI (sll WI src1 (const 16)))
|
(ext DI (sll WI src1 (const 16)))
|
(ext DI (trunc HI src2)))
|
(ext DI (trunc HI src2)))
|
(const 16))
|
(const 16))
|
(const 16)))
|
(const 16)))
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni mullo-a "mullo-a"
|
(dni mullo-a "mullo-a"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
"mullo $src1,$src2,$acc"
|
"mullo $src1,$src2,$acc"
|
(+ OP1_3 src1 acc (f-op23 1) src2)
|
(+ OP1_3 src1 acc (f-op23 1) src2)
|
(set acc
|
(set acc
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(mul DI
|
(mul DI
|
(ext DI (sll WI src1 (const 16)))
|
(ext DI (sll WI src1 (const 16)))
|
(ext DI (trunc HI src2)))
|
(ext DI (trunc HI src2)))
|
(const 16))
|
(const 16))
|
(const 16)))
|
(const 16)))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dni mulwhi "mulwhi"
|
(dni mulwhi "mulwhi"
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
"mulwhi $src1,$src2"
|
"mulwhi $src1,$src2"
|
(+ OP1_3 OP2_2 src1 src2)
|
(+ OP1_3 OP2_2 src1 src2)
|
(set accum
|
(set accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(mul DI
|
(mul DI
|
(ext DI src1)
|
(ext DI src1)
|
(ext DI (trunc HI (sra WI src2 (const 16)))))
|
(ext DI (trunc HI (sra WI src2 (const 16)))))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni mulwhi-a "mulwhi-a"
|
(dni mulwhi-a "mulwhi-a"
|
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
|
"mulwhi $src1,$src2,$acc"
|
"mulwhi $src1,$src2,$acc"
|
(+ OP1_3 src1 acc (f-op23 2) src2)
|
(+ OP1_3 src1 acc (f-op23 2) src2)
|
; Note that this doesn't do the sign extension, which is correct.
|
; Note that this doesn't do the sign extension, which is correct.
|
(set acc
|
(set acc
|
(mul (ext DI src1)
|
(mul (ext DI src1)
|
(ext DI (trunc HI (sra src2 (const 16))))))
|
(ext DI (trunc HI (sra src2 (const 16))))))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dni mulwlo "mulwlo"
|
(dni mulwlo "mulwlo"
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
"mulwlo $src1,$src2"
|
"mulwlo $src1,$src2"
|
(+ OP1_3 OP2_3 src1 src2)
|
(+ OP1_3 OP2_3 src1 src2)
|
(set accum
|
(set accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(mul DI
|
(mul DI
|
(ext DI src1)
|
(ext DI src1)
|
(ext DI (trunc HI src2)))
|
(ext DI (trunc HI src2)))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni mulwlo-a "mulwlo-a"
|
(dni mulwlo-a "mulwlo-a"
|
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
|
"mulwlo $src1,$src2,$acc"
|
"mulwlo $src1,$src2,$acc"
|
(+ OP1_3 src1 acc (f-op23 3) src2)
|
(+ OP1_3 src1 acc (f-op23 3) src2)
|
; Note that this doesn't do the sign extension, which is correct.
|
; Note that this doesn't do the sign extension, which is correct.
|
(set acc
|
(set acc
|
(mul (ext DI src1)
|
(mul (ext DI src1)
|
(ext DI (trunc HI src2))))
|
(ext DI (trunc HI src2))))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dni mv "mv"
|
(dni mv "mv"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"mv $dr,$sr"
|
"mv $dr,$sr"
|
(+ OP1_1 OP2_8 dr sr)
|
(+ OP1_1 OP2_8 dr sr)
|
(set dr sr)
|
(set dr sr)
|
()
|
()
|
)
|
)
|
|
|
(dni mvfachi "mvfachi"
|
(dni mvfachi "mvfachi"
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
"mvfachi $dr"
|
"mvfachi $dr"
|
(+ OP1_5 OP2_15 (f-r2 0) dr)
|
(+ OP1_5 OP2_15 (f-r2 0) dr)
|
(set dr (trunc WI (sra DI accum (const 32))))
|
(set dr (trunc WI (sra DI accum (const 32))))
|
((m32r/d (unit u-exec (cycles 2))))
|
((m32r/d (unit u-exec (cycles 2))))
|
)
|
)
|
|
|
(dni mvfachi-a "mvfachi-a"
|
(dni mvfachi-a "mvfachi-a"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
"mvfachi $dr,$accs"
|
"mvfachi $dr,$accs"
|
(+ OP1_5 dr OP2_15 accs (f-op3 0))
|
(+ OP1_5 dr OP2_15 accs (f-op3 0))
|
(set dr (trunc WI (sra DI accs (const 32))))
|
(set dr (trunc WI (sra DI accs (const 32))))
|
((m32rx (unit u-exec (cycles 2)))
|
((m32rx (unit u-exec (cycles 2)))
|
(m32r2 (unit u-exec (cycles 2))))
|
(m32r2 (unit u-exec (cycles 2))))
|
)
|
)
|
|
|
(dni mvfaclo "mvfaclo"
|
(dni mvfaclo "mvfaclo"
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
"mvfaclo $dr"
|
"mvfaclo $dr"
|
(+ OP1_5 OP2_15 (f-r2 1) dr)
|
(+ OP1_5 OP2_15 (f-r2 1) dr)
|
(set dr (trunc WI accum))
|
(set dr (trunc WI accum))
|
((m32r/d (unit u-exec (cycles 2))))
|
((m32r/d (unit u-exec (cycles 2))))
|
)
|
)
|
|
|
(dni mvfaclo-a "mvfaclo-a"
|
(dni mvfaclo-a "mvfaclo-a"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
"mvfaclo $dr,$accs"
|
"mvfaclo $dr,$accs"
|
(+ OP1_5 dr OP2_15 accs (f-op3 1))
|
(+ OP1_5 dr OP2_15 accs (f-op3 1))
|
(set dr (trunc WI accs))
|
(set dr (trunc WI accs))
|
((m32rx (unit u-exec (cycles 2)))
|
((m32rx (unit u-exec (cycles 2)))
|
(m32r2 (unit u-exec (cycles 2))))
|
(m32r2 (unit u-exec (cycles 2))))
|
)
|
)
|
|
|
(dni mvfacmi "mvfacmi"
|
(dni mvfacmi "mvfacmi"
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
"mvfacmi $dr"
|
"mvfacmi $dr"
|
(+ OP1_5 OP2_15 (f-r2 2) dr)
|
(+ OP1_5 OP2_15 (f-r2 2) dr)
|
(set dr (trunc WI (sra DI accum (const 16))))
|
(set dr (trunc WI (sra DI accum (const 16))))
|
((m32r/d (unit u-exec (cycles 2))))
|
((m32r/d (unit u-exec (cycles 2))))
|
)
|
)
|
|
|
(dni mvfacmi-a "mvfacmi-a"
|
(dni mvfacmi-a "mvfacmi-a"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
"mvfacmi $dr,$accs"
|
"mvfacmi $dr,$accs"
|
(+ OP1_5 dr OP2_15 accs (f-op3 2))
|
(+ OP1_5 dr OP2_15 accs (f-op3 2))
|
(set dr (trunc WI (sra DI accs (const 16))))
|
(set dr (trunc WI (sra DI accs (const 16))))
|
((m32rx (unit u-exec (cycles 2)))
|
((m32rx (unit u-exec (cycles 2)))
|
(m32r2 (unit u-exec (cycles 2))))
|
(m32r2 (unit u-exec (cycles 2))))
|
)
|
)
|
|
|
(dni mvfc "mvfc"
|
(dni mvfc "mvfc"
|
((PIPE O) (IDOC MISC))
|
((PIPE O) (IDOC MISC))
|
"mvfc $dr,$scr"
|
"mvfc $dr,$scr"
|
(+ OP1_1 OP2_9 dr scr)
|
(+ OP1_1 OP2_9 dr scr)
|
(set dr scr)
|
(set dr scr)
|
()
|
()
|
)
|
)
|
|
|
(dni mvtachi "mvtachi"
|
(dni mvtachi "mvtachi"
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
"mvtachi $src1"
|
"mvtachi $src1"
|
(+ OP1_5 OP2_7 (f-r2 0) src1)
|
(+ OP1_5 OP2_7 (f-r2 0) src1)
|
(set accum
|
(set accum
|
(or DI
|
(or DI
|
(and DI accum (const DI #xffffffff))
|
(and DI accum (const DI #xffffffff))
|
(sll DI (ext DI src1) (const 32))))
|
(sll DI (ext DI src1) (const 32))))
|
((m32r/d (unit u-exec (in sr src1))))
|
((m32r/d (unit u-exec (in sr src1))))
|
)
|
)
|
|
|
(dni mvtachi-a "mvtachi-a"
|
(dni mvtachi-a "mvtachi-a"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
"mvtachi $src1,$accs"
|
"mvtachi $src1,$accs"
|
(+ OP1_5 src1 OP2_7 accs (f-op3 0))
|
(+ OP1_5 src1 OP2_7 accs (f-op3 0))
|
(set accs
|
(set accs
|
(or DI
|
(or DI
|
(and DI accs (const DI #xffffffff))
|
(and DI accs (const DI #xffffffff))
|
(sll DI (ext DI src1) (const 32))))
|
(sll DI (ext DI src1) (const 32))))
|
((m32rx (unit u-exec (in sr src1)))
|
((m32rx (unit u-exec (in sr src1)))
|
(m32r2 (unit u-exec (in sr src1))))
|
(m32r2 (unit u-exec (in sr src1))))
|
)
|
)
|
|
|
(dni mvtaclo "mvtaclo"
|
(dni mvtaclo "mvtaclo"
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
((MACH m32r) (PIPE S) (IDOC ACCUM))
|
"mvtaclo $src1"
|
"mvtaclo $src1"
|
(+ OP1_5 OP2_7 (f-r2 1) src1)
|
(+ OP1_5 OP2_7 (f-r2 1) src1)
|
(set accum
|
(set accum
|
(or DI
|
(or DI
|
(and DI accum (const DI #xffffffff00000000))
|
(and DI accum (const DI #xffffffff00000000))
|
(zext DI src1)))
|
(zext DI src1)))
|
((m32r/d (unit u-exec (in sr src1))))
|
((m32r/d (unit u-exec (in sr src1))))
|
)
|
)
|
|
|
(dni mvtaclo-a "mvtaclo-a"
|
(dni mvtaclo-a "mvtaclo-a"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
"mvtaclo $src1,$accs"
|
"mvtaclo $src1,$accs"
|
(+ OP1_5 src1 OP2_7 accs (f-op3 1))
|
(+ OP1_5 src1 OP2_7 accs (f-op3 1))
|
(set accs
|
(set accs
|
(or DI
|
(or DI
|
(and DI accs (const DI #xffffffff00000000))
|
(and DI accs (const DI #xffffffff00000000))
|
(zext DI src1)))
|
(zext DI src1)))
|
((m32rx (unit u-exec (in sr src1)))
|
((m32rx (unit u-exec (in sr src1)))
|
(m32r2 (unit u-exec (in sr src1))))
|
(m32r2 (unit u-exec (in sr src1))))
|
)
|
)
|
|
|
(dni mvtc "mvtc"
|
(dni mvtc "mvtc"
|
((PIPE O) (IDOC MISC))
|
((PIPE O) (IDOC MISC))
|
"mvtc $sr,$dcr"
|
"mvtc $sr,$dcr"
|
(+ OP1_1 OP2_10 dcr sr)
|
(+ OP1_1 OP2_10 dcr sr)
|
(set dcr sr)
|
(set dcr sr)
|
()
|
()
|
)
|
)
|
|
|
(dni neg "neg"
|
(dni neg "neg"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"neg $dr,$sr"
|
"neg $dr,$sr"
|
(+ OP1_0 OP2_3 dr sr)
|
(+ OP1_0 OP2_3 dr sr)
|
(set dr (neg sr))
|
(set dr (neg sr))
|
()
|
()
|
)
|
)
|
|
|
(dni nop "nop"
|
(dni nop "nop"
|
((PIPE OS) (IDOC MISC))
|
((PIPE OS) (IDOC MISC))
|
"nop"
|
"nop"
|
(+ OP1_7 OP2_0 (f-r1 0) (f-r2 0))
|
(+ OP1_7 OP2_0 (f-r1 0) (f-r2 0))
|
(c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n")
|
(c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n")
|
; FIXME: quick hack: parallel nops don't contribute to cycle count.
|
; FIXME: quick hack: parallel nops don't contribute to cycle count.
|
; Other kinds of nops do however (which we currently ignore).
|
; Other kinds of nops do however (which we currently ignore).
|
((m32r/d (unit u-exec (cycles 0)))
|
((m32r/d (unit u-exec (cycles 0)))
|
(m32rx (unit u-exec (cycles 0)))
|
(m32rx (unit u-exec (cycles 0)))
|
(m32r2 (unit u-exec (cycles 0))))
|
(m32r2 (unit u-exec (cycles 0))))
|
)
|
)
|
|
|
(dni not "not"
|
(dni not "not"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"not $dr,$sr"
|
"not $dr,$sr"
|
(+ OP1_0 OP2_11 dr sr)
|
(+ OP1_0 OP2_11 dr sr)
|
(set dr (inv sr))
|
(set dr (inv sr))
|
()
|
()
|
)
|
)
|
|
|
(dni rac "rac"
|
(dni rac "rac"
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
"rac"
|
"rac"
|
(+ OP1_5 OP2_9 (f-r1 0) (f-r2 0))
|
(+ OP1_5 OP2_9 (f-r1 0) (f-r2 0))
|
(sequence ((DI tmp1))
|
(sequence ((DI tmp1))
|
(set tmp1 (sll DI accum (const 1)))
|
(set tmp1 (sll DI accum (const 1)))
|
(set tmp1 (add DI tmp1 (const DI #x8000)))
|
(set tmp1 (add DI tmp1 (const DI #x8000)))
|
(set accum
|
(set accum
|
(cond DI
|
(cond DI
|
((gt tmp1 (const DI #x00007fffffff0000))
|
((gt tmp1 (const DI #x00007fffffff0000))
|
(const DI #x00007fffffff0000))
|
(const DI #x00007fffffff0000))
|
((lt tmp1 (const DI #xffff800000000000))
|
((lt tmp1 (const DI #xffff800000000000))
|
(const DI #xffff800000000000))
|
(const DI #xffff800000000000))
|
(else (and tmp1 (const DI #xffffffffffff0000)))))
|
(else (and tmp1 (const DI #xffffffffffff0000)))))
|
)
|
)
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni rac-dsi "rac-dsi"
|
(dni rac-dsi "rac-dsi"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"rac $accd,$accs,$imm1"
|
"rac $accd,$accs,$imm1"
|
(+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
|
(+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
|
(sequence ((DI tmp1))
|
(sequence ((DI tmp1))
|
(set tmp1 (sll accs imm1))
|
(set tmp1 (sll accs imm1))
|
(set tmp1 (add tmp1 (const DI #x8000)))
|
(set tmp1 (add tmp1 (const DI #x8000)))
|
(set accd
|
(set accd
|
(cond DI
|
(cond DI
|
((gt tmp1 (const DI #x00007fffffff0000))
|
((gt tmp1 (const DI #x00007fffffff0000))
|
(const DI #x00007fffffff0000))
|
(const DI #x00007fffffff0000))
|
((lt tmp1 (const DI #xffff800000000000))
|
((lt tmp1 (const DI #xffff800000000000))
|
(const DI #xffff800000000000))
|
(const DI #xffff800000000000))
|
(else (and tmp1 (const DI #xffffffffffff0000)))))
|
(else (and tmp1 (const DI #xffffffffffff0000)))))
|
)
|
)
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dnmi rac-d "rac-d"
|
(dnmi rac-d "rac-d"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"rac $accd"
|
"rac $accd"
|
(emit rac-dsi accd (f-accs 0) (f-imm1 0))
|
(emit rac-dsi accd (f-accs 0) (f-imm1 0))
|
)
|
)
|
|
|
(dnmi rac-ds "rac-ds"
|
(dnmi rac-ds "rac-ds"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"rac $accd,$accs"
|
"rac $accd,$accs"
|
(emit rac-dsi accd accs (f-imm1 0))
|
(emit rac-dsi accd accs (f-imm1 0))
|
)
|
)
|
|
|
|
|
(dni rach "rach"
|
(dni rach "rach"
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
((MACH m32r) (PIPE S) (IDOC MAC))
|
"rach"
|
"rach"
|
(+ OP1_5 OP2_8 (f-r1 0) (f-r2 0))
|
(+ OP1_5 OP2_8 (f-r1 0) (f-r2 0))
|
(sequence ((DI tmp1))
|
(sequence ((DI tmp1))
|
; Lop off top 8 bits.
|
; Lop off top 8 bits.
|
; The sign bit we want to use is bit 55 so the 64 bit value
|
; The sign bit we want to use is bit 55 so the 64 bit value
|
; isn't properly signed which we deal with in the if's below.
|
; isn't properly signed which we deal with in the if's below.
|
(set tmp1 (and accum (const DI #xffffffffffffff)))
|
(set tmp1 (and accum (const DI #xffffffffffffff)))
|
(if (andif (ge tmp1 (const DI #x003fff80000000))
|
(if (andif (ge tmp1 (const DI #x003fff80000000))
|
(le tmp1 (const DI #x7fffffffffffff)))
|
(le tmp1 (const DI #x7fffffffffffff)))
|
(set tmp1 (const DI #x003fff80000000))
|
(set tmp1 (const DI #x003fff80000000))
|
; else part
|
; else part
|
(if (andif (ge tmp1 (const DI #x80000000000000))
|
(if (andif (ge tmp1 (const DI #x80000000000000))
|
(le tmp1 (const DI #xffc00000000000)))
|
(le tmp1 (const DI #xffc00000000000)))
|
(set tmp1 (const DI #xffc00000000000))
|
(set tmp1 (const DI #xffc00000000000))
|
(set tmp1 (and (add accum (const DI #x40000000))
|
(set tmp1 (and (add accum (const DI #x40000000))
|
(const DI #xffffffff80000000)))))
|
(const DI #xffffffff80000000)))))
|
(set tmp1 (sll tmp1 (const 1)))
|
(set tmp1 (sll tmp1 (const 1)))
|
; Sign extend top 8 bits.
|
; Sign extend top 8 bits.
|
(set accum
|
(set accum
|
; FIXME: 7?
|
; FIXME: 7?
|
(sra DI (sll DI tmp1 (const 7)) (const 7)))
|
(sra DI (sll DI tmp1 (const 7)) (const 7)))
|
)
|
)
|
((m32r/d (unit u-mac)))
|
((m32r/d (unit u-mac)))
|
)
|
)
|
|
|
(dni rach-dsi "rach-dsi"
|
(dni rach-dsi "rach-dsi"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"rach $accd,$accs,$imm1"
|
"rach $accd,$accs,$imm1"
|
(+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
|
(+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
|
(sequence ((DI tmp1))
|
(sequence ((DI tmp1))
|
(set tmp1 (sll accs imm1))
|
(set tmp1 (sll accs imm1))
|
(set tmp1 (add tmp1 (const DI #x80000000)))
|
(set tmp1 (add tmp1 (const DI #x80000000)))
|
(set accd
|
(set accd
|
(cond DI
|
(cond DI
|
((gt tmp1 (const DI #x00007fff00000000))
|
((gt tmp1 (const DI #x00007fff00000000))
|
(const DI #x00007fff00000000))
|
(const DI #x00007fff00000000))
|
((lt tmp1 (const DI #xffff800000000000))
|
((lt tmp1 (const DI #xffff800000000000))
|
(const DI #xffff800000000000))
|
(const DI #xffff800000000000))
|
(else (and tmp1 (const DI #xffffffff00000000)))))
|
(else (and tmp1 (const DI #xffffffff00000000)))))
|
)
|
)
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
(dnmi rach-d "rach-d"
|
(dnmi rach-d "rach-d"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"rach $accd"
|
"rach $accd"
|
(emit rach-dsi accd (f-accs 0) (f-imm1 0))
|
(emit rach-dsi accd (f-accs 0) (f-imm1 0))
|
)
|
)
|
|
|
(dnmi rach-ds "rach-ds"
|
(dnmi rach-ds "rach-ds"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"rach $accd,$accs"
|
"rach $accd,$accs"
|
(emit rach-dsi accd accs (f-imm1 0))
|
(emit rach-dsi accd accs (f-imm1 0))
|
)
|
)
|
|
|
(dni rte "rte"
|
(dni rte "rte"
|
(UNCOND-CTI (PIPE O) (IDOC BR))
|
(UNCOND-CTI (PIPE O) (IDOC BR))
|
"rte"
|
"rte"
|
(+ OP1_1 OP2_13 (f-r1 0) (f-r2 6))
|
(+ OP1_1 OP2_13 (f-r1 0) (f-r2 6))
|
(sequence ()
|
(sequence ()
|
; pc = bpc & -4
|
; pc = bpc & -4
|
(set pc (and (reg h-cr 6) (const -4)))
|
(set pc (and (reg h-cr 6) (const -4)))
|
; bpc = bbpc
|
; bpc = bbpc
|
(set (reg h-cr 6) (reg h-cr 14))
|
(set (reg h-cr 6) (reg h-cr 14))
|
; psw = bpsw
|
; psw = bpsw
|
(set (reg h-psw) (reg h-bpsw))
|
(set (reg h-psw) (reg h-bpsw))
|
; bpsw = bbpsw
|
; bpsw = bbpsw
|
(set (reg h-bpsw) (reg h-bbpsw))
|
(set (reg h-bpsw) (reg h-bbpsw))
|
)
|
)
|
()
|
()
|
)
|
)
|
|
|
(dni seth "seth"
|
(dni seth "seth"
|
((IDOC ALU))
|
((IDOC ALU))
|
"seth $dr,$hash$hi16"
|
"seth $dr,$hash$hi16"
|
(+ OP1_13 OP2_12 dr (f-r2 0) hi16)
|
(+ OP1_13 OP2_12 dr (f-r2 0) hi16)
|
(set dr (sll WI hi16 (const 16)))
|
(set dr (sll WI hi16 (const 16)))
|
()
|
()
|
)
|
)
|
|
|
(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
|
(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
|
(begin
|
(begin
|
(dni sym sym ((PIPE O_OS) (IDOC ALU))
|
(dni sym sym ((PIPE O_OS) (IDOC ALU))
|
(.str sym " $dr,$sr")
|
(.str sym " $dr,$sr")
|
(+ OP1_1 op2-r-op dr sr)
|
(+ OP1_1 op2-r-op dr sr)
|
(set dr (sem-op dr (and sr (const 31))))
|
(set dr (sem-op dr (and sr (const 31))))
|
()
|
()
|
)
|
)
|
(dni (.sym sym "3") sym ((IDOC ALU))
|
(dni (.sym sym "3") sym ((IDOC ALU))
|
(.str sym "3 $dr,$sr,$simm16")
|
(.str sym "3 $dr,$sr,$simm16")
|
(+ OP1_9 op2-3-op dr sr simm16)
|
(+ OP1_9 op2-3-op dr sr simm16)
|
(set dr (sem-op sr (and WI simm16 (const 31))))
|
(set dr (sem-op sr (and WI simm16 (const 31))))
|
()
|
()
|
)
|
)
|
(dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
|
(dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
|
(.str sym "i $dr,$uimm5")
|
(.str sym "i $dr,$uimm5")
|
(+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
|
(+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
|
(set dr (sem-op dr uimm5))
|
(set dr (sem-op dr uimm5))
|
()
|
()
|
)
|
)
|
)
|
)
|
)
|
)
|
(shift-op sll OP2_4 OP2_12 2 sll)
|
(shift-op sll OP2_4 OP2_12 2 sll)
|
(shift-op sra OP2_2 OP2_10 1 sra)
|
(shift-op sra OP2_2 OP2_10 1 sra)
|
(shift-op srl OP2_0 OP2_8 0 srl)
|
(shift-op srl OP2_0 OP2_8 0 srl)
|
|
|
(define-pmacro (store-op suffix op2-op mode)
|
(define-pmacro (store-op suffix op2-op mode)
|
(begin
|
(begin
|
(dni (.sym st suffix) (.str "st" suffix)
|
(dni (.sym st suffix) (.str "st" suffix)
|
((PIPE O) (IDOC MEM))
|
((PIPE O) (IDOC MEM))
|
(.str "st" suffix " $src1,@$src2")
|
(.str "st" suffix " $src1,@$src2")
|
(+ OP1_2 op2-op src1 src2)
|
(+ OP1_2 op2-op src1 src2)
|
(set mode (mem mode src2) src1)
|
(set mode (mem mode src2) src1)
|
((m32r/d (unit u-store (cycles 1)))
|
((m32r/d (unit u-store (cycles 1)))
|
(m32rx (unit u-store (cycles 1)))
|
(m32rx (unit u-store (cycles 1)))
|
(m32r2 (unit u-store (cycles 1))))
|
(m32r2 (unit u-store (cycles 1))))
|
)
|
)
|
(dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
|
(dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
|
(NO-DIS (PIPE O) (IDOC MEM))
|
(NO-DIS (PIPE O) (IDOC MEM))
|
(.str "st" suffix " $src1,@($src2)")
|
(.str "st" suffix " $src1,@($src2)")
|
(emit (.sym st suffix) src1 src2))
|
(emit (.sym st suffix) src1 src2))
|
(dni (.sym st suffix -d) (.str "st" suffix "-d")
|
(dni (.sym st suffix -d) (.str "st" suffix "-d")
|
((IDOC MEM))
|
((IDOC MEM))
|
(.str "st" suffix " $src1,@($slo16,$src2)")
|
(.str "st" suffix " $src1,@($slo16,$src2)")
|
(+ OP1_10 op2-op src1 src2 slo16)
|
(+ OP1_10 op2-op src1 src2 slo16)
|
(set mode (mem mode (add src2 slo16)) src1)
|
(set mode (mem mode (add src2 slo16)) src1)
|
((m32r/d (unit u-store (cycles 2)))
|
((m32r/d (unit u-store (cycles 2)))
|
(m32rx (unit u-store (cycles 2)))
|
(m32rx (unit u-store (cycles 2)))
|
(m32r2 (unit u-store (cycles 2))))
|
(m32r2 (unit u-store (cycles 2))))
|
)
|
)
|
(dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
|
(dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
|
(NO-DIS (IDOC MEM))
|
(NO-DIS (IDOC MEM))
|
(.str "st" suffix " $src1,@($src2,$slo16)")
|
(.str "st" suffix " $src1,@($src2,$slo16)")
|
(emit (.sym st suffix -d) src1 src2 slo16))
|
(emit (.sym st suffix -d) src1 src2 slo16))
|
)
|
)
|
)
|
)
|
(store-op "" OP2_4 WI)
|
(store-op "" OP2_4 WI)
|
(store-op b OP2_0 QI)
|
(store-op b OP2_0 QI)
|
(store-op h OP2_2 HI)
|
(store-op h OP2_2 HI)
|
|
|
(dni st-plus "st+"
|
(dni st-plus "st+"
|
((PIPE O) (IDOC MEM))
|
((PIPE O) (IDOC MEM))
|
"st $src1,@+$src2"
|
"st $src1,@+$src2"
|
(+ OP1_2 OP2_6 src1 src2)
|
(+ OP1_2 OP2_6 src1 src2)
|
; This has to be coded carefully to avoid an "earlyclobber" of src2.
|
; This has to be coded carefully to avoid an "earlyclobber" of src2.
|
(sequence ((WI new-src2))
|
(sequence ((WI new-src2))
|
(set new-src2 (add WI src2 (const WI 4)))
|
(set new-src2 (add WI src2 (const WI 4)))
|
(set (mem WI new-src2) src1)
|
(set (mem WI new-src2) src1)
|
(set src2 new-src2))
|
(set src2 new-src2))
|
((m32r/d (unit u-store)
|
((m32r/d (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(m32rx (unit u-store)
|
(m32rx (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(m32r2 (unit u-store)
|
(m32r2 (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
)
|
)
|
)
|
)
|
|
|
(dni sth-plus "sth+"
|
(dni sth-plus "sth+"
|
((MACH m32rx,m32r2) (PIPE O) SPECIAL)
|
((MACH m32rx,m32r2) (PIPE O) SPECIAL)
|
"sth $src1,@$src2+"
|
"sth $src1,@$src2+"
|
(+ OP1_2 OP2_3 src1 src2)
|
(+ OP1_2 OP2_3 src1 src2)
|
; This has to be coded carefully to avoid an "earlyclobber" of src2.
|
; This has to be coded carefully to avoid an "earlyclobber" of src2.
|
(sequence ((HI new-src2))
|
(sequence ((HI new-src2))
|
(set (mem HI new-src2) src1)
|
(set (mem HI new-src2) src1)
|
(set new-src2 (add src2 (const 2)))
|
(set new-src2 (add src2 (const 2)))
|
(set src2 new-src2))
|
(set src2 new-src2))
|
((m32rx (unit u-store)
|
((m32rx (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(m32r2 (unit u-store)
|
(m32r2 (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
)
|
)
|
)
|
)
|
|
|
(dni stb-plus "stb+"
|
(dni stb-plus "stb+"
|
((MACH m32rx,m32r2) (PIPE O) SPECIAL)
|
((MACH m32rx,m32r2) (PIPE O) SPECIAL)
|
"stb $src1,@$src2+"
|
"stb $src1,@$src2+"
|
(+ OP1_2 OP2_1 src1 src2)
|
(+ OP1_2 OP2_1 src1 src2)
|
; This has to be coded carefully to avoid an "earlyclobber" of src2.
|
; This has to be coded carefully to avoid an "earlyclobber" of src2.
|
(sequence ((QI new-src2))
|
(sequence ((QI new-src2))
|
(set (mem QI new-src2) src1)
|
(set (mem QI new-src2) src1)
|
(set new-src2 (add src2 (const 1)))
|
(set new-src2 (add src2 (const 1)))
|
(set src2 new-src2))
|
(set src2 new-src2))
|
((m32rx (unit u-store)
|
((m32rx (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(m32r2 (unit u-store)
|
(m32r2 (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
)
|
)
|
)
|
)
|
|
|
(dni st-minus "st-"
|
(dni st-minus "st-"
|
((PIPE O) (IDOC MEM))
|
((PIPE O) (IDOC MEM))
|
"st $src1,@-$src2"
|
"st $src1,@-$src2"
|
(+ OP1_2 OP2_7 src1 src2)
|
(+ OP1_2 OP2_7 src1 src2)
|
; This is the original way. It doesn't work for parallel execution
|
; This is the original way. It doesn't work for parallel execution
|
; because of the earlyclobber of src2.
|
; because of the earlyclobber of src2.
|
;(sequence ()
|
;(sequence ()
|
; (set src2 (sub src2 (const 4)))
|
; (set src2 (sub src2 (const 4)))
|
; (set (mem WI src2) src1))
|
; (set (mem WI src2) src1))
|
(sequence ((WI new-src2))
|
(sequence ((WI new-src2))
|
(set new-src2 (sub src2 (const 4)))
|
(set new-src2 (sub src2 (const 4)))
|
(set (mem WI new-src2) src1)
|
(set (mem WI new-src2) src1)
|
(set src2 new-src2))
|
(set src2 new-src2))
|
((m32r/d (unit u-store)
|
((m32r/d (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(m32rx (unit u-store)
|
(m32rx (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(m32r2 (unit u-store)
|
(m32r2 (unit u-store)
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
|
)
|
)
|
)
|
)
|
|
|
(dnmi push "push" ((PIPE O) (IDOC MEM))
|
(dnmi push "push" ((PIPE O) (IDOC MEM))
|
"push $src1"
|
"push $src1"
|
(emit st-minus src1 (src2 15)) ; "st %0,@-sp"
|
(emit st-minus src1 (src2 15)) ; "st %0,@-sp"
|
)
|
)
|
|
|
(dni sub "sub"
|
(dni sub "sub"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"sub $dr,$sr"
|
"sub $dr,$sr"
|
(+ OP1_0 OP2_2 dr sr)
|
(+ OP1_0 OP2_2 dr sr)
|
(set dr (sub dr sr))
|
(set dr (sub dr sr))
|
()
|
()
|
)
|
)
|
|
|
(dni subv "sub:rv"
|
(dni subv "sub:rv"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"subv $dr,$sr"
|
"subv $dr,$sr"
|
(+ OP1_0 OP2_0 dr sr)
|
(+ OP1_0 OP2_0 dr sr)
|
(parallel ()
|
(parallel ()
|
(set dr (sub dr sr))
|
(set dr (sub dr sr))
|
(set condbit (sub-oflag dr sr (const 0))))
|
(set condbit (sub-oflag dr sr (const 0))))
|
()
|
()
|
)
|
)
|
|
|
(dni subx "sub:rx"
|
(dni subx "sub:rx"
|
((PIPE OS) (IDOC ALU))
|
((PIPE OS) (IDOC ALU))
|
"subx $dr,$sr"
|
"subx $dr,$sr"
|
(+ OP1_0 OP2_1 dr sr)
|
(+ OP1_0 OP2_1 dr sr)
|
(parallel ()
|
(parallel ()
|
(set dr (subc dr sr condbit))
|
(set dr (subc dr sr condbit))
|
(set condbit (sub-cflag dr sr condbit)))
|
(set condbit (sub-cflag dr sr condbit)))
|
()
|
()
|
)
|
)
|
|
|
(dni trap "trap"
|
(dni trap "trap"
|
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC))
|
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC))
|
"trap $uimm4"
|
"trap $uimm4"
|
(+ OP1_1 OP2_15 (f-r1 0) uimm4)
|
(+ OP1_1 OP2_15 (f-r1 0) uimm4)
|
(sequence ()
|
(sequence ()
|
; bbpc = bpc
|
; bbpc = bpc
|
(set (reg h-cr 14) (reg h-cr 6))
|
(set (reg h-cr 14) (reg h-cr 6))
|
; Set bpc to the return address. Actually it's not quite the
|
; Set bpc to the return address. Actually it's not quite the
|
; return address as RTE rounds the address down to a word
|
; return address as RTE rounds the address down to a word
|
; boundary.
|
; boundary.
|
(set (reg h-cr 6) (add pc (const 4)))
|
(set (reg h-cr 6) (add pc (const 4)))
|
; bbpsw = bpsw
|
; bbpsw = bpsw
|
(set (reg h-bbpsw) (reg h-bpsw))
|
(set (reg h-bbpsw) (reg h-bpsw))
|
; bpsw = psw
|
; bpsw = psw
|
(set (reg h-bpsw) (reg h-psw))
|
(set (reg h-bpsw) (reg h-psw))
|
; sm is unchanged, ie,c are set to zero.
|
; sm is unchanged, ie,c are set to zero.
|
(set (reg h-psw) (and (reg h-psw) (const #x80)))
|
(set (reg h-psw) (and (reg h-psw) (const #x80)))
|
; m32r_trap handles operating vs user mode
|
; m32r_trap handles operating vs user mode
|
(set WI pc (c-call WI "m32r_trap" pc uimm4))
|
(set WI pc (c-call WI "m32r_trap" pc uimm4))
|
)
|
)
|
()
|
()
|
)
|
)
|
|
|
(dni unlock "unlock"
|
(dni unlock "unlock"
|
((PIPE O) (IDOC MISC))
|
((PIPE O) (IDOC MISC))
|
"unlock $src1,@$src2"
|
"unlock $src1,@$src2"
|
(+ OP1_2 OP2_5 src1 src2)
|
(+ OP1_2 OP2_5 src1 src2)
|
(sequence ()
|
(sequence ()
|
(if (reg h-lock)
|
(if (reg h-lock)
|
(set (mem WI src2) src1))
|
(set (mem WI src2) src1))
|
(set (reg h-lock) (const BI 0)))
|
(set (reg h-lock) (const BI 0)))
|
((m32r/d (unit u-load))
|
((m32r/d (unit u-load))
|
(m32rx (unit u-load))
|
(m32rx (unit u-load))
|
(m32r2 (unit u-load)))
|
(m32r2 (unit u-load)))
|
)
|
)
|
|
|
; Saturate into byte.
|
; Saturate into byte.
|
(dni satb "satb"
|
(dni satb "satb"
|
((MACH m32rx,m32r2) (IDOC ALU))
|
((MACH m32rx,m32r2) (IDOC ALU))
|
"satb $dr,$sr"
|
"satb $dr,$sr"
|
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
|
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
|
(set dr
|
(set dr
|
; FIXME: min/max would simplify this nicely of course.
|
; FIXME: min/max would simplify this nicely of course.
|
(cond WI
|
(cond WI
|
((ge sr (const 127)) (const 127))
|
((ge sr (const 127)) (const 127))
|
((le sr (const -128)) (const -128))
|
((le sr (const -128)) (const -128))
|
(else sr)))
|
(else sr)))
|
()
|
()
|
)
|
)
|
|
|
; Saturate into half word.
|
; Saturate into half word.
|
(dni sath "sath"
|
(dni sath "sath"
|
((MACH m32rx,m32r2) (IDOC ALU))
|
((MACH m32rx,m32r2) (IDOC ALU))
|
"sath $dr,$sr"
|
"sath $dr,$sr"
|
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
|
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
|
(set dr
|
(set dr
|
(cond WI
|
(cond WI
|
((ge sr (const 32767)) (const 32767))
|
((ge sr (const 32767)) (const 32767))
|
((le sr (const -32768)) (const -32768))
|
((le sr (const -32768)) (const -32768))
|
(else sr)))
|
(else sr)))
|
()
|
()
|
)
|
)
|
|
|
; Saturate word.
|
; Saturate word.
|
(dni sat "sat"
|
(dni sat "sat"
|
((MACH m32rx,m32r2) SPECIAL (IDOC ALU))
|
((MACH m32rx,m32r2) SPECIAL (IDOC ALU))
|
"sat $dr,$sr"
|
"sat $dr,$sr"
|
(+ OP1_8 dr OP2_6 sr (f-uimm16 0))
|
(+ OP1_8 dr OP2_6 sr (f-uimm16 0))
|
(set dr
|
(set dr
|
(if WI condbit
|
(if WI condbit
|
(if WI (lt sr (const 0))
|
(if WI (lt sr (const 0))
|
(const #x7fffffff)
|
(const #x7fffffff)
|
(const #x80000000))
|
(const #x80000000))
|
sr))
|
sr))
|
()
|
()
|
)
|
)
|
|
|
; Parallel compare byte zeros.
|
; Parallel compare byte zeros.
|
; Set C bit in condition register if any byte in source register is zero.
|
; Set C bit in condition register if any byte in source register is zero.
|
(dni pcmpbz "pcmpbz"
|
(dni pcmpbz "pcmpbz"
|
((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
|
((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
|
"pcmpbz $src2"
|
"pcmpbz $src2"
|
(+ OP1_0 (f-r1 3) OP2_7 src2)
|
(+ OP1_0 (f-r1 3) OP2_7 src2)
|
(set condbit
|
(set condbit
|
(cond BI
|
(cond BI
|
((eq (and src2 (const #xff)) (const 0)) (const BI 1))
|
((eq (and src2 (const #xff)) (const 0)) (const BI 1))
|
((eq (and src2 (const #xff00)) (const 0)) (const BI 1))
|
((eq (and src2 (const #xff00)) (const 0)) (const BI 1))
|
((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
|
((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
|
((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
|
((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
|
(else (const BI 0))))
|
(else (const BI 0))))
|
((m32rx (unit u-cmp))
|
((m32rx (unit u-cmp))
|
(m32r2 (unit u-cmp)))
|
(m32r2 (unit u-cmp)))
|
)
|
)
|
|
|
; Add accumulators
|
; Add accumulators
|
(dni sadd "sadd"
|
(dni sadd "sadd"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
|
"sadd"
|
"sadd"
|
(+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
|
(+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
|
(set (reg h-accums 0)
|
(set (reg h-accums 0)
|
(add (sra (reg h-accums 1) (const 16))
|
(add (sra (reg h-accums 1) (const 16))
|
(reg h-accums 0)))
|
(reg h-accums 0)))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
; Multiply and add into accumulator 1
|
; Multiply and add into accumulator 1
|
(dni macwu1 "macwu1"
|
(dni macwu1 "macwu1"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"macwu1 $src1,$src2"
|
"macwu1 $src1,$src2"
|
(+ OP1_5 src1 OP2_11 src2)
|
(+ OP1_5 src1 OP2_11 src2)
|
(set (reg h-accums 1)
|
(set (reg h-accums 1)
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(add DI
|
(add DI
|
(reg h-accums 1)
|
(reg h-accums 1)
|
(mul DI
|
(mul DI
|
(ext DI src1)
|
(ext DI src1)
|
(ext DI (and src2 (const #xffff)))))
|
(ext DI (and src2 (const #xffff)))))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
; Multiply and subtract from accumulator 0
|
; Multiply and subtract from accumulator 0
|
(dni msblo "msblo"
|
(dni msblo "msblo"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"msblo $src1,$src2"
|
"msblo $src1,$src2"
|
(+ OP1_5 src1 OP2_13 src2)
|
(+ OP1_5 src1 OP2_13 src2)
|
(set accum
|
(set accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(sub accum
|
(sub accum
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(mul DI
|
(mul DI
|
(ext DI (trunc HI src1))
|
(ext DI (trunc HI src1))
|
(ext DI (trunc HI src2)))
|
(ext DI (trunc HI src2)))
|
(const 32))
|
(const 32))
|
(const 16)))
|
(const 16)))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
; Multiply into accumulator 1
|
; Multiply into accumulator 1
|
(dni mulwu1 "mulwu1"
|
(dni mulwu1 "mulwu1"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"mulwu1 $src1,$src2"
|
"mulwu1 $src1,$src2"
|
(+ OP1_5 src1 OP2_10 src2)
|
(+ OP1_5 src1 OP2_10 src2)
|
(set (reg h-accums 1)
|
(set (reg h-accums 1)
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(mul DI
|
(mul DI
|
(ext DI src1)
|
(ext DI src1)
|
(ext DI (and src2 (const #xffff))))
|
(ext DI (and src2 (const #xffff))))
|
(const 16))
|
(const 16))
|
(const 16)))
|
(const 16)))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
; Multiply and add into accumulator 1
|
; Multiply and add into accumulator 1
|
(dni maclh1 "maclh1"
|
(dni maclh1 "maclh1"
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
|
"maclh1 $src1,$src2"
|
"maclh1 $src1,$src2"
|
(+ OP1_5 src1 OP2_12 src2)
|
(+ OP1_5 src1 OP2_12 src2)
|
(set (reg h-accums 1)
|
(set (reg h-accums 1)
|
(sra DI
|
(sra DI
|
(sll DI
|
(sll DI
|
(add DI
|
(add DI
|
(reg h-accums 1)
|
(reg h-accums 1)
|
(sll DI
|
(sll DI
|
(ext DI
|
(ext DI
|
(mul SI
|
(mul SI
|
(ext SI (trunc HI src1))
|
(ext SI (trunc HI src1))
|
(sra SI src2 (const SI 16))))
|
(sra SI src2 (const SI 16))))
|
(const 16)))
|
(const 16)))
|
(const 8))
|
(const 8))
|
(const 8)))
|
(const 8)))
|
((m32rx (unit u-mac))
|
((m32rx (unit u-mac))
|
(m32r2 (unit u-mac)))
|
(m32r2 (unit u-mac)))
|
)
|
)
|
|
|
; skip instruction if C
|
; skip instruction if C
|
(dni sc "sc"
|
(dni sc "sc"
|
((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
|
((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
|
"sc"
|
"sc"
|
(+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
|
(+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
|
(skip (zext INT condbit))
|
(skip (zext INT condbit))
|
()
|
()
|
)
|
)
|
|
|
; skip instruction if not C
|
; skip instruction if not C
|
(dni snc "snc"
|
(dni snc "snc"
|
((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
|
((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
|
"snc"
|
"snc"
|
(+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
|
(+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
|
(skip (zext INT (not condbit)))
|
(skip (zext INT (not condbit)))
|
()
|
()
|
)
|
)
|
|
|
; PSW &= ~((unsigned char) uimm8 | 0x000ff00)
|
; PSW &= ~((unsigned char) uimm8 | 0x000ff00)
|
(dni clrpsw "clrpsw"
|
(dni clrpsw "clrpsw"
|
((PIPE O) SPECIAL_M32R)
|
((PIPE O) SPECIAL_M32R)
|
"clrpsw $uimm8"
|
"clrpsw $uimm8"
|
(+ OP1_7 (f-r1 2) uimm8)
|
(+ OP1_7 (f-r1 2) uimm8)
|
(set USI (reg h-cr 0)
|
(set USI (reg h-cr 0)
|
(and USI (reg h-cr 0)
|
(and USI (reg h-cr 0)
|
(or USI (inv BI uimm8) (const #xff00))))
|
(or USI (inv BI uimm8) (const #xff00))))
|
()
|
()
|
)
|
)
|
|
|
; PSW |= (unsigned char) uimm8
|
; PSW |= (unsigned char) uimm8
|
(dni setpsw "setpsw"
|
(dni setpsw "setpsw"
|
((PIPE O) SPECIAL_M32R)
|
((PIPE O) SPECIAL_M32R)
|
"setpsw $uimm8"
|
"setpsw $uimm8"
|
(+ OP1_7 (f-r1 1) uimm8)
|
(+ OP1_7 (f-r1 1) uimm8)
|
(set USI (reg h-cr 0) uimm8)
|
(set USI (reg h-cr 0) uimm8)
|
()
|
()
|
)
|
)
|
|
|
; bset
|
; bset
|
(dni bset "bset"
|
(dni bset "bset"
|
(SPECIAL_M32R)
|
(SPECIAL_M32R)
|
"bset $uimm3,@($slo16,$sr)"
|
"bset $uimm3,@($slo16,$sr)"
|
(+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
|
(+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
|
(set QI (mem QI (add sr slo16))
|
(set QI (mem QI (add sr slo16))
|
(or QI (mem QI (add sr slo16))
|
(or QI (mem QI (add sr slo16))
|
(sll USI (const 1) (sub (const 7) uimm3))))
|
(sll USI (const 1) (sub (const 7) uimm3))))
|
()
|
()
|
)
|
)
|
|
|
; bclr
|
; bclr
|
(dni bclr "bclr"
|
(dni bclr "bclr"
|
(SPECIAL_M32R)
|
(SPECIAL_M32R)
|
"bclr $uimm3,@($slo16,$sr)"
|
"bclr $uimm3,@($slo16,$sr)"
|
(+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16)
|
(+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16)
|
(set QI (mem QI (add sr slo16))
|
(set QI (mem QI (add sr slo16))
|
(and QI (mem QI (add sr slo16))
|
(and QI (mem QI (add sr slo16))
|
(inv QI (sll USI (const 1) (sub (const 7) uimm3)))))
|
(inv QI (sll USI (const 1) (sub (const 7) uimm3)))))
|
()
|
()
|
)
|
)
|
|
|
; btst
|
; btst
|
(dni btst "btst"
|
(dni btst "btst"
|
(SPECIAL_M32R (PIPE O))
|
(SPECIAL_M32R (PIPE O))
|
"btst $uimm3,$sr"
|
"btst $uimm3,$sr"
|
(+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
|
(+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
|
(set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1)))
|
(set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1)))
|
()
|
()
|
)
|
)
|
|
|
|
|
