/* tc-d30v.c -- Assembler code for the Mitsubishi D30V
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/* tc-d30v.c -- Assembler code for the Mitsubishi D30V
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Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008
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Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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GAS is distributed in the hope that it will be useful,
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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Boston, MA 02110-1301, USA. */
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#include "as.h"
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#include "as.h"
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#include "safe-ctype.h"
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#include "safe-ctype.h"
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#include "subsegs.h"
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#include "subsegs.h"
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#include "opcode/d30v.h"
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#include "opcode/d30v.h"
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const char comment_chars[] = ";";
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const char comment_chars[] = ";";
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const char line_comment_chars[] = "#";
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = "";
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const char line_separator_chars[] = "";
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const char *md_shortopts = "OnNcC";
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const char *md_shortopts = "OnNcC";
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const char EXP_CHARS[] = "eE";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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const char FLT_CHARS[] = "dD";
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#if HAVE_LIMITS_H
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#if HAVE_LIMITS_H
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#include <limits.h>
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#include <limits.h>
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#endif
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#endif
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#ifndef CHAR_BIT
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#ifndef CHAR_BIT
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#define CHAR_BIT 8
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#define CHAR_BIT 8
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#endif
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#endif
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#define NOP_MULTIPLY 1
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#define NOP_MULTIPLY 1
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#define NOP_ALL 2
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#define NOP_ALL 2
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static int warn_nops = 0;
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static int warn_nops = 0;
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static int Optimizing = 0;
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static int Optimizing = 0;
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static int warn_register_name_conflicts = 1;
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static int warn_register_name_conflicts = 1;
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#define FORCE_SHORT 1
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#define FORCE_SHORT 1
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#define FORCE_LONG 2
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#define FORCE_LONG 2
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/* EXEC types. */
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/* EXEC types. */
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typedef enum _exec_type
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typedef enum _exec_type
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{
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{
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EXEC_UNKNOWN, /* No order specified. */
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EXEC_UNKNOWN, /* No order specified. */
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EXEC_PARALLEL, /* Done in parallel (FM=00). */
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EXEC_PARALLEL, /* Done in parallel (FM=00). */
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EXEC_SEQ, /* Sequential (FM=01). */
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EXEC_SEQ, /* Sequential (FM=01). */
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EXEC_REVSEQ /* Reverse sequential (FM=10). */
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EXEC_REVSEQ /* Reverse sequential (FM=10). */
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} exec_type_enum;
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} exec_type_enum;
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/* Fixups. */
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/* Fixups. */
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#define MAX_INSN_FIXUPS 5
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#define MAX_INSN_FIXUPS 5
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struct d30v_fixup
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struct d30v_fixup
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{
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{
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expressionS exp;
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expressionS exp;
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int operand;
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int operand;
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int pcrel;
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int pcrel;
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int size;
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int size;
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bfd_reloc_code_real_type reloc;
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bfd_reloc_code_real_type reloc;
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};
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};
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typedef struct _fixups
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typedef struct _fixups
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{
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{
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int fc;
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int fc;
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struct d30v_fixup fix[MAX_INSN_FIXUPS];
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struct d30v_fixup fix[MAX_INSN_FIXUPS];
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struct _fixups *next;
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struct _fixups *next;
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} Fixups;
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} Fixups;
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static Fixups FixUps[2];
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static Fixups FixUps[2];
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static Fixups *fixups;
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static Fixups *fixups;
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/* Whether current and previous instruction are word multiply insns. */
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/* Whether current and previous instruction are word multiply insns. */
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static int cur_mul32_p = 0;
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static int cur_mul32_p = 0;
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static int prev_mul32_p = 0;
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static int prev_mul32_p = 0;
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/* The flag_explicitly_parallel is true iff the instruction being assembled
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/* The flag_explicitly_parallel is true iff the instruction being assembled
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has been explicitly written as a parallel short-instruction pair by the
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has been explicitly written as a parallel short-instruction pair by the
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human programmer. It is used in parallel_ok () to distinguish between
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human programmer. It is used in parallel_ok () to distinguish between
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those dangerous parallelizations attempted by the human, which are to be
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those dangerous parallelizations attempted by the human, which are to be
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allowed, and those attempted by the assembler, which are not. It is set
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allowed, and those attempted by the assembler, which are not. It is set
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from md_assemble (). */
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from md_assemble (). */
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static int flag_explicitly_parallel = 0;
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static int flag_explicitly_parallel = 0;
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static int flag_xp_state = 0;
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static int flag_xp_state = 0;
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/* Whether current and previous left sub-instruction disables
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/* Whether current and previous left sub-instruction disables
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execution of right sub-instruction. */
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execution of right sub-instruction. */
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static int cur_left_kills_right_p = 0;
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static int cur_left_kills_right_p = 0;
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static int prev_left_kills_right_p = 0;
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static int prev_left_kills_right_p = 0;
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/* The known current alignment of the current section. */
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/* The known current alignment of the current section. */
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static int d30v_current_align;
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static int d30v_current_align;
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static segT d30v_current_align_seg;
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static segT d30v_current_align_seg;
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/* The last seen label in the current section. This is used to auto-align
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/* The last seen label in the current section. This is used to auto-align
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labels preceding instructions. */
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labels preceding instructions. */
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static symbolS *d30v_last_label;
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static symbolS *d30v_last_label;
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/* Two nops. */
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/* Two nops. */
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#define NOP_LEFT ((long long) NOP << 32)
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#define NOP_LEFT ((long long) NOP << 32)
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#define NOP_RIGHT ((long long) NOP)
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#define NOP_RIGHT ((long long) NOP)
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#define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
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#define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
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struct option md_longopts[] =
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struct option md_longopts[] =
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{
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{
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{NULL, no_argument, NULL, 0}
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{NULL, no_argument, NULL, 0}
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};
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};
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size_t md_longopts_size = sizeof (md_longopts);
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size_t md_longopts_size = sizeof (md_longopts);
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/* Opcode hash table. */
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/* Opcode hash table. */
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static struct hash_control *d30v_hash;
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static struct hash_control *d30v_hash;
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/* Do a binary search of the pre_defined_registers array to see if
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/* Do a binary search of the pre_defined_registers array to see if
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NAME is a valid regiter name. Return the register number from the
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NAME is a valid regiter name. Return the register number from the
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array on success, or -1 on failure. */
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array on success, or -1 on failure. */
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static int
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static int
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reg_name_search (char *name)
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reg_name_search (char *name)
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{
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{
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int middle, low, high;
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int middle, low, high;
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int cmp;
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int cmp;
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low = 0;
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low = 0;
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high = reg_name_cnt () - 1;
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high = reg_name_cnt () - 1;
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do
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do
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{
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{
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middle = (low + high) / 2;
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middle = (low + high) / 2;
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cmp = strcasecmp (name, pre_defined_registers[middle].name);
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cmp = strcasecmp (name, pre_defined_registers[middle].name);
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if (cmp < 0)
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if (cmp < 0)
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high = middle - 1;
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high = middle - 1;
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else if (cmp > 0)
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else if (cmp > 0)
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low = middle + 1;
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low = middle + 1;
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else
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else
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{
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{
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if (symbol_find (name) != NULL)
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if (symbol_find (name) != NULL)
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{
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{
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if (warn_register_name_conflicts)
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if (warn_register_name_conflicts)
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as_warn (_("Register name %s conflicts with symbol of the same name"),
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as_warn (_("Register name %s conflicts with symbol of the same name"),
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name);
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name);
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}
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}
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return pre_defined_registers[middle].value;
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return pre_defined_registers[middle].value;
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}
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}
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}
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}
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while (low <= high);
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while (low <= high);
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return -1;
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return -1;
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}
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}
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/* Check the string at input_line_pointer to see if it is a valid
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/* Check the string at input_line_pointer to see if it is a valid
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register name. */
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register name. */
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static int
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static int
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register_name (expressionS *expressionP)
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register_name (expressionS *expressionP)
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{
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{
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int reg_number;
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int reg_number;
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char c, *p = input_line_pointer;
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char c, *p = input_line_pointer;
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while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
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while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
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p++;
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p++;
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c = *p;
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c = *p;
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if (c)
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if (c)
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*p++ = 0;
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*p++ = 0;
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/* Look to see if it's in the register table. */
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/* Look to see if it's in the register table. */
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reg_number = reg_name_search (input_line_pointer);
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reg_number = reg_name_search (input_line_pointer);
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if (reg_number >= 0)
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if (reg_number >= 0)
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{
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{
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expressionP->X_op = O_register;
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expressionP->X_op = O_register;
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/* Temporarily store a pointer to the string here. */
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/* Temporarily store a pointer to the string here. */
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expressionP->X_op_symbol = (symbolS *) input_line_pointer;
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expressionP->X_op_symbol = (symbolS *) input_line_pointer;
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expressionP->X_add_number = reg_number;
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expressionP->X_add_number = reg_number;
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input_line_pointer = p;
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input_line_pointer = p;
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return 1;
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return 1;
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}
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}
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if (c)
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if (c)
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*(p - 1) = c;
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*(p - 1) = c;
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return 0;
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return 0;
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}
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}
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static int
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static int
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check_range (unsigned long num, int bits, int flags)
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check_range (unsigned long num, int bits, int flags)
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{
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{
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long min, max;
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long min, max;
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/* Don't bother checking 32-bit values. */
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/* Don't bother checking 32-bit values. */
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if (bits == 32)
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if (bits == 32)
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{
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{
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if (sizeof (unsigned long) * CHAR_BIT == 32)
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if (sizeof (unsigned long) * CHAR_BIT == 32)
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return 0;
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return 0;
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/* We don't record signed or unsigned for 32-bit quantities.
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/* We don't record signed or unsigned for 32-bit quantities.
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Allow either. */
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Allow either. */
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min = -((unsigned long) 1 << (bits - 1));
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min = -((unsigned long) 1 << (bits - 1));
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max = ((unsigned long) 1 << bits) - 1;
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max = ((unsigned long) 1 << bits) - 1;
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return (long) num < min || (long) num > max;
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return (long) num < min || (long) num > max;
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}
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}
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if (flags & OPERAND_SHIFT)
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if (flags & OPERAND_SHIFT)
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{
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{
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/* We know that all shifts are right by three bits. */
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/* We know that all shifts are right by three bits. */
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num >>= 3;
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num >>= 3;
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if (flags & OPERAND_SIGNED)
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if (flags & OPERAND_SIGNED)
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{
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{
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unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1;
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unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1;
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num = (num ^ sign_bit) - sign_bit;
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num = (num ^ sign_bit) - sign_bit;
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}
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}
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}
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}
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if (flags & OPERAND_SIGNED)
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if (flags & OPERAND_SIGNED)
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{
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{
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max = ((unsigned long) 1 << (bits - 1)) - 1;
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max = ((unsigned long) 1 << (bits - 1)) - 1;
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min = - ((unsigned long) 1 << (bits - 1));
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min = - ((unsigned long) 1 << (bits - 1));
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return (long) num > max || (long) num < min;
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return (long) num > max || (long) num < min;
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}
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}
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else
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else
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{
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{
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max = ((unsigned long) 1 << bits) - 1;
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max = ((unsigned long) 1 << bits) - 1;
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return num > (unsigned long) max;
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return num > (unsigned long) max;
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}
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}
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}
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}
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void
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void
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md_show_usage (FILE *stream)
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md_show_usage (FILE *stream)
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{
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{
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fprintf (stream, _("\nD30V options:\n\
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fprintf (stream, _("\nD30V options:\n\
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-O Make adjacent short instructions parallel if possible.\n\
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-O Make adjacent short instructions parallel if possible.\n\
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-n Warn about all NOPs inserted by the assembler.\n\
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-n Warn about all NOPs inserted by the assembler.\n\
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-N Warn about NOPs inserted after word multiplies.\n\
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-N Warn about NOPs inserted after word multiplies.\n\
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-c Warn about symbols whoes names match register names.\n\
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-c Warn about symbols whoes names match register names.\n\
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-C Opposite of -C. -c is the default.\n"));
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-C Opposite of -C. -c is the default.\n"));
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}
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}
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int
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int
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md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
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md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
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{
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{
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switch (c)
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switch (c)
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{
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{
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/* Optimize. Will attempt to parallelize operations. */
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/* Optimize. Will attempt to parallelize operations. */
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case 'O':
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case 'O':
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Optimizing = 1;
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Optimizing = 1;
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break;
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break;
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|
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/* Warn about all NOPS that the assembler inserts. */
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/* Warn about all NOPS that the assembler inserts. */
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case 'n':
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case 'n':
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warn_nops = NOP_ALL;
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warn_nops = NOP_ALL;
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break;
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break;
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/* Warn about the NOPS that the assembler inserts because of the
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/* Warn about the NOPS that the assembler inserts because of the
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multiply hazard. */
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multiply hazard. */
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case 'N':
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case 'N':
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warn_nops = NOP_MULTIPLY;
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warn_nops = NOP_MULTIPLY;
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break;
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break;
|
|
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case 'c':
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case 'c':
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warn_register_name_conflicts = 1;
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warn_register_name_conflicts = 1;
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break;
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break;
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|
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case 'C':
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case 'C':
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warn_register_name_conflicts = 0;
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warn_register_name_conflicts = 0;
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break;
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break;
|
|
|
default:
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default:
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return 0;
|
return 0;
|
}
|
}
|
return 1;
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return 1;
|
}
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}
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|
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symbolS *
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symbolS *
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md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
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md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
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{
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{
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return 0;
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return 0;
|
}
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}
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char *
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char *
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md_atof (int type, char *litP, int *sizeP)
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md_atof (int type, char *litP, int *sizeP)
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{
|
{
|
return ieee_md_atof (type, litP, sizeP, TRUE);
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return ieee_md_atof (type, litP, sizeP, TRUE);
|
}
|
}
|
|
|
void
|
void
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md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
|
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
|
asection *sec ATTRIBUTE_UNUSED,
|
asection *sec ATTRIBUTE_UNUSED,
|
fragS *fragP ATTRIBUTE_UNUSED)
|
fragS *fragP ATTRIBUTE_UNUSED)
|
{
|
{
|
abort ();
|
abort ();
|
}
|
}
|
|
|
valueT
|
valueT
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md_section_align (asection *seg, valueT addr)
|
md_section_align (asection *seg, valueT addr)
|
{
|
{
|
int align = bfd_get_section_alignment (stdoutput, seg);
|
int align = bfd_get_section_alignment (stdoutput, seg);
|
return ((addr + (1 << align) - 1) & (-1 << align));
|
return ((addr + (1 << align) - 1) & (-1 << align));
|
}
|
}
|
|
|
void
|
void
|
md_begin (void)
|
md_begin (void)
|
{
|
{
|
struct d30v_opcode *opcode;
|
struct d30v_opcode *opcode;
|
d30v_hash = hash_new ();
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d30v_hash = hash_new ();
|
|
|
/* Insert opcode names into a hash table. */
|
/* Insert opcode names into a hash table. */
|
for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++)
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for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++)
|
hash_insert (d30v_hash, opcode->name, (char *) opcode);
|
hash_insert (d30v_hash, opcode->name, (char *) opcode);
|
|
|
fixups = &FixUps[0];
|
fixups = &FixUps[0];
|
FixUps[0].next = &FixUps[1];
|
FixUps[0].next = &FixUps[1];
|
FixUps[1].next = &FixUps[0];
|
FixUps[1].next = &FixUps[0];
|
|
|
d30v_current_align_seg = now_seg;
|
d30v_current_align_seg = now_seg;
|
}
|
}
|
|
|
/* Remove the postincrement or postdecrement operator ( '+' or '-' )
|
/* Remove the postincrement or postdecrement operator ( '+' or '-' )
|
from an expression. */
|
from an expression. */
|
|
|
static int
|
static int
|
postfix (char *p)
|
postfix (char *p)
|
{
|
{
|
while (*p != '-' && *p != '+')
|
while (*p != '-' && *p != '+')
|
{
|
{
|
if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',')
|
if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',')
|
break;
|
break;
|
p++;
|
p++;
|
}
|
}
|
|
|
if (*p == '-')
|
if (*p == '-')
|
{
|
{
|
*p = ' ';
|
*p = ' ';
|
return -1;
|
return -1;
|
}
|
}
|
|
|
if (*p == '+')
|
if (*p == '+')
|
{
|
{
|
*p = ' ';
|
*p = ' ';
|
return 1;
|
return 1;
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
static bfd_reloc_code_real_type
|
static bfd_reloc_code_real_type
|
get_reloc (const struct d30v_operand *op, int rel_flag)
|
get_reloc (const struct d30v_operand *op, int rel_flag)
|
{
|
{
|
switch (op->bits)
|
switch (op->bits)
|
{
|
{
|
case 6:
|
case 6:
|
if (op->flags & OPERAND_SHIFT)
|
if (op->flags & OPERAND_SHIFT)
|
return BFD_RELOC_D30V_9_PCREL;
|
return BFD_RELOC_D30V_9_PCREL;
|
else
|
else
|
return BFD_RELOC_D30V_6;
|
return BFD_RELOC_D30V_6;
|
break;
|
break;
|
case 12:
|
case 12:
|
if (!(op->flags & OPERAND_SHIFT))
|
if (!(op->flags & OPERAND_SHIFT))
|
as_warn (_("unexpected 12-bit reloc type"));
|
as_warn (_("unexpected 12-bit reloc type"));
|
if (rel_flag == RELOC_PCREL)
|
if (rel_flag == RELOC_PCREL)
|
return BFD_RELOC_D30V_15_PCREL;
|
return BFD_RELOC_D30V_15_PCREL;
|
else
|
else
|
return BFD_RELOC_D30V_15;
|
return BFD_RELOC_D30V_15;
|
case 18:
|
case 18:
|
if (!(op->flags & OPERAND_SHIFT))
|
if (!(op->flags & OPERAND_SHIFT))
|
as_warn (_("unexpected 18-bit reloc type"));
|
as_warn (_("unexpected 18-bit reloc type"));
|
if (rel_flag == RELOC_PCREL)
|
if (rel_flag == RELOC_PCREL)
|
return BFD_RELOC_D30V_21_PCREL;
|
return BFD_RELOC_D30V_21_PCREL;
|
else
|
else
|
return BFD_RELOC_D30V_21;
|
return BFD_RELOC_D30V_21;
|
case 32:
|
case 32:
|
if (rel_flag == RELOC_PCREL)
|
if (rel_flag == RELOC_PCREL)
|
return BFD_RELOC_D30V_32_PCREL;
|
return BFD_RELOC_D30V_32_PCREL;
|
else
|
else
|
return BFD_RELOC_D30V_32;
|
return BFD_RELOC_D30V_32;
|
default:
|
default:
|
return 0;
|
return 0;
|
}
|
}
|
}
|
}
|
|
|
/* Parse a string of operands and return an array of expressions. */
|
/* Parse a string of operands and return an array of expressions. */
|
|
|
static int
|
static int
|
get_operands (expressionS exp[], int cmp_hack)
|
get_operands (expressionS exp[], int cmp_hack)
|
{
|
{
|
char *p = input_line_pointer;
|
char *p = input_line_pointer;
|
int numops = 0;
|
int numops = 0;
|
int post = 0;
|
int post = 0;
|
|
|
if (cmp_hack)
|
if (cmp_hack)
|
{
|
{
|
exp[numops].X_op = O_absent;
|
exp[numops].X_op = O_absent;
|
exp[numops++].X_add_number = cmp_hack - 1;
|
exp[numops++].X_add_number = cmp_hack - 1;
|
}
|
}
|
|
|
while (*p)
|
while (*p)
|
{
|
{
|
while (*p == ' ' || *p == '\t' || *p == ',')
|
while (*p == ' ' || *p == '\t' || *p == ',')
|
p++;
|
p++;
|
|
|
if (*p == 0 || *p == '\n' || *p == '\r')
|
if (*p == 0 || *p == '\n' || *p == '\r')
|
break;
|
break;
|
|
|
if (*p == '@')
|
if (*p == '@')
|
{
|
{
|
p++;
|
p++;
|
exp[numops].X_op = O_absent;
|
exp[numops].X_op = O_absent;
|
if (*p == '(')
|
if (*p == '(')
|
{
|
{
|
p++;
|
p++;
|
exp[numops].X_add_number = OPERAND_ATPAR;
|
exp[numops].X_add_number = OPERAND_ATPAR;
|
post = postfix (p);
|
post = postfix (p);
|
}
|
}
|
else if (*p == '-')
|
else if (*p == '-')
|
{
|
{
|
p++;
|
p++;
|
exp[numops].X_add_number = OPERAND_ATMINUS;
|
exp[numops].X_add_number = OPERAND_ATMINUS;
|
}
|
}
|
else
|
else
|
{
|
{
|
exp[numops].X_add_number = OPERAND_ATSIGN;
|
exp[numops].X_add_number = OPERAND_ATSIGN;
|
post = postfix (p);
|
post = postfix (p);
|
}
|
}
|
numops++;
|
numops++;
|
continue;
|
continue;
|
}
|
}
|
|
|
if (*p == ')')
|
if (*p == ')')
|
{
|
{
|
/* Just skip the trailing paren. */
|
/* Just skip the trailing paren. */
|
p++;
|
p++;
|
continue;
|
continue;
|
}
|
}
|
|
|
input_line_pointer = p;
|
input_line_pointer = p;
|
|
|
/* Check to see if it might be a register name. */
|
/* Check to see if it might be a register name. */
|
if (!register_name (&exp[numops]))
|
if (!register_name (&exp[numops]))
|
{
|
{
|
/* Parse as an expression. */
|
/* Parse as an expression. */
|
expression (&exp[numops]);
|
expression (&exp[numops]);
|
}
|
}
|
|
|
if (exp[numops].X_op == O_illegal)
|
if (exp[numops].X_op == O_illegal)
|
as_bad (_("illegal operand"));
|
as_bad (_("illegal operand"));
|
else if (exp[numops].X_op == O_absent)
|
else if (exp[numops].X_op == O_absent)
|
as_bad (_("missing operand"));
|
as_bad (_("missing operand"));
|
|
|
numops++;
|
numops++;
|
p = input_line_pointer;
|
p = input_line_pointer;
|
|
|
switch (post)
|
switch (post)
|
{
|
{
|
case -1:
|
case -1:
|
/* Postdecrement mode. */
|
/* Postdecrement mode. */
|
exp[numops].X_op = O_absent;
|
exp[numops].X_op = O_absent;
|
exp[numops++].X_add_number = OPERAND_MINUS;
|
exp[numops++].X_add_number = OPERAND_MINUS;
|
break;
|
break;
|
case 1:
|
case 1:
|
/* Postincrement mode. */
|
/* Postincrement mode. */
|
exp[numops].X_op = O_absent;
|
exp[numops].X_op = O_absent;
|
exp[numops++].X_add_number = OPERAND_PLUS;
|
exp[numops++].X_add_number = OPERAND_PLUS;
|
break;
|
break;
|
}
|
}
|
post = 0;
|
post = 0;
|
}
|
}
|
|
|
exp[numops].X_op = 0;
|
exp[numops].X_op = 0;
|
|
|
return numops;
|
return numops;
|
}
|
}
|
|
|
/* Generate the instruction.
|
/* Generate the instruction.
|
It does everything but write the FM bits. */
|
It does everything but write the FM bits. */
|
|
|
static long long
|
static long long
|
build_insn (struct d30v_insn *opcode, expressionS *opers)
|
build_insn (struct d30v_insn *opcode, expressionS *opers)
|
{
|
{
|
int i, length, bits, shift, flags;
|
int i, length, bits, shift, flags;
|
unsigned long number, id = 0;
|
unsigned long number, id = 0;
|
long long insn;
|
long long insn;
|
struct d30v_opcode *op = opcode->op;
|
struct d30v_opcode *op = opcode->op;
|
struct d30v_format *form = opcode->form;
|
struct d30v_format *form = opcode->form;
|
|
|
insn =
|
insn =
|
opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18;
|
opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18;
|
|
|
for (i = 0; form->operands[i]; i++)
|
for (i = 0; form->operands[i]; i++)
|
{
|
{
|
flags = d30v_operand_table[form->operands[i]].flags;
|
flags = d30v_operand_table[form->operands[i]].flags;
|
|
|
/* Must be a register or number. */
|
/* Must be a register or number. */
|
if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM)
|
if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM)
|
&& !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL))
|
&& !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL))
|
continue;
|
continue;
|
|
|
bits = d30v_operand_table[form->operands[i]].bits;
|
bits = d30v_operand_table[form->operands[i]].bits;
|
if (flags & OPERAND_SHIFT)
|
if (flags & OPERAND_SHIFT)
|
bits += 3;
|
bits += 3;
|
|
|
length = d30v_operand_table[form->operands[i]].length;
|
length = d30v_operand_table[form->operands[i]].length;
|
shift = 12 - d30v_operand_table[form->operands[i]].position;
|
shift = 12 - d30v_operand_table[form->operands[i]].position;
|
if (opers[i].X_op != O_symbol)
|
if (opers[i].X_op != O_symbol)
|
number = opers[i].X_add_number;
|
number = opers[i].X_add_number;
|
else
|
else
|
number = 0;
|
number = 0;
|
if (flags & OPERAND_REG)
|
if (flags & OPERAND_REG)
|
{
|
{
|
/* Check for mvfsys or mvtsys control registers. */
|
/* Check for mvfsys or mvtsys control registers. */
|
if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG)
|
if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG)
|
{
|
{
|
/* PSWL or PSWH. */
|
/* PSWL or PSWH. */
|
id = (number & 0x7f) - MAX_CONTROL_REG;
|
id = (number & 0x7f) - MAX_CONTROL_REG;
|
number = 0;
|
number = 0;
|
}
|
}
|
else if (number & OPERAND_FLAG)
|
else if (number & OPERAND_FLAG)
|
/* NUMBER is a flag register. */
|
/* NUMBER is a flag register. */
|
id = 3;
|
id = 3;
|
|
|
number &= 0x7F;
|
number &= 0x7F;
|
}
|
}
|
else if (flags & OPERAND_SPECIAL)
|
else if (flags & OPERAND_SPECIAL)
|
number = id;
|
number = id;
|
|
|
if (opers[i].X_op != O_register && opers[i].X_op != O_constant
|
if (opers[i].X_op != O_register && opers[i].X_op != O_constant
|
&& !(flags & OPERAND_NAME))
|
&& !(flags & OPERAND_NAME))
|
{
|
{
|
/* Now create a fixup. */
|
/* Now create a fixup. */
|
if (fixups->fc >= MAX_INSN_FIXUPS)
|
if (fixups->fc >= MAX_INSN_FIXUPS)
|
as_fatal (_("too many fixups"));
|
as_fatal (_("too many fixups"));
|
|
|
fixups->fix[fixups->fc].reloc =
|
fixups->fix[fixups->fc].reloc =
|
get_reloc (d30v_operand_table + form->operands[i], op->reloc_flag);
|
get_reloc (d30v_operand_table + form->operands[i], op->reloc_flag);
|
fixups->fix[fixups->fc].size = 4;
|
fixups->fix[fixups->fc].size = 4;
|
fixups->fix[fixups->fc].exp = opers[i];
|
fixups->fix[fixups->fc].exp = opers[i];
|
fixups->fix[fixups->fc].operand = form->operands[i];
|
fixups->fix[fixups->fc].operand = form->operands[i];
|
if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL)
|
if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL)
|
fixups->fix[fixups->fc].pcrel = RELOC_PCREL;
|
fixups->fix[fixups->fc].pcrel = RELOC_PCREL;
|
else
|
else
|
fixups->fix[fixups->fc].pcrel = op->reloc_flag;
|
fixups->fix[fixups->fc].pcrel = op->reloc_flag;
|
(fixups->fc)++;
|
(fixups->fc)++;
|
}
|
}
|
|
|
/* Truncate to the proper number of bits. */
|
/* Truncate to the proper number of bits. */
|
if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
|
if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
|
as_bad (_("operand out of range: %ld"), number);
|
as_bad (_("operand out of range: %ld"), number);
|
if (bits < 31)
|
if (bits < 31)
|
number &= 0x7FFFFFFF >> (31 - bits);
|
number &= 0x7FFFFFFF >> (31 - bits);
|
if (flags & OPERAND_SHIFT)
|
if (flags & OPERAND_SHIFT)
|
number >>= 3;
|
number >>= 3;
|
if (bits == 32)
|
if (bits == 32)
|
{
|
{
|
/* It's a LONG instruction. */
|
/* It's a LONG instruction. */
|
insn |= ((number & 0xffffffff) >> 26); /* Top 6 bits. */
|
insn |= ((number & 0xffffffff) >> 26); /* Top 6 bits. */
|
insn <<= 32; /* Shift the first word over. */
|
insn <<= 32; /* Shift the first word over. */
|
insn |= ((number & 0x03FC0000) << 2); /* Next 8 bits. */
|
insn |= ((number & 0x03FC0000) << 2); /* Next 8 bits. */
|
insn |= number & 0x0003FFFF; /* Bottom 18 bits. */
|
insn |= number & 0x0003FFFF; /* Bottom 18 bits. */
|
}
|
}
|
else
|
else
|
insn |= number << shift;
|
insn |= number << shift;
|
}
|
}
|
|
|
return insn;
|
return insn;
|
}
|
}
|
|
|
static void
|
static void
|
d30v_number_to_chars (char *buf, /* Return 'nbytes' of chars here. */
|
d30v_number_to_chars (char *buf, /* Return 'nbytes' of chars here. */
|
long long value, /* The value of the bits. */
|
long long value, /* The value of the bits. */
|
int n) /* Number of bytes in the output. */
|
int n) /* Number of bytes in the output. */
|
{
|
{
|
while (n--)
|
while (n--)
|
{
|
{
|
buf[n] = value & 0xff;
|
buf[n] = value & 0xff;
|
value >>= 8;
|
value >>= 8;
|
}
|
}
|
}
|
}
|
|
|
/* Write out a long form instruction. */
|
/* Write out a long form instruction. */
|
|
|
static void
|
static void
|
write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED,
|
write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED,
|
long long insn,
|
long long insn,
|
Fixups *fx)
|
Fixups *fx)
|
{
|
{
|
int i, where;
|
int i, where;
|
char *f = frag_more (8);
|
char *f = frag_more (8);
|
|
|
insn |= FM11;
|
insn |= FM11;
|
d30v_number_to_chars (f, insn, 8);
|
d30v_number_to_chars (f, insn, 8);
|
|
|
for (i = 0; i < fx->fc; i++)
|
for (i = 0; i < fx->fc; i++)
|
{
|
{
|
if (fx->fix[i].reloc)
|
if (fx->fix[i].reloc)
|
{
|
{
|
where = f - frag_now->fr_literal;
|
where = f - frag_now->fr_literal;
|
fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp),
|
fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp),
|
fx->fix[i].pcrel, fx->fix[i].reloc);
|
fx->fix[i].pcrel, fx->fix[i].reloc);
|
}
|
}
|
}
|
}
|
|
|
fx->fc = 0;
|
fx->fc = 0;
|
}
|
}
|
|
|
/* Write out a short form instruction by itself. */
|
/* Write out a short form instruction by itself. */
|
|
|
static void
|
static void
|
write_1_short (struct d30v_insn *opcode,
|
write_1_short (struct d30v_insn *opcode,
|
long long insn,
|
long long insn,
|
Fixups *fx,
|
Fixups *fx,
|
int use_sequential)
|
int use_sequential)
|
{
|
{
|
char *f = frag_more (8);
|
char *f = frag_more (8);
|
int i, where;
|
int i, where;
|
|
|
if (warn_nops == NOP_ALL)
|
if (warn_nops == NOP_ALL)
|
as_warn (_("%s NOP inserted"), use_sequential ?
|
as_warn (_("%s NOP inserted"), use_sequential ?
|
_("sequential") : _("parallel"));
|
_("sequential") : _("parallel"));
|
|
|
/* The other container needs to be NOP. */
|
/* The other container needs to be NOP. */
|
if (use_sequential)
|
if (use_sequential)
|
{
|
{
|
/* Use a sequential NOP rather than a parallel one,
|
/* Use a sequential NOP rather than a parallel one,
|
as the current instruction is a FLAG_MUL32 type one
|
as the current instruction is a FLAG_MUL32 type one
|
and the next instruction is a load. */
|
and the next instruction is a load. */
|
|
|
/* According to 4.3.1: for FM=01, sub-instructions performed
|
/* According to 4.3.1: for FM=01, sub-instructions performed
|
only by IU cannot be encoded in L-container. */
|
only by IU cannot be encoded in L-container. */
|
if (opcode->op->unit == IU)
|
if (opcode->op->unit == IU)
|
/* Right then left. */
|
/* Right then left. */
|
insn |= FM10 | NOP_LEFT;
|
insn |= FM10 | NOP_LEFT;
|
else
|
else
|
/* Left then right. */
|
/* Left then right. */
|
insn = FM01 | (insn << 32) | NOP_RIGHT;
|
insn = FM01 | (insn << 32) | NOP_RIGHT;
|
}
|
}
|
else
|
else
|
{
|
{
|
/* According to 4.3.1: for FM=00, sub-instructions performed
|
/* According to 4.3.1: for FM=00, sub-instructions performed
|
only by IU cannot be encoded in L-container. */
|
only by IU cannot be encoded in L-container. */
|
if (opcode->op->unit == IU)
|
if (opcode->op->unit == IU)
|
/* Right container. */
|
/* Right container. */
|
insn |= FM00 | NOP_LEFT;
|
insn |= FM00 | NOP_LEFT;
|
else
|
else
|
/* Left container. */
|
/* Left container. */
|
insn = FM00 | (insn << 32) | NOP_RIGHT;
|
insn = FM00 | (insn << 32) | NOP_RIGHT;
|
}
|
}
|
|
|
d30v_number_to_chars (f, insn, 8);
|
d30v_number_to_chars (f, insn, 8);
|
|
|
for (i = 0; i < fx->fc; i++)
|
for (i = 0; i < fx->fc; i++)
|
{
|
{
|
if (fx->fix[i].reloc)
|
if (fx->fix[i].reloc)
|
{
|
{
|
where = f - frag_now->fr_literal;
|
where = f - frag_now->fr_literal;
|
fix_new_exp (frag_now,
|
fix_new_exp (frag_now,
|
where,
|
where,
|
fx->fix[i].size,
|
fx->fix[i].size,
|
&(fx->fix[i].exp),
|
&(fx->fix[i].exp),
|
fx->fix[i].pcrel,
|
fx->fix[i].pcrel,
|
fx->fix[i].reloc);
|
fx->fix[i].reloc);
|
}
|
}
|
}
|
}
|
|
|
fx->fc = 0;
|
fx->fc = 0;
|
}
|
}
|
|
|
/* Check 2 instructions and determine if they can be safely
|
/* Check 2 instructions and determine if they can be safely
|
executed in parallel. Return 1 if they can be. */
|
executed in parallel. Return 1 if they can be. */
|
|
|
static int
|
static int
|
parallel_ok (struct d30v_insn *op1,
|
parallel_ok (struct d30v_insn *op1,
|
unsigned long insn1,
|
unsigned long insn1,
|
struct d30v_insn *op2,
|
struct d30v_insn *op2,
|
unsigned long insn2,
|
unsigned long insn2,
|
exec_type_enum exec_type)
|
exec_type_enum exec_type)
|
{
|
{
|
int i, j, shift, regno, bits, ecc;
|
int i, j, shift, regno, bits, ecc;
|
unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
|
unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
|
unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2];
|
unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2];
|
struct d30v_format *f;
|
struct d30v_format *f;
|
struct d30v_opcode *op;
|
struct d30v_opcode *op;
|
|
|
/* Section 4.3: Both instructions must not be IU or MU only. */
|
/* Section 4.3: Both instructions must not be IU or MU only. */
|
if ((op1->op->unit == IU && op2->op->unit == IU)
|
if ((op1->op->unit == IU && op2->op->unit == IU)
|
|| (op1->op->unit == MU && op2->op->unit == MU))
|
|| (op1->op->unit == MU && op2->op->unit == MU))
|
return 0;
|
return 0;
|
|
|
/* First instruction must not be a jump to safely optimize, unless this
|
/* First instruction must not be a jump to safely optimize, unless this
|
is an explicit parallel operation. */
|
is an explicit parallel operation. */
|
if (exec_type != EXEC_PARALLEL
|
if (exec_type != EXEC_PARALLEL
|
&& (op1->op->flags_used & (FLAG_JMP | FLAG_JSR)))
|
&& (op1->op->flags_used & (FLAG_JMP | FLAG_JSR)))
|
return 0;
|
return 0;
|
|
|
/* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
|
/* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
|
then it is safe to allow the two to be done as parallel ops, since only
|
then it is safe to allow the two to be done as parallel ops, since only
|
one will ever be executed at a time. */
|
one will ever be executed at a time. */
|
if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX)
|
if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX)
|
|| (op1->ecc == ECC_FX && op2->ecc == ECC_TX)
|
|| (op1->ecc == ECC_FX && op2->ecc == ECC_TX)
|
|| (op1->ecc == ECC_XT && op2->ecc == ECC_XF)
|
|| (op1->ecc == ECC_XT && op2->ecc == ECC_XF)
|
|| (op1->ecc == ECC_XF && op2->ecc == ECC_XT))
|
|| (op1->ecc == ECC_XF && op2->ecc == ECC_XT))
|
return 1;
|
return 1;
|
|
|
/* [0] r0-r31
|
/* [0] r0-r31
|
[1] r32-r63
|
[1] r32-r63
|
[2] a0, a1, flag registers. */
|
[2] a0, a1, flag registers. */
|
for (j = 0; j < 2; j++)
|
for (j = 0; j < 2; j++)
|
{
|
{
|
if (j == 0)
|
if (j == 0)
|
{
|
{
|
f = op1->form;
|
f = op1->form;
|
op = op1->op;
|
op = op1->op;
|
ecc = op1->ecc;
|
ecc = op1->ecc;
|
ins = insn1;
|
ins = insn1;
|
}
|
}
|
else
|
else
|
{
|
{
|
f = op2->form;
|
f = op2->form;
|
op = op2->op;
|
op = op2->op;
|
ecc = op2->ecc;
|
ecc = op2->ecc;
|
ins = insn2;
|
ins = insn2;
|
}
|
}
|
|
|
flag_reg[j] = 0;
|
flag_reg[j] = 0;
|
mod_reg[j][0] = mod_reg[j][1] = 0;
|
mod_reg[j][0] = mod_reg[j][1] = 0;
|
used_reg[j][0] = used_reg[j][1] = 0;
|
used_reg[j][0] = used_reg[j][1] = 0;
|
|
|
if (flag_explicitly_parallel)
|
if (flag_explicitly_parallel)
|
{
|
{
|
/* For human specified parallel instructions we have been asked
|
/* For human specified parallel instructions we have been asked
|
to ignore the possibility that both instructions could modify
|
to ignore the possibility that both instructions could modify
|
bits in the PSW, so we initialise the mod & used arrays to 0.
|
bits in the PSW, so we initialise the mod & used arrays to 0.
|
We have been asked, however, to refuse to allow parallel
|
We have been asked, however, to refuse to allow parallel
|
instructions which explicitly set the same flag register,
|
instructions which explicitly set the same flag register,
|
eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
|
eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
|
for the use of a flag register and set a bit in the mod or used
|
for the use of a flag register and set a bit in the mod or used
|
array appropriately. */
|
array appropriately. */
|
mod_reg[j][2] = 0;
|
mod_reg[j][2] = 0;
|
used_reg[j][2] = 0;
|
used_reg[j][2] = 0;
|
}
|
}
|
else
|
else
|
{
|
{
|
mod_reg[j][2] = (op->flags_set & FLAG_ALL);
|
mod_reg[j][2] = (op->flags_set & FLAG_ALL);
|
used_reg[j][2] = (op->flags_used & FLAG_ALL);
|
used_reg[j][2] = (op->flags_used & FLAG_ALL);
|
}
|
}
|
|
|
/* BSR/JSR always sets R62. */
|
/* BSR/JSR always sets R62. */
|
if (op->flags_used & FLAG_JSR)
|
if (op->flags_used & FLAG_JSR)
|
mod_reg[j][1] = (1L << (62 - 32));
|
mod_reg[j][1] = (1L << (62 - 32));
|
|
|
/* Conditional execution affects the flags_used. */
|
/* Conditional execution affects the flags_used. */
|
switch (ecc)
|
switch (ecc)
|
{
|
{
|
case ECC_TX:
|
case ECC_TX:
|
case ECC_FX:
|
case ECC_FX:
|
used_reg[j][2] |= flag_reg[j] = FLAG_0;
|
used_reg[j][2] |= flag_reg[j] = FLAG_0;
|
break;
|
break;
|
|
|
case ECC_XT:
|
case ECC_XT:
|
case ECC_XF:
|
case ECC_XF:
|
used_reg[j][2] |= flag_reg[j] = FLAG_1;
|
used_reg[j][2] |= flag_reg[j] = FLAG_1;
|
break;
|
break;
|
|
|
case ECC_TT:
|
case ECC_TT:
|
case ECC_TF:
|
case ECC_TF:
|
used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1);
|
used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1);
|
break;
|
break;
|
}
|
}
|
|
|
for (i = 0; f->operands[i]; i++)
|
for (i = 0; f->operands[i]; i++)
|
{
|
{
|
flags = d30v_operand_table[f->operands[i]].flags;
|
flags = d30v_operand_table[f->operands[i]].flags;
|
shift = 12 - d30v_operand_table[f->operands[i]].position;
|
shift = 12 - d30v_operand_table[f->operands[i]].position;
|
bits = d30v_operand_table[f->operands[i]].bits;
|
bits = d30v_operand_table[f->operands[i]].bits;
|
if (bits == 32)
|
if (bits == 32)
|
mask = 0xffffffff;
|
mask = 0xffffffff;
|
else
|
else
|
mask = 0x7FFFFFFF >> (31 - bits);
|
mask = 0x7FFFFFFF >> (31 - bits);
|
|
|
if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS))
|
if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS))
|
{
|
{
|
/* This is a post-increment or post-decrement.
|
/* This is a post-increment or post-decrement.
|
The previous register needs to be marked as modified. */
|
The previous register needs to be marked as modified. */
|
shift = 12 - d30v_operand_table[f->operands[i - 1]].position;
|
shift = 12 - d30v_operand_table[f->operands[i - 1]].position;
|
regno = (ins >> shift) & 0x3f;
|
regno = (ins >> shift) & 0x3f;
|
if (regno >= 32)
|
if (regno >= 32)
|
mod_reg[j][1] |= 1L << (regno - 32);
|
mod_reg[j][1] |= 1L << (regno - 32);
|
else
|
else
|
mod_reg[j][0] |= 1L << regno;
|
mod_reg[j][0] |= 1L << regno;
|
}
|
}
|
else if (flags & OPERAND_REG)
|
else if (flags & OPERAND_REG)
|
{
|
{
|
regno = (ins >> shift) & mask;
|
regno = (ins >> shift) & mask;
|
/* The memory write functions don't have a destination
|
/* The memory write functions don't have a destination
|
register. */
|
register. */
|
if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM))
|
if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM))
|
{
|
{
|
/* MODIFIED registers and flags. */
|
/* MODIFIED registers and flags. */
|
if (flags & OPERAND_ACC)
|
if (flags & OPERAND_ACC)
|
{
|
{
|
if (regno == 0)
|
if (regno == 0)
|
mod_reg[j][2] |= FLAG_A0;
|
mod_reg[j][2] |= FLAG_A0;
|
else if (regno == 1)
|
else if (regno == 1)
|
mod_reg[j][2] |= FLAG_A1;
|
mod_reg[j][2] |= FLAG_A1;
|
else
|
else
|
abort ();
|
abort ();
|
}
|
}
|
else if (flags & OPERAND_FLAG)
|
else if (flags & OPERAND_FLAG)
|
mod_reg[j][2] |= 1L << regno;
|
mod_reg[j][2] |= 1L << regno;
|
else if (!(flags & OPERAND_CONTROL))
|
else if (!(flags & OPERAND_CONTROL))
|
{
|
{
|
int r, z;
|
int r, z;
|
|
|
/* Need to check if there are two destination
|
/* Need to check if there are two destination
|
registers, for example ld2w. */
|
registers, for example ld2w. */
|
if (flags & OPERAND_2REG)
|
if (flags & OPERAND_2REG)
|
z = 1;
|
z = 1;
|
else
|
else
|
z = 0;
|
z = 0;
|
|
|
for (r = regno; r <= regno + z; r++)
|
for (r = regno; r <= regno + z; r++)
|
{
|
{
|
if (r >= 32)
|
if (r >= 32)
|
mod_reg[j][1] |= 1L << (r - 32);
|
mod_reg[j][1] |= 1L << (r - 32);
|
else
|
else
|
mod_reg[j][0] |= 1L << r;
|
mod_reg[j][0] |= 1L << r;
|
}
|
}
|
}
|
}
|
}
|
}
|
else
|
else
|
{
|
{
|
/* USED, but not modified registers and flags. */
|
/* USED, but not modified registers and flags. */
|
if (flags & OPERAND_ACC)
|
if (flags & OPERAND_ACC)
|
{
|
{
|
if (regno == 0)
|
if (regno == 0)
|
used_reg[j][2] |= FLAG_A0;
|
used_reg[j][2] |= FLAG_A0;
|
else if (regno == 1)
|
else if (regno == 1)
|
used_reg[j][2] |= FLAG_A1;
|
used_reg[j][2] |= FLAG_A1;
|
else
|
else
|
abort ();
|
abort ();
|
}
|
}
|
else if (flags & OPERAND_FLAG)
|
else if (flags & OPERAND_FLAG)
|
used_reg[j][2] |= 1L << regno;
|
used_reg[j][2] |= 1L << regno;
|
else if (!(flags & OPERAND_CONTROL))
|
else if (!(flags & OPERAND_CONTROL))
|
{
|
{
|
int r, z;
|
int r, z;
|
|
|
/* Need to check if there are two source
|
/* Need to check if there are two source
|
registers, for example st2w. */
|
registers, for example st2w. */
|
if (flags & OPERAND_2REG)
|
if (flags & OPERAND_2REG)
|
z = 1;
|
z = 1;
|
else
|
else
|
z = 0;
|
z = 0;
|
|
|
for (r = regno; r <= regno + z; r++)
|
for (r = regno; r <= regno + z; r++)
|
{
|
{
|
if (r >= 32)
|
if (r >= 32)
|
used_reg[j][1] |= 1L << (r - 32);
|
used_reg[j][1] |= 1L << (r - 32);
|
else
|
else
|
used_reg[j][0] |= 1L << r;
|
used_reg[j][0] |= 1L << r;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
flags_set1 = op1->op->flags_set;
|
flags_set1 = op1->op->flags_set;
|
flags_set2 = op2->op->flags_set;
|
flags_set2 = op2->op->flags_set;
|
flags_used1 = op1->op->flags_used;
|
flags_used1 = op1->op->flags_used;
|
flags_used2 = op2->op->flags_used;
|
flags_used2 = op2->op->flags_used;
|
|
|
/* Check for illegal combinations with ADDppp/SUBppp. */
|
/* Check for illegal combinations with ADDppp/SUBppp. */
|
if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0
|
if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0
|
&& (flags_used2 & FLAG_ADDSUBppp) != 0)
|
&& (flags_used2 & FLAG_ADDSUBppp) != 0)
|
|| ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0
|
|| ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0
|
&& (flags_used1 & FLAG_ADDSUBppp) != 0))
|
&& (flags_used1 & FLAG_ADDSUBppp) != 0))
|
return 0;
|
return 0;
|
|
|
/* Load instruction combined with half-word multiply is illegal. */
|
/* Load instruction combined with half-word multiply is illegal. */
|
if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16))
|
if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16))
|
|| ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16)))
|
|| ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16)))
|
return 0;
|
return 0;
|
|
|
/* Specifically allow add || add by removing carry, overflow bits dependency.
|
/* Specifically allow add || add by removing carry, overflow bits dependency.
|
This is safe, even if an addc follows since the IU takes the argument in
|
This is safe, even if an addc follows since the IU takes the argument in
|
the right container, and it writes its results last.
|
the right container, and it writes its results last.
|
However, don't paralellize add followed by addc or sub followed by
|
However, don't paralellize add followed by addc or sub followed by
|
subb. */
|
subb. */
|
if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA
|
if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA
|
&& (used_reg[0][2] & ~flag_reg[0]) == 0
|
&& (used_reg[0][2] & ~flag_reg[0]) == 0
|
&& (used_reg[1][2] & ~flag_reg[1]) == 0
|
&& (used_reg[1][2] & ~flag_reg[1]) == 0
|
&& op1->op->unit == EITHER && op2->op->unit == EITHER)
|
&& op1->op->unit == EITHER && op2->op->unit == EITHER)
|
{
|
{
|
mod_reg[0][2] = mod_reg[1][2] = 0;
|
mod_reg[0][2] = mod_reg[1][2] = 0;
|
}
|
}
|
|
|
for (j = 0; j < 3; j++)
|
for (j = 0; j < 3; j++)
|
{
|
{
|
/* If the second instruction depends on the first, we obviously
|
/* If the second instruction depends on the first, we obviously
|
cannot parallelize. Note, the mod flag implies use, so
|
cannot parallelize. Note, the mod flag implies use, so
|
check that as well. */
|
check that as well. */
|
/* If flag_explicitly_parallel is set, then the case of the
|
/* If flag_explicitly_parallel is set, then the case of the
|
second instruction using a register the first instruction
|
second instruction using a register the first instruction
|
modifies is assumed to be okay; we trust the human. We
|
modifies is assumed to be okay; we trust the human. We
|
don't trust the human if both instructions modify the same
|
don't trust the human if both instructions modify the same
|
register but we do trust the human if they modify the same
|
register but we do trust the human if they modify the same
|
flags. */
|
flags. */
|
/* We have now been requested not to trust the human if the
|
/* We have now been requested not to trust the human if the
|
instructions modify the same flag registers either. */
|
instructions modify the same flag registers either. */
|
if (flag_explicitly_parallel)
|
if (flag_explicitly_parallel)
|
{
|
{
|
if ((mod_reg[0][j] & mod_reg[1][j]) != 0)
|
if ((mod_reg[0][j] & mod_reg[1][j]) != 0)
|
return 0;
|
return 0;
|
}
|
}
|
else
|
else
|
if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0)
|
if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0)
|
return 0;
|
return 0;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
/* Write out a short form instruction if possible.
|
/* Write out a short form instruction if possible.
|
Return number of instructions not written out. */
|
Return number of instructions not written out. */
|
|
|
static int
|
static int
|
write_2_short (struct d30v_insn *opcode1,
|
write_2_short (struct d30v_insn *opcode1,
|
long long insn1,
|
long long insn1,
|
struct d30v_insn *opcode2,
|
struct d30v_insn *opcode2,
|
long long insn2,
|
long long insn2,
|
exec_type_enum exec_type,
|
exec_type_enum exec_type,
|
Fixups *fx)
|
Fixups *fx)
|
{
|
{
|
long long insn = NOP2;
|
long long insn = NOP2;
|
char *f;
|
char *f;
|
int i, j, where;
|
int i, j, where;
|
|
|
if (exec_type == EXEC_SEQ
|
if (exec_type == EXEC_SEQ
|
&& (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
|
&& (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
|
&& ((opcode1->op->flags_used & FLAG_DELAY) == 0)
|
&& ((opcode1->op->flags_used & FLAG_DELAY) == 0)
|
&& ((opcode1->ecc == ECC_AL) || ! Optimizing))
|
&& ((opcode1->ecc == ECC_AL) || ! Optimizing))
|
{
|
{
|
/* Unconditional, non-delayed branches kill instructions in
|
/* Unconditional, non-delayed branches kill instructions in
|
the right bin. Conditional branches don't always but if
|
the right bin. Conditional branches don't always but if
|
we are not optimizing, then we have been asked to produce
|
we are not optimizing, then we have been asked to produce
|
an error about such constructs. For the purposes of this
|
an error about such constructs. For the purposes of this
|
test, subroutine calls are considered to be branches. */
|
test, subroutine calls are considered to be branches. */
|
write_1_short (opcode1, insn1, fx->next, FALSE);
|
write_1_short (opcode1, insn1, fx->next, FALSE);
|
return 1;
|
return 1;
|
}
|
}
|
|
|
/* Note: we do not have to worry about subroutine calls occurring
|
/* Note: we do not have to worry about subroutine calls occurring
|
in the right hand container. The return address is always
|
in the right hand container. The return address is always
|
aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
|
aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
|
switch (exec_type)
|
switch (exec_type)
|
{
|
{
|
case EXEC_UNKNOWN: /* Order not specified. */
|
case EXEC_UNKNOWN: /* Order not specified. */
|
if (Optimizing
|
if (Optimizing
|
&& parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
|
&& parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
|
&& ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU
|
&& ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU
|
|| opcode1->op->unit == MU)
|
|| opcode1->op->unit == MU)
|
&&
|
&&
|
( opcode2->op->unit == EITHER_BUT_PREFER_MU
|
( opcode2->op->unit == EITHER_BUT_PREFER_MU
|
|| opcode2->op->unit == MU)))
|
|| opcode2->op->unit == MU)))
|
{
|
{
|
/* Parallel. */
|
/* Parallel. */
|
exec_type = EXEC_PARALLEL;
|
exec_type = EXEC_PARALLEL;
|
|
|
if (opcode1->op->unit == IU
|
if (opcode1->op->unit == IU
|
|| opcode2->op->unit == MU
|
|| opcode2->op->unit == MU
|
|| opcode2->op->unit == EITHER_BUT_PREFER_MU)
|
|| opcode2->op->unit == EITHER_BUT_PREFER_MU)
|
insn = FM00 | (insn2 << 32) | insn1;
|
insn = FM00 | (insn2 << 32) | insn1;
|
else
|
else
|
{
|
{
|
insn = FM00 | (insn1 << 32) | insn2;
|
insn = FM00 | (insn1 << 32) | insn2;
|
fx = fx->next;
|
fx = fx->next;
|
}
|
}
|
}
|
}
|
else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)
|
else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)
|
&& ((opcode1->op->flags_used & FLAG_DELAY) == 0))
|
&& ((opcode1->op->flags_used & FLAG_DELAY) == 0))
|
|| opcode1->op->flags_used & FLAG_RP)
|
|| opcode1->op->flags_used & FLAG_RP)
|
{
|
{
|
/* We must emit (non-delayed) branch type instructions
|
/* We must emit (non-delayed) branch type instructions
|
on their own with nothing in the right container. */
|
on their own with nothing in the right container. */
|
/* We must treat repeat instructions likewise, since the
|
/* We must treat repeat instructions likewise, since the
|
following instruction has to be separate from the repeat
|
following instruction has to be separate from the repeat
|
in order to be repeated. */
|
in order to be repeated. */
|
write_1_short (opcode1, insn1, fx->next, FALSE);
|
write_1_short (opcode1, insn1, fx->next, FALSE);
|
return 1;
|
return 1;
|
}
|
}
|
else if (prev_left_kills_right_p)
|
else if (prev_left_kills_right_p)
|
{
|
{
|
/* The left instruction kils the right slot, so we
|
/* The left instruction kils the right slot, so we
|
must leave it empty. */
|
must leave it empty. */
|
write_1_short (opcode1, insn1, fx->next, FALSE);
|
write_1_short (opcode1, insn1, fx->next, FALSE);
|
return 1;
|
return 1;
|
}
|
}
|
else if (opcode1->op->unit == IU)
|
else if (opcode1->op->unit == IU)
|
{
|
{
|
if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
|
if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
|
{
|
{
|
/* Case 103810 is a request from Mitsubishi that opcodes
|
/* Case 103810 is a request from Mitsubishi that opcodes
|
with EITHER_BUT_PREFER_MU should not be executed in
|
with EITHER_BUT_PREFER_MU should not be executed in
|
reverse sequential order. */
|
reverse sequential order. */
|
write_1_short (opcode1, insn1, fx->next, FALSE);
|
write_1_short (opcode1, insn1, fx->next, FALSE);
|
return 1;
|
return 1;
|
}
|
}
|
|
|
/* Reverse sequential. */
|
/* Reverse sequential. */
|
insn = FM10 | (insn2 << 32) | insn1;
|
insn = FM10 | (insn2 << 32) | insn1;
|
exec_type = EXEC_REVSEQ;
|
exec_type = EXEC_REVSEQ;
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Sequential. */
|
/* Sequential. */
|
insn = FM01 | (insn1 << 32) | insn2;
|
insn = FM01 | (insn1 << 32) | insn2;
|
fx = fx->next;
|
fx = fx->next;
|
exec_type = EXEC_SEQ;
|
exec_type = EXEC_SEQ;
|
}
|
}
|
break;
|
break;
|
|
|
case EXEC_PARALLEL: /* Parallel. */
|
case EXEC_PARALLEL: /* Parallel. */
|
flag_explicitly_parallel = flag_xp_state;
|
flag_explicitly_parallel = flag_xp_state;
|
if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
|
if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
|
as_bad (_("Instructions may not be executed in parallel"));
|
as_bad (_("Instructions may not be executed in parallel"));
|
else if (opcode1->op->unit == IU)
|
else if (opcode1->op->unit == IU)
|
{
|
{
|
if (opcode2->op->unit == IU)
|
if (opcode2->op->unit == IU)
|
as_bad (_("Two IU instructions may not be executed in parallel"));
|
as_bad (_("Two IU instructions may not be executed in parallel"));
|
as_warn (_("Swapping instruction order"));
|
as_warn (_("Swapping instruction order"));
|
insn = FM00 | (insn2 << 32) | insn1;
|
insn = FM00 | (insn2 << 32) | insn1;
|
}
|
}
|
else if (opcode2->op->unit == MU)
|
else if (opcode2->op->unit == MU)
|
{
|
{
|
if (opcode1->op->unit == MU)
|
if (opcode1->op->unit == MU)
|
as_bad (_("Two MU instructions may not be executed in parallel"));
|
as_bad (_("Two MU instructions may not be executed in parallel"));
|
else if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
|
else if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
|
as_warn (_("Executing %s in IU may not work"), opcode1->op->name);
|
as_warn (_("Executing %s in IU may not work"), opcode1->op->name);
|
as_warn (_("Swapping instruction order"));
|
as_warn (_("Swapping instruction order"));
|
insn = FM00 | (insn2 << 32) | insn1;
|
insn = FM00 | (insn2 << 32) | insn1;
|
}
|
}
|
else
|
else
|
{
|
{
|
if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
|
if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
|
as_warn (_("Executing %s in IU may not work in parallel execution"),
|
as_warn (_("Executing %s in IU may not work in parallel execution"),
|
opcode2->op->name);
|
opcode2->op->name);
|
|
|
insn = FM00 | (insn1 << 32) | insn2;
|
insn = FM00 | (insn1 << 32) | insn2;
|
fx = fx->next;
|
fx = fx->next;
|
}
|
}
|
flag_explicitly_parallel = 0;
|
flag_explicitly_parallel = 0;
|
break;
|
break;
|
|
|
case EXEC_SEQ: /* Sequential. */
|
case EXEC_SEQ: /* Sequential. */
|
if (opcode1->op->unit == IU)
|
if (opcode1->op->unit == IU)
|
as_bad (_("IU instruction may not be in the left container"));
|
as_bad (_("IU instruction may not be in the left container"));
|
if (prev_left_kills_right_p)
|
if (prev_left_kills_right_p)
|
as_bad (_("special left instruction `%s' kills instruction "
|
as_bad (_("special left instruction `%s' kills instruction "
|
"`%s' in right container"),
|
"`%s' in right container"),
|
opcode1->op->name, opcode2->op->name);
|
opcode1->op->name, opcode2->op->name);
|
insn = FM01 | (insn1 << 32) | insn2;
|
insn = FM01 | (insn1 << 32) | insn2;
|
fx = fx->next;
|
fx = fx->next;
|
break;
|
break;
|
|
|
case EXEC_REVSEQ: /* Reverse sequential. */
|
case EXEC_REVSEQ: /* Reverse sequential. */
|
if (opcode2->op->unit == MU)
|
if (opcode2->op->unit == MU)
|
as_bad (_("MU instruction may not be in the right container"));
|
as_bad (_("MU instruction may not be in the right container"));
|
if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
|
if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
|
as_warn (_("Executing %s in reverse serial with %s may not work"),
|
as_warn (_("Executing %s in reverse serial with %s may not work"),
|
opcode1->op->name, opcode2->op->name);
|
opcode1->op->name, opcode2->op->name);
|
else if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
|
else if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
|
as_warn (_("Executing %s in IU in reverse serial may not work"),
|
as_warn (_("Executing %s in IU in reverse serial may not work"),
|
opcode2->op->name);
|
opcode2->op->name);
|
insn = FM10 | (insn1 << 32) | insn2;
|
insn = FM10 | (insn1 << 32) | insn2;
|
fx = fx->next;
|
fx = fx->next;
|
break;
|
break;
|
|
|
default:
|
default:
|
as_fatal (_("unknown execution type passed to write_2_short()"));
|
as_fatal (_("unknown execution type passed to write_2_short()"));
|
}
|
}
|
|
|
f = frag_more (8);
|
f = frag_more (8);
|
d30v_number_to_chars (f, insn, 8);
|
d30v_number_to_chars (f, insn, 8);
|
|
|
/* If the previous instruction was a 32-bit multiply but it is put into a
|
/* If the previous instruction was a 32-bit multiply but it is put into a
|
parallel container, mark the current instruction as being a 32-bit
|
parallel container, mark the current instruction as being a 32-bit
|
multiply. */
|
multiply. */
|
if (prev_mul32_p && exec_type == EXEC_PARALLEL)
|
if (prev_mul32_p && exec_type == EXEC_PARALLEL)
|
cur_mul32_p = 1;
|
cur_mul32_p = 1;
|
|
|
for (j = 0; j < 2; j++)
|
for (j = 0; j < 2; j++)
|
{
|
{
|
for (i = 0; i < fx->fc; i++)
|
for (i = 0; i < fx->fc; i++)
|
{
|
{
|
if (fx->fix[i].reloc)
|
if (fx->fix[i].reloc)
|
{
|
{
|
where = (f - frag_now->fr_literal) + 4 * j;
|
where = (f - frag_now->fr_literal) + 4 * j;
|
|
|
fix_new_exp (frag_now,
|
fix_new_exp (frag_now,
|
where,
|
where,
|
fx->fix[i].size,
|
fx->fix[i].size,
|
&(fx->fix[i].exp),
|
&(fx->fix[i].exp),
|
fx->fix[i].pcrel,
|
fx->fix[i].pcrel,
|
fx->fix[i].reloc);
|
fx->fix[i].reloc);
|
}
|
}
|
}
|
}
|
|
|
fx->fc = 0;
|
fx->fc = 0;
|
fx = fx->next;
|
fx = fx->next;
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Get a pointer to an entry in the format table.
|
/* Get a pointer to an entry in the format table.
|
It must look at all formats for an opcode and use the operands
|
It must look at all formats for an opcode and use the operands
|
to choose the correct one. Return NULL on error. */
|
to choose the correct one. Return NULL on error. */
|
|
|
static struct d30v_format *
|
static struct d30v_format *
|
find_format (struct d30v_opcode *opcode,
|
find_format (struct d30v_opcode *opcode,
|
expressionS myops[],
|
expressionS myops[],
|
int fsize,
|
int fsize,
|
int cmp_hack)
|
int cmp_hack)
|
{
|
{
|
int numops, match, index, i = 0, j, k;
|
int numops, match, index, i = 0, j, k;
|
struct d30v_format *fm;
|
struct d30v_format *fm;
|
|
|
if (opcode == NULL)
|
if (opcode == NULL)
|
return NULL;
|
return NULL;
|
|
|
/* Get all the operands and save them as expressions. */
|
/* Get all the operands and save them as expressions. */
|
numops = get_operands (myops, cmp_hack);
|
numops = get_operands (myops, cmp_hack);
|
|
|
while ((index = opcode->format[i++]) != 0)
|
while ((index = opcode->format[i++]) != 0)
|
{
|
{
|
if (fsize == FORCE_SHORT && index >= LONG)
|
if (fsize == FORCE_SHORT && index >= LONG)
|
continue;
|
continue;
|
|
|
if (fsize == FORCE_LONG && index < LONG)
|
if (fsize == FORCE_LONG && index < LONG)
|
continue;
|
continue;
|
|
|
fm = (struct d30v_format *) &d30v_format_table[index];
|
fm = (struct d30v_format *) &d30v_format_table[index];
|
k = index;
|
k = index;
|
while (fm->form == index)
|
while (fm->form == index)
|
{
|
{
|
match = 1;
|
match = 1;
|
/* Now check the operands for compatibility. */
|
/* Now check the operands for compatibility. */
|
for (j = 0; match && fm->operands[j]; j++)
|
for (j = 0; match && fm->operands[j]; j++)
|
{
|
{
|
int flags = d30v_operand_table[fm->operands[j]].flags;
|
int flags = d30v_operand_table[fm->operands[j]].flags;
|
int bits = d30v_operand_table[fm->operands[j]].bits;
|
int bits = d30v_operand_table[fm->operands[j]].bits;
|
int X_op = myops[j].X_op;
|
int X_op = myops[j].X_op;
|
int num = myops[j].X_add_number;
|
int num = myops[j].X_add_number;
|
|
|
if (flags & OPERAND_SPECIAL)
|
if (flags & OPERAND_SPECIAL)
|
break;
|
break;
|
else if (X_op == O_illegal)
|
else if (X_op == O_illegal)
|
match = 0;
|
match = 0;
|
else if (flags & OPERAND_REG)
|
else if (flags & OPERAND_REG)
|
{
|
{
|
if (X_op != O_register
|
if (X_op != O_register
|
|| ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
|
|| ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
|
|| (!(flags & OPERAND_ACC) && (num & OPERAND_ACC))
|
|| (!(flags & OPERAND_ACC) && (num & OPERAND_ACC))
|
|| ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
|
|| ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
|
|| (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG))
|
|| (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG))
|
|| ((flags & OPERAND_CONTROL)
|
|| ((flags & OPERAND_CONTROL)
|
&& !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
|
&& !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
|
match = 0;
|
match = 0;
|
}
|
}
|
else if (((flags & OPERAND_MINUS)
|
else if (((flags & OPERAND_MINUS)
|
&& (X_op != O_absent || num != OPERAND_MINUS))
|
&& (X_op != O_absent || num != OPERAND_MINUS))
|
|| ((flags & OPERAND_PLUS)
|
|| ((flags & OPERAND_PLUS)
|
&& (X_op != O_absent || num != OPERAND_PLUS))
|
&& (X_op != O_absent || num != OPERAND_PLUS))
|
|| ((flags & OPERAND_ATMINUS)
|
|| ((flags & OPERAND_ATMINUS)
|
&& (X_op != O_absent || num != OPERAND_ATMINUS))
|
&& (X_op != O_absent || num != OPERAND_ATMINUS))
|
|| ((flags & OPERAND_ATPAR)
|
|| ((flags & OPERAND_ATPAR)
|
&& (X_op != O_absent || num != OPERAND_ATPAR))
|
&& (X_op != O_absent || num != OPERAND_ATPAR))
|
|| ((flags & OPERAND_ATSIGN)
|
|| ((flags & OPERAND_ATSIGN)
|
&& (X_op != O_absent || num != OPERAND_ATSIGN)))
|
&& (X_op != O_absent || num != OPERAND_ATSIGN)))
|
match = 0;
|
match = 0;
|
else if (flags & OPERAND_NUM)
|
else if (flags & OPERAND_NUM)
|
{
|
{
|
/* A number can be a constant or symbol expression. */
|
/* A number can be a constant or symbol expression. */
|
|
|
/* If we have found a register name, but that name
|
/* If we have found a register name, but that name
|
also matches a symbol, then re-parse the name as
|
also matches a symbol, then re-parse the name as
|
an expression. */
|
an expression. */
|
if (X_op == O_register
|
if (X_op == O_register
|
&& symbol_find ((char *) myops[j].X_op_symbol))
|
&& symbol_find ((char *) myops[j].X_op_symbol))
|
{
|
{
|
input_line_pointer = (char *) myops[j].X_op_symbol;
|
input_line_pointer = (char *) myops[j].X_op_symbol;
|
expression (&myops[j]);
|
expression (&myops[j]);
|
}
|
}
|
|
|
/* Turn an expression into a symbol for later resolution. */
|
/* Turn an expression into a symbol for later resolution. */
|
if (X_op != O_absent && X_op != O_constant
|
if (X_op != O_absent && X_op != O_constant
|
&& X_op != O_symbol && X_op != O_register
|
&& X_op != O_symbol && X_op != O_register
|
&& X_op != O_big)
|
&& X_op != O_big)
|
{
|
{
|
symbolS *sym = make_expr_symbol (&myops[j]);
|
symbolS *sym = make_expr_symbol (&myops[j]);
|
myops[j].X_op = X_op = O_symbol;
|
myops[j].X_op = X_op = O_symbol;
|
myops[j].X_add_symbol = sym;
|
myops[j].X_add_symbol = sym;
|
myops[j].X_add_number = num = 0;
|
myops[j].X_add_number = num = 0;
|
}
|
}
|
|
|
if (fm->form >= LONG)
|
if (fm->form >= LONG)
|
{
|
{
|
/* If we're testing for a LONG format, either fits. */
|
/* If we're testing for a LONG format, either fits. */
|
if (X_op != O_constant && X_op != O_symbol)
|
if (X_op != O_constant && X_op != O_symbol)
|
match = 0;
|
match = 0;
|
}
|
}
|
else if (fm->form < LONG
|
else if (fm->form < LONG
|
&& ((fsize == FORCE_SHORT && X_op == O_symbol)
|
&& ((fsize == FORCE_SHORT && X_op == O_symbol)
|
|| (fm->form == SHORT_D2 && j == 0)))
|
|| (fm->form == SHORT_D2 && j == 0)))
|
match = 1;
|
match = 1;
|
|
|
/* This is the tricky part. Will the constant or symbol
|
/* This is the tricky part. Will the constant or symbol
|
fit into the space in the current format? */
|
fit into the space in the current format? */
|
else if (X_op == O_constant)
|
else if (X_op == O_constant)
|
{
|
{
|
if (check_range (num, bits, flags))
|
if (check_range (num, bits, flags))
|
match = 0;
|
match = 0;
|
}
|
}
|
else if (X_op == O_symbol
|
else if (X_op == O_symbol
|
&& S_IS_DEFINED (myops[j].X_add_symbol)
|
&& S_IS_DEFINED (myops[j].X_add_symbol)
|
&& S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
|
&& S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
|
&& opcode->reloc_flag == RELOC_PCREL)
|
&& opcode->reloc_flag == RELOC_PCREL)
|
{
|
{
|
/* If the symbol is defined, see if the value will fit
|
/* If the symbol is defined, see if the value will fit
|
into the form we're considering. */
|
into the form we're considering. */
|
fragS *f;
|
fragS *f;
|
long value;
|
long value;
|
|
|
/* Calculate the current address by running through the
|
/* Calculate the current address by running through the
|
previous frags and adding our current offset. */
|
previous frags and adding our current offset. */
|
value = 0;
|
value = 0;
|
for (f = frchain_now->frch_root; f; f = f->fr_next)
|
for (f = frchain_now->frch_root; f; f = f->fr_next)
|
value += f->fr_fix + f->fr_offset;
|
value += f->fr_fix + f->fr_offset;
|
value = (S_GET_VALUE (myops[j].X_add_symbol) - value
|
value = (S_GET_VALUE (myops[j].X_add_symbol) - value
|
- (obstack_next_free (&frchain_now->frch_obstack)
|
- (obstack_next_free (&frchain_now->frch_obstack)
|
- frag_now->fr_literal));
|
- frag_now->fr_literal));
|
if (check_range (value, bits, flags))
|
if (check_range (value, bits, flags))
|
match = 0;
|
match = 0;
|
}
|
}
|
else
|
else
|
match = 0;
|
match = 0;
|
}
|
}
|
}
|
}
|
/* We're only done if the operands matched so far AND there
|
/* We're only done if the operands matched so far AND there
|
are no more to check. */
|
are no more to check. */
|
if (match && myops[j].X_op == 0)
|
if (match && myops[j].X_op == 0)
|
{
|
{
|
/* Final check - issue a warning if an odd numbered register
|
/* Final check - issue a warning if an odd numbered register
|
is used as the first register in an instruction that reads
|
is used as the first register in an instruction that reads
|
or writes 2 registers. */
|
or writes 2 registers. */
|
|
|
for (j = 0; fm->operands[j]; j++)
|
for (j = 0; fm->operands[j]; j++)
|
if (myops[j].X_op == O_register
|
if (myops[j].X_op == O_register
|
&& (myops[j].X_add_number & 1)
|
&& (myops[j].X_add_number & 1)
|
&& (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG))
|
&& (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG))
|
as_warn (_("Odd numbered register used as target of multi-register instruction"));
|
as_warn (_("Odd numbered register used as target of multi-register instruction"));
|
|
|
return fm;
|
return fm;
|
}
|
}
|
fm = (struct d30v_format *) &d30v_format_table[++k];
|
fm = (struct d30v_format *) &d30v_format_table[++k];
|
}
|
}
|
}
|
}
|
return NULL;
|
return NULL;
|
}
|
}
|
|
|
/* Assemble a single instruction and return an opcode.
|
/* Assemble a single instruction and return an opcode.
|
Return -1 (an invalid opcode) on error. */
|
Return -1 (an invalid opcode) on error. */
|
|
|
#define NAME_BUF_LEN 20
|
#define NAME_BUF_LEN 20
|
|
|
static long long
|
static long long
|
do_assemble (char *str,
|
do_assemble (char *str,
|
struct d30v_insn *opcode,
|
struct d30v_insn *opcode,
|
int shortp,
|
int shortp,
|
int is_parallel)
|
int is_parallel)
|
{
|
{
|
char *op_start;
|
char *op_start;
|
char *save;
|
char *save;
|
char *op_end;
|
char *op_end;
|
char name[NAME_BUF_LEN];
|
char name[NAME_BUF_LEN];
|
int cmp_hack;
|
int cmp_hack;
|
int nlen = 0;
|
int nlen = 0;
|
int fsize = (shortp ? FORCE_SHORT : 0);
|
int fsize = (shortp ? FORCE_SHORT : 0);
|
expressionS myops[6];
|
expressionS myops[6];
|
long long insn;
|
long long insn;
|
|
|
/* Drop leading whitespace. */
|
/* Drop leading whitespace. */
|
while (*str == ' ')
|
while (*str == ' ')
|
str++;
|
str++;
|
|
|
/* Find the opcode end. */
|
/* Find the opcode end. */
|
for (op_start = op_end = str;
|
for (op_start = op_end = str;
|
*op_end
|
*op_end
|
&& nlen < (NAME_BUF_LEN - 1)
|
&& nlen < (NAME_BUF_LEN - 1)
|
&& *op_end != '/'
|
&& *op_end != '/'
|
&& !is_end_of_line[(unsigned char) *op_end] && *op_end != ' ';
|
&& !is_end_of_line[(unsigned char) *op_end] && *op_end != ' ';
|
op_end++)
|
op_end++)
|
{
|
{
|
name[nlen] = TOLOWER (op_start[nlen]);
|
name[nlen] = TOLOWER (op_start[nlen]);
|
nlen++;
|
nlen++;
|
}
|
}
|
|
|
if (nlen == 0)
|
if (nlen == 0)
|
return -1;
|
return -1;
|
|
|
name[nlen] = 0;
|
name[nlen] = 0;
|
|
|
/* If there is an execution condition code, handle it. */
|
/* If there is an execution condition code, handle it. */
|
if (*op_end == '/')
|
if (*op_end == '/')
|
{
|
{
|
int i = 0;
|
int i = 0;
|
while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2))
|
while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2))
|
i++;
|
i++;
|
|
|
if (i == ECC_MAX)
|
if (i == ECC_MAX)
|
{
|
{
|
char tmp[4];
|
char tmp[4];
|
strncpy (tmp, op_end + 1, 2);
|
strncpy (tmp, op_end + 1, 2);
|
tmp[2] = 0;
|
tmp[2] = 0;
|
as_bad (_("unknown condition code: %s"), tmp);
|
as_bad (_("unknown condition code: %s"), tmp);
|
return -1;
|
return -1;
|
}
|
}
|
opcode->ecc = i;
|
opcode->ecc = i;
|
op_end += 3;
|
op_end += 3;
|
}
|
}
|
else
|
else
|
opcode->ecc = ECC_AL;
|
opcode->ecc = ECC_AL;
|
|
|
/* CMP and CMPU change their name based on condition codes. */
|
/* CMP and CMPU change their name based on condition codes. */
|
if (!strncmp (name, "cmp", 3))
|
if (!strncmp (name, "cmp", 3))
|
{
|
{
|
int p, i;
|
int p, i;
|
char **str = (char **) d30v_cc_names;
|
char **str = (char **) d30v_cc_names;
|
if (name[3] == 'u')
|
if (name[3] == 'u')
|
p = 4;
|
p = 4;
|
else
|
else
|
p = 3;
|
p = 3;
|
|
|
for (i = 1; *str && strncmp (*str, &name[p], 2); i++, str++)
|
for (i = 1; *str && strncmp (*str, &name[p], 2); i++, str++)
|
;
|
;
|
|
|
/* cmpu only supports some condition codes. */
|
/* cmpu only supports some condition codes. */
|
if (p == 4)
|
if (p == 4)
|
{
|
{
|
if (i < 3 || i > 6)
|
if (i < 3 || i > 6)
|
{
|
{
|
name[p + 2] = 0;
|
name[p + 2] = 0;
|
as_bad (_("cmpu doesn't support condition code %s"), &name[p]);
|
as_bad (_("cmpu doesn't support condition code %s"), &name[p]);
|
}
|
}
|
}
|
}
|
|
|
if (!*str)
|
if (!*str)
|
{
|
{
|
name[p + 2] = 0;
|
name[p + 2] = 0;
|
as_bad (_("unknown condition code: %s"), &name[p]);
|
as_bad (_("unknown condition code: %s"), &name[p]);
|
}
|
}
|
|
|
cmp_hack = i;
|
cmp_hack = i;
|
name[p] = 0;
|
name[p] = 0;
|
}
|
}
|
else
|
else
|
cmp_hack = 0;
|
cmp_hack = 0;
|
|
|
/* Need to look for .s or .l. */
|
/* Need to look for .s or .l. */
|
if (name[nlen - 2] == '.')
|
if (name[nlen - 2] == '.')
|
{
|
{
|
switch (name[nlen - 1])
|
switch (name[nlen - 1])
|
{
|
{
|
case 's':
|
case 's':
|
fsize = FORCE_SHORT;
|
fsize = FORCE_SHORT;
|
break;
|
break;
|
case 'l':
|
case 'l':
|
fsize = FORCE_LONG;
|
fsize = FORCE_LONG;
|
break;
|
break;
|
}
|
}
|
name[nlen - 2] = 0;
|
name[nlen - 2] = 0;
|
}
|
}
|
|
|
/* Find the first opcode with the proper name. */
|
/* Find the first opcode with the proper name. */
|
opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name);
|
opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name);
|
if (opcode->op == NULL)
|
if (opcode->op == NULL)
|
{
|
{
|
as_bad (_("unknown opcode: %s"), name);
|
as_bad (_("unknown opcode: %s"), name);
|
return -1;
|
return -1;
|
}
|
}
|
|
|
save = input_line_pointer;
|
save = input_line_pointer;
|
input_line_pointer = op_end;
|
input_line_pointer = op_end;
|
while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack)))
|
while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack)))
|
{
|
{
|
opcode->op++;
|
opcode->op++;
|
if (opcode->op->name == NULL || strcmp (opcode->op->name, name))
|
if (opcode->op->name == NULL || strcmp (opcode->op->name, name))
|
{
|
{
|
as_bad (_("operands for opcode `%s' do not match any valid format"),
|
as_bad (_("operands for opcode `%s' do not match any valid format"),
|
name);
|
name);
|
return -1;
|
return -1;
|
}
|
}
|
}
|
}
|
input_line_pointer = save;
|
input_line_pointer = save;
|
|
|
insn = build_insn (opcode, myops);
|
insn = build_insn (opcode, myops);
|
|
|
/* Propagate multiply status. */
|
/* Propagate multiply status. */
|
if (insn != -1)
|
if (insn != -1)
|
{
|
{
|
if (is_parallel && prev_mul32_p)
|
if (is_parallel && prev_mul32_p)
|
cur_mul32_p = 1;
|
cur_mul32_p = 1;
|
else
|
else
|
{
|
{
|
prev_mul32_p = cur_mul32_p;
|
prev_mul32_p = cur_mul32_p;
|
cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0;
|
cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0;
|
}
|
}
|
}
|
}
|
|
|
/* Propagate left_kills_right status. */
|
/* Propagate left_kills_right status. */
|
if (insn != -1)
|
if (insn != -1)
|
{
|
{
|
prev_left_kills_right_p = cur_left_kills_right_p;
|
prev_left_kills_right_p = cur_left_kills_right_p;
|
|
|
if (opcode->op->flags_set & FLAG_LKR)
|
if (opcode->op->flags_set & FLAG_LKR)
|
{
|
{
|
cur_left_kills_right_p = 1;
|
cur_left_kills_right_p = 1;
|
|
|
if (strcmp (opcode->op->name, "mvtsys") == 0)
|
if (strcmp (opcode->op->name, "mvtsys") == 0)
|
{
|
{
|
/* Left kills right for only mvtsys only for
|
/* Left kills right for only mvtsys only for
|
PSW/PSWH/PSWL/flags target. */
|
PSW/PSWH/PSWL/flags target. */
|
if ((myops[0].X_op == O_register) &&
|
if ((myops[0].X_op == O_register) &&
|
((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */
|
((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */
|
(myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */
|
(myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */
|
(myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */
|
(myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */
|
(myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */
|
(myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */
|
(myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */
|
(myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */
|
(myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */
|
(myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */
|
(myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */
|
(myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */
|
(myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */
|
(myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */
|
(myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */
|
(myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */
|
(myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */
|
(myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */
|
(myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */
|
(myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */
|
{
|
{
|
cur_left_kills_right_p = 1;
|
cur_left_kills_right_p = 1;
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Other mvtsys target registers don't kill right
|
/* Other mvtsys target registers don't kill right
|
instruction. */
|
instruction. */
|
cur_left_kills_right_p = 0;
|
cur_left_kills_right_p = 0;
|
}
|
}
|
} /* mvtsys */
|
} /* mvtsys */
|
}
|
}
|
else
|
else
|
cur_left_kills_right_p = 0;
|
cur_left_kills_right_p = 0;
|
}
|
}
|
|
|
return insn;
|
return insn;
|
}
|
}
|
|
|
/* Called internally to handle all alignment needs. This takes care
|
/* Called internally to handle all alignment needs. This takes care
|
of eliding calls to frag_align if'n the cached current alignment
|
of eliding calls to frag_align if'n the cached current alignment
|
says we've already got it, as well as taking care of the auto-aligning
|
says we've already got it, as well as taking care of the auto-aligning
|
labels wrt code. */
|
labels wrt code. */
|
|
|
static void
|
static void
|
d30v_align (int n, char *pfill, symbolS *label)
|
d30v_align (int n, char *pfill, symbolS *label)
|
{
|
{
|
/* The front end is prone to changing segments out from under us
|
/* The front end is prone to changing segments out from under us
|
temporarily when -g is in effect. */
|
temporarily when -g is in effect. */
|
int switched_seg_p = (d30v_current_align_seg != now_seg);
|
int switched_seg_p = (d30v_current_align_seg != now_seg);
|
|
|
/* Do not assume that if 'd30v_current_align >= n' and
|
/* Do not assume that if 'd30v_current_align >= n' and
|
'! switched_seg_p' that it is safe to avoid performing
|
'! switched_seg_p' that it is safe to avoid performing
|
this alignment request. The alignment of the current frag
|
this alignment request. The alignment of the current frag
|
can be changed under our feet, for example by a .ascii
|
can be changed under our feet, for example by a .ascii
|
directive in the source code. cf testsuite/gas/d30v/reloc.s */
|
directive in the source code. cf testsuite/gas/d30v/reloc.s */
|
d30v_cleanup (FALSE);
|
d30v_cleanup (FALSE);
|
|
|
if (pfill == NULL)
|
if (pfill == NULL)
|
{
|
{
|
if (n > 2
|
if (n > 2
|
&& (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
|
&& (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
|
{
|
{
|
static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 };
|
static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 };
|
|
|
/* First, make sure we're on a four-byte boundary, in case
|
/* First, make sure we're on a four-byte boundary, in case
|
someone has been putting .byte values the text section. */
|
someone has been putting .byte values the text section. */
|
if (d30v_current_align < 2 || switched_seg_p)
|
if (d30v_current_align < 2 || switched_seg_p)
|
frag_align (2, 0, 0);
|
frag_align (2, 0, 0);
|
frag_align_pattern (n, nop, sizeof nop, 0);
|
frag_align_pattern (n, nop, sizeof nop, 0);
|
}
|
}
|
else
|
else
|
frag_align (n, 0, 0);
|
frag_align (n, 0, 0);
|
}
|
}
|
else
|
else
|
frag_align (n, *pfill, 0);
|
frag_align (n, *pfill, 0);
|
|
|
if (!switched_seg_p)
|
if (!switched_seg_p)
|
d30v_current_align = n;
|
d30v_current_align = n;
|
|
|
if (label != NULL)
|
if (label != NULL)
|
{
|
{
|
symbolS *sym;
|
symbolS *sym;
|
int label_seen = FALSE;
|
int label_seen = FALSE;
|
struct frag *old_frag;
|
struct frag *old_frag;
|
valueT old_value;
|
valueT old_value;
|
valueT new_value;
|
valueT new_value;
|
|
|
assert (S_GET_SEGMENT (label) == now_seg);
|
assert (S_GET_SEGMENT (label) == now_seg);
|
|
|
old_frag = symbol_get_frag (label);
|
old_frag = symbol_get_frag (label);
|
old_value = S_GET_VALUE (label);
|
old_value = S_GET_VALUE (label);
|
new_value = (valueT) frag_now_fix ();
|
new_value = (valueT) frag_now_fix ();
|
|
|
/* It is possible to have more than one label at a particular
|
/* It is possible to have more than one label at a particular
|
address, especially if debugging is enabled, so we must
|
address, especially if debugging is enabled, so we must
|
take care to adjust all the labels at this address in this
|
take care to adjust all the labels at this address in this
|
fragment. To save time we search from the end of the symbol
|
fragment. To save time we search from the end of the symbol
|
list, backwards, since the symbols we are interested in are
|
list, backwards, since the symbols we are interested in are
|
almost certainly the ones that were most recently added.
|
almost certainly the ones that were most recently added.
|
Also to save time we stop searching once we have seen at least
|
Also to save time we stop searching once we have seen at least
|
one matching label, and we encounter a label that is no longer
|
one matching label, and we encounter a label that is no longer
|
in the target fragment. Note, this search is guaranteed to
|
in the target fragment. Note, this search is guaranteed to
|
find at least one match when sym == label, so no special case
|
find at least one match when sym == label, so no special case
|
code is necessary. */
|
code is necessary. */
|
for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
|
for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
|
{
|
{
|
if (symbol_get_frag (sym) == old_frag
|
if (symbol_get_frag (sym) == old_frag
|
&& S_GET_VALUE (sym) == old_value)
|
&& S_GET_VALUE (sym) == old_value)
|
{
|
{
|
label_seen = TRUE;
|
label_seen = TRUE;
|
symbol_set_frag (sym, frag_now);
|
symbol_set_frag (sym, frag_now);
|
S_SET_VALUE (sym, new_value);
|
S_SET_VALUE (sym, new_value);
|
}
|
}
|
else if (label_seen && symbol_get_frag (sym) != old_frag)
|
else if (label_seen && symbol_get_frag (sym) != old_frag)
|
break;
|
break;
|
}
|
}
|
}
|
}
|
|
|
record_alignment (now_seg, n);
|
record_alignment (now_seg, n);
|
}
|
}
|
|
|
/* This is the main entry point for the machine-dependent assembler.
|
/* This is the main entry point for the machine-dependent assembler.
|
STR points to a machine-dependent instruction. This function is
|
STR points to a machine-dependent instruction. This function is
|
supposed to emit the frags/bytes it assembles to. For the D30V, it
|
supposed to emit the frags/bytes it assembles to. For the D30V, it
|
mostly handles the special VLIW parsing and packing and leaves the
|
mostly handles the special VLIW parsing and packing and leaves the
|
difficult stuff to do_assemble (). */
|
difficult stuff to do_assemble (). */
|
|
|
static long long prev_insn = -1;
|
static long long prev_insn = -1;
|
static struct d30v_insn prev_opcode;
|
static struct d30v_insn prev_opcode;
|
static subsegT prev_subseg;
|
static subsegT prev_subseg;
|
static segT prev_seg = 0;
|
static segT prev_seg = 0;
|
|
|
void
|
void
|
md_assemble (char *str)
|
md_assemble (char *str)
|
{
|
{
|
struct d30v_insn opcode;
|
struct d30v_insn opcode;
|
long long insn;
|
long long insn;
|
/* Execution type; parallel, etc. */
|
/* Execution type; parallel, etc. */
|
exec_type_enum extype = EXEC_UNKNOWN;
|
exec_type_enum extype = EXEC_UNKNOWN;
|
/* Saved extype. Used for multiline instructions. */
|
/* Saved extype. Used for multiline instructions. */
|
static exec_type_enum etype = EXEC_UNKNOWN;
|
static exec_type_enum etype = EXEC_UNKNOWN;
|
char *str2;
|
char *str2;
|
|
|
if ((prev_insn != -1) && prev_seg
|
if ((prev_insn != -1) && prev_seg
|
&& ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
|
&& ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
|
d30v_cleanup (FALSE);
|
d30v_cleanup (FALSE);
|
|
|
if (d30v_current_align < 3)
|
if (d30v_current_align < 3)
|
d30v_align (3, NULL, d30v_last_label);
|
d30v_align (3, NULL, d30v_last_label);
|
else if (d30v_current_align > 3)
|
else if (d30v_current_align > 3)
|
d30v_current_align = 3;
|
d30v_current_align = 3;
|
d30v_last_label = NULL;
|
d30v_last_label = NULL;
|
|
|
flag_explicitly_parallel = 0;
|
flag_explicitly_parallel = 0;
|
flag_xp_state = 0;
|
flag_xp_state = 0;
|
if (etype == EXEC_UNKNOWN)
|
if (etype == EXEC_UNKNOWN)
|
{
|
{
|
/* Look for the special multiple instruction separators. */
|
/* Look for the special multiple instruction separators. */
|
str2 = strstr (str, "||");
|
str2 = strstr (str, "||");
|
if (str2)
|
if (str2)
|
{
|
{
|
extype = EXEC_PARALLEL;
|
extype = EXEC_PARALLEL;
|
flag_xp_state = 1;
|
flag_xp_state = 1;
|
}
|
}
|
else
|
else
|
{
|
{
|
str2 = strstr (str, "->");
|
str2 = strstr (str, "->");
|
if (str2)
|
if (str2)
|
extype = EXEC_SEQ;
|
extype = EXEC_SEQ;
|
else
|
else
|
{
|
{
|
str2 = strstr (str, "<-");
|
str2 = strstr (str, "<-");
|
if (str2)
|
if (str2)
|
extype = EXEC_REVSEQ;
|
extype = EXEC_REVSEQ;
|
}
|
}
|
}
|
}
|
|
|
/* STR2 points to the separator, if one. */
|
/* STR2 points to the separator, if one. */
|
if (str2)
|
if (str2)
|
{
|
{
|
*str2 = 0;
|
*str2 = 0;
|
|
|
/* If two instructions are present and we already have one saved,
|
/* If two instructions are present and we already have one saved,
|
then first write it out. */
|
then first write it out. */
|
d30v_cleanup (FALSE);
|
d30v_cleanup (FALSE);
|
|
|
/* Assemble first instruction and save it. */
|
/* Assemble first instruction and save it. */
|
prev_insn = do_assemble (str, &prev_opcode, 1, 0);
|
prev_insn = do_assemble (str, &prev_opcode, 1, 0);
|
if (prev_insn == -1)
|
if (prev_insn == -1)
|
as_bad (_("Cannot assemble instruction"));
|
as_bad (_("Cannot assemble instruction"));
|
if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG)
|
if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG)
|
as_bad (_("First opcode is long. Unable to mix instructions as specified."));
|
as_bad (_("First opcode is long. Unable to mix instructions as specified."));
|
fixups = fixups->next;
|
fixups = fixups->next;
|
str = str2 + 2;
|
str = str2 + 2;
|
prev_seg = now_seg;
|
prev_seg = now_seg;
|
prev_subseg = now_subseg;
|
prev_subseg = now_subseg;
|
}
|
}
|
}
|
}
|
|
|
insn = do_assemble (str, &opcode,
|
insn = do_assemble (str, &opcode,
|
(extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN),
|
(extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN),
|
extype == EXEC_PARALLEL);
|
extype == EXEC_PARALLEL);
|
if (insn == -1)
|
if (insn == -1)
|
{
|
{
|
if (extype != EXEC_UNKNOWN)
|
if (extype != EXEC_UNKNOWN)
|
etype = extype;
|
etype = extype;
|
as_bad (_("Cannot assemble instruction"));
|
as_bad (_("Cannot assemble instruction"));
|
return;
|
return;
|
}
|
}
|
|
|
if (etype != EXEC_UNKNOWN)
|
if (etype != EXEC_UNKNOWN)
|
{
|
{
|
extype = etype;
|
extype = etype;
|
etype = EXEC_UNKNOWN;
|
etype = EXEC_UNKNOWN;
|
}
|
}
|
|
|
/* Word multiply instructions must not be followed by either a load or a
|
/* Word multiply instructions must not be followed by either a load or a
|
16-bit multiply instruction in the next cycle. */
|
16-bit multiply instruction in the next cycle. */
|
if ( (extype != EXEC_REVSEQ)
|
if ( (extype != EXEC_REVSEQ)
|
&& prev_mul32_p
|
&& prev_mul32_p
|
&& (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
|
&& (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
|
{
|
{
|
/* However, load and multiply should able to be combined in a parallel
|
/* However, load and multiply should able to be combined in a parallel
|
operation, so check for that first. */
|
operation, so check for that first. */
|
if (prev_insn != -1
|
if (prev_insn != -1
|
&& (opcode.op->flags_used & FLAG_MEM)
|
&& (opcode.op->flags_used & FLAG_MEM)
|
&& opcode.form->form < LONG
|
&& opcode.form->form < LONG
|
&& (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
|
&& (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
|
&& parallel_ok (&prev_opcode, (long) prev_insn,
|
&& parallel_ok (&prev_opcode, (long) prev_insn,
|
&opcode, (long) insn, extype)
|
&opcode, (long) insn, extype)
|
&& write_2_short (&prev_opcode, (long) prev_insn,
|
&& write_2_short (&prev_opcode, (long) prev_insn,
|
&opcode, (long) insn, extype, fixups) == 0)
|
&opcode, (long) insn, extype, fixups) == 0)
|
{
|
{
|
/* No instructions saved. */
|
/* No instructions saved. */
|
prev_insn = -1;
|
prev_insn = -1;
|
return;
|
return;
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Can't parallelize, flush previous instruction and emit a
|
/* Can't parallelize, flush previous instruction and emit a
|
word of NOPS, unless the previous instruction is a NOP,
|
word of NOPS, unless the previous instruction is a NOP,
|
in which case just flush it, as this will generate a word
|
in which case just flush it, as this will generate a word
|
of NOPs for us. */
|
of NOPs for us. */
|
|
|
if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
|
if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
|
d30v_cleanup (FALSE);
|
d30v_cleanup (FALSE);
|
else
|
else
|
{
|
{
|
char *f;
|
char *f;
|
|
|
if (prev_insn != -1)
|
if (prev_insn != -1)
|
d30v_cleanup (TRUE);
|
d30v_cleanup (TRUE);
|
else
|
else
|
{
|
{
|
f = frag_more (8);
|
f = frag_more (8);
|
d30v_number_to_chars (f, NOP2, 8);
|
d30v_number_to_chars (f, NOP2, 8);
|
|
|
if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
|
if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
|
{
|
{
|
if (opcode.op->flags_used & FLAG_MEM)
|
if (opcode.op->flags_used & FLAG_MEM)
|
as_warn (_("word of NOPs added between word multiply and load"));
|
as_warn (_("word of NOPs added between word multiply and load"));
|
else
|
else
|
as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
|
as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
extype = EXEC_UNKNOWN;
|
extype = EXEC_UNKNOWN;
|
}
|
}
|
}
|
}
|
else if ( (extype == EXEC_REVSEQ)
|
else if ( (extype == EXEC_REVSEQ)
|
&& cur_mul32_p
|
&& cur_mul32_p
|
&& (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
|
&& (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
|
{
|
{
|
/* Can't parallelize, flush current instruction and add a
|
/* Can't parallelize, flush current instruction and add a
|
sequential NOP. */
|
sequential NOP. */
|
write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
|
write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
|
|
|
/* Make the previous instruction the current one. */
|
/* Make the previous instruction the current one. */
|
extype = EXEC_UNKNOWN;
|
extype = EXEC_UNKNOWN;
|
insn = prev_insn;
|
insn = prev_insn;
|
now_seg = prev_seg;
|
now_seg = prev_seg;
|
now_subseg = prev_subseg;
|
now_subseg = prev_subseg;
|
prev_insn = -1;
|
prev_insn = -1;
|
cur_mul32_p = prev_mul32_p;
|
cur_mul32_p = prev_mul32_p;
|
prev_mul32_p = 0;
|
prev_mul32_p = 0;
|
memcpy (&opcode, &prev_opcode, sizeof (prev_opcode));
|
memcpy (&opcode, &prev_opcode, sizeof (prev_opcode));
|
}
|
}
|
|
|
/* If this is a long instruction, write it and any previous short
|
/* If this is a long instruction, write it and any previous short
|
instruction. */
|
instruction. */
|
if (opcode.form->form >= LONG)
|
if (opcode.form->form >= LONG)
|
{
|
{
|
if (extype != EXEC_UNKNOWN)
|
if (extype != EXEC_UNKNOWN)
|
as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
|
as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
|
d30v_cleanup (FALSE);
|
d30v_cleanup (FALSE);
|
write_long (&opcode, insn, fixups);
|
write_long (&opcode, insn, fixups);
|
prev_insn = -1;
|
prev_insn = -1;
|
}
|
}
|
else if ((prev_insn != -1)
|
else if ((prev_insn != -1)
|
&& (write_2_short
|
&& (write_2_short
|
(&prev_opcode, (long) prev_insn, &opcode,
|
(&prev_opcode, (long) prev_insn, &opcode,
|
(long) insn, extype, fixups) == 0))
|
(long) insn, extype, fixups) == 0))
|
{
|
{
|
/* No instructions saved. */
|
/* No instructions saved. */
|
prev_insn = -1;
|
prev_insn = -1;
|
}
|
}
|
else
|
else
|
{
|
{
|
if (extype != EXEC_UNKNOWN)
|
if (extype != EXEC_UNKNOWN)
|
as_bad (_("Unable to mix instructions as specified"));
|
as_bad (_("Unable to mix instructions as specified"));
|
|
|
/* Save off last instruction so it may be packed on next pass. */
|
/* Save off last instruction so it may be packed on next pass. */
|
memcpy (&prev_opcode, &opcode, sizeof (prev_opcode));
|
memcpy (&prev_opcode, &opcode, sizeof (prev_opcode));
|
prev_insn = insn;
|
prev_insn = insn;
|
prev_seg = now_seg;
|
prev_seg = now_seg;
|
prev_subseg = now_subseg;
|
prev_subseg = now_subseg;
|
fixups = fixups->next;
|
fixups = fixups->next;
|
prev_mul32_p = cur_mul32_p;
|
prev_mul32_p = cur_mul32_p;
|
}
|
}
|
}
|
}
|
|
|
/* If while processing a fixup, a reloc really needs to be created,
|
/* If while processing a fixup, a reloc really needs to be created,
|
then it is done here. */
|
then it is done here. */
|
|
|
arelent *
|
arelent *
|
tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
|
tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
|
{
|
{
|
arelent *reloc;
|
arelent *reloc;
|
reloc = xmalloc (sizeof (arelent));
|
reloc = xmalloc (sizeof (arelent));
|
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
|
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
|
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
|
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
|
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
|
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
|
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
|
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
|
if (reloc->howto == NULL)
|
if (reloc->howto == NULL)
|
{
|
{
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
_("reloc %d not supported by object file format"),
|
_("reloc %d not supported by object file format"),
|
(int) fixp->fx_r_type);
|
(int) fixp->fx_r_type);
|
return NULL;
|
return NULL;
|
}
|
}
|
|
|
reloc->addend = 0;
|
reloc->addend = 0;
|
return reloc;
|
return reloc;
|
}
|
}
|
|
|
int
|
int
|
md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
|
md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
|
asection *seg ATTRIBUTE_UNUSED)
|
asection *seg ATTRIBUTE_UNUSED)
|
{
|
{
|
abort ();
|
abort ();
|
return 0;
|
return 0;
|
}
|
}
|
|
|
long
|
long
|
md_pcrel_from_section (fixS *fixp, segT sec)
|
md_pcrel_from_section (fixS *fixp, segT sec)
|
{
|
{
|
if (fixp->fx_addsy != (symbolS *) NULL
|
if (fixp->fx_addsy != (symbolS *) NULL
|
&& (!S_IS_DEFINED (fixp->fx_addsy)
|
&& (!S_IS_DEFINED (fixp->fx_addsy)
|
|| (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
|
|| (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
|
return 0;
|
return 0;
|
return fixp->fx_frag->fr_address + fixp->fx_where;
|
return fixp->fx_frag->fr_address + fixp->fx_where;
|
}
|
}
|
|
|
/* Called after the assembler has finished parsing the input file or
|
/* Called after the assembler has finished parsing the input file or
|
after a label is defined. Because the D30V assembler sometimes
|
after a label is defined. Because the D30V assembler sometimes
|
saves short instructions to see if it can package them with the
|
saves short instructions to see if it can package them with the
|
next instruction, there may be a short instruction that still needs
|
next instruction, there may be a short instruction that still needs
|
written. */
|
written. */
|
|
|
int
|
int
|
d30v_cleanup (int use_sequential)
|
d30v_cleanup (int use_sequential)
|
{
|
{
|
segT seg;
|
segT seg;
|
subsegT subseg;
|
subsegT subseg;
|
|
|
if (prev_insn != -1)
|
if (prev_insn != -1)
|
{
|
{
|
seg = now_seg;
|
seg = now_seg;
|
subseg = now_subseg;
|
subseg = now_subseg;
|
subseg_set (prev_seg, prev_subseg);
|
subseg_set (prev_seg, prev_subseg);
|
write_1_short (&prev_opcode, (long) prev_insn, fixups->next,
|
write_1_short (&prev_opcode, (long) prev_insn, fixups->next,
|
use_sequential);
|
use_sequential);
|
subseg_set (seg, subseg);
|
subseg_set (seg, subseg);
|
prev_insn = -1;
|
prev_insn = -1;
|
if (use_sequential)
|
if (use_sequential)
|
prev_mul32_p = FALSE;
|
prev_mul32_p = FALSE;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
/* This function is called at the start of every line. It checks to
|
/* This function is called at the start of every line. It checks to
|
see if the first character is a '.', which indicates the start of a
|
see if the first character is a '.', which indicates the start of a
|
pseudo-op. If it is, then write out any unwritten instructions. */
|
pseudo-op. If it is, then write out any unwritten instructions. */
|
|
|
void
|
void
|
d30v_start_line (void)
|
d30v_start_line (void)
|
{
|
{
|
char *c = input_line_pointer;
|
char *c = input_line_pointer;
|
|
|
while (ISSPACE (*c))
|
while (ISSPACE (*c))
|
c++;
|
c++;
|
|
|
if (*c == '.')
|
if (*c == '.')
|
d30v_cleanup (FALSE);
|
d30v_cleanup (FALSE);
|
}
|
}
|
|
|
static void
|
static void
|
check_size (long value, int bits, char *file, int line)
|
check_size (long value, int bits, char *file, int line)
|
{
|
{
|
int tmp, max;
|
int tmp, max;
|
|
|
if (value < 0)
|
if (value < 0)
|
tmp = ~value;
|
tmp = ~value;
|
else
|
else
|
tmp = value;
|
tmp = value;
|
|
|
max = (1 << (bits - 1)) - 1;
|
max = (1 << (bits - 1)) - 1;
|
|
|
if (tmp > max)
|
if (tmp > max)
|
as_bad_where (file, line, _("value too large to fit in %d bits"), bits);
|
as_bad_where (file, line, _("value too large to fit in %d bits"), bits);
|
}
|
}
|
|
|
/* d30v_frob_label() is called when after a label is recognized. */
|
/* d30v_frob_label() is called when after a label is recognized. */
|
|
|
void
|
void
|
d30v_frob_label (symbolS *lab)
|
d30v_frob_label (symbolS *lab)
|
{
|
{
|
/* Emit any pending instructions. */
|
/* Emit any pending instructions. */
|
d30v_cleanup (FALSE);
|
d30v_cleanup (FALSE);
|
|
|
/* Update the label's address with the current output pointer. */
|
/* Update the label's address with the current output pointer. */
|
symbol_set_frag (lab, frag_now);
|
symbol_set_frag (lab, frag_now);
|
S_SET_VALUE (lab, (valueT) frag_now_fix ());
|
S_SET_VALUE (lab, (valueT) frag_now_fix ());
|
|
|
/* Record this label for future adjustment after we find out what
|
/* Record this label for future adjustment after we find out what
|
kind of data it references, and the required alignment therewith. */
|
kind of data it references, and the required alignment therewith. */
|
d30v_last_label = lab;
|
d30v_last_label = lab;
|
}
|
}
|
|
|
/* Hook into cons for capturing alignment changes. */
|
/* Hook into cons for capturing alignment changes. */
|
|
|
void
|
void
|
d30v_cons_align (int size)
|
d30v_cons_align (int size)
|
{
|
{
|
int log_size;
|
int log_size;
|
|
|
log_size = 0;
|
log_size = 0;
|
while ((size >>= 1) != 0)
|
while ((size >>= 1) != 0)
|
++log_size;
|
++log_size;
|
|
|
if (d30v_current_align < log_size)
|
if (d30v_current_align < log_size)
|
d30v_align (log_size, (char *) NULL, NULL);
|
d30v_align (log_size, (char *) NULL, NULL);
|
else if (d30v_current_align > log_size)
|
else if (d30v_current_align > log_size)
|
d30v_current_align = log_size;
|
d30v_current_align = log_size;
|
d30v_last_label = NULL;
|
d30v_last_label = NULL;
|
}
|
}
|
|
|
void
|
void
|
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
|
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
|
{
|
{
|
char *where;
|
char *where;
|
unsigned long insn, insn2;
|
unsigned long insn, insn2;
|
long value = *valP;
|
long value = *valP;
|
|
|
if (fixP->fx_addsy == (symbolS *) NULL)
|
if (fixP->fx_addsy == (symbolS *) NULL)
|
fixP->fx_done = 1;
|
fixP->fx_done = 1;
|
|
|
/* We don't support subtracting a symbol. */
|
/* We don't support subtracting a symbol. */
|
if (fixP->fx_subsy != (symbolS *) NULL)
|
if (fixP->fx_subsy != (symbolS *) NULL)
|
as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
|
as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
|
|
|
/* Fetch the instruction, insert the fully resolved operand
|
/* Fetch the instruction, insert the fully resolved operand
|
value, and stuff the instruction back again. */
|
value, and stuff the instruction back again. */
|
where = fixP->fx_frag->fr_literal + fixP->fx_where;
|
where = fixP->fx_frag->fr_literal + fixP->fx_where;
|
insn = bfd_getb32 ((unsigned char *) where);
|
insn = bfd_getb32 ((unsigned char *) where);
|
|
|
switch (fixP->fx_r_type)
|
switch (fixP->fx_r_type)
|
{
|
{
|
case BFD_RELOC_8: /* Check for a bad .byte directive. */
|
case BFD_RELOC_8: /* Check for a bad .byte directive. */
|
if (fixP->fx_addsy != NULL)
|
if (fixP->fx_addsy != NULL)
|
as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
|
as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
|
fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
|
fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
|
else if (((unsigned)value) > 0xff)
|
else if (((unsigned)value) > 0xff)
|
as_bad (_("line %d: unable to place value %lx into a byte"),
|
as_bad (_("line %d: unable to place value %lx into a byte"),
|
fixP->fx_line, value);
|
fixP->fx_line, value);
|
else
|
else
|
*(unsigned char *) where = value;
|
*(unsigned char *) where = value;
|
break;
|
break;
|
|
|
case BFD_RELOC_16: /* Check for a bad .short directive. */
|
case BFD_RELOC_16: /* Check for a bad .short directive. */
|
if (fixP->fx_addsy != NULL)
|
if (fixP->fx_addsy != NULL)
|
as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
|
as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
|
fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
|
fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
|
else if (((unsigned)value) > 0xffff)
|
else if (((unsigned)value) > 0xffff)
|
as_bad (_("line %d: unable to place value %lx into a short"),
|
as_bad (_("line %d: unable to place value %lx into a short"),
|
fixP->fx_line, value);
|
fixP->fx_line, value);
|
else
|
else
|
bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
|
bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
|
break;
|
break;
|
|
|
case BFD_RELOC_64: /* Check for a bad .quad directive. */
|
case BFD_RELOC_64: /* Check for a bad .quad directive. */
|
if (fixP->fx_addsy != NULL)
|
if (fixP->fx_addsy != NULL)
|
as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
|
as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
|
fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
|
fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
|
else
|
else
|
{
|
{
|
bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
|
bfd_putb32 (0, ((unsigned char *) where) + 4);
|
bfd_putb32 (0, ((unsigned char *) where) + 4);
|
}
|
}
|
break;
|
break;
|
|
|
case BFD_RELOC_D30V_6:
|
case BFD_RELOC_D30V_6:
|
check_size (value, 6, fixP->fx_file, fixP->fx_line);
|
check_size (value, 6, fixP->fx_file, fixP->fx_line);
|
insn |= value & 0x3F;
|
insn |= value & 0x3F;
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
break;
|
break;
|
|
|
case BFD_RELOC_D30V_9_PCREL:
|
case BFD_RELOC_D30V_9_PCREL:
|
if (fixP->fx_where & 0x7)
|
if (fixP->fx_where & 0x7)
|
{
|
{
|
if (fixP->fx_done)
|
if (fixP->fx_done)
|
value += 4;
|
value += 4;
|
else
|
else
|
fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R;
|
fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R;
|
}
|
}
|
check_size (value, 9, fixP->fx_file, fixP->fx_line);
|
check_size (value, 9, fixP->fx_file, fixP->fx_line);
|
insn |= ((value >> 3) & 0x3F) << 12;
|
insn |= ((value >> 3) & 0x3F) << 12;
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
break;
|
break;
|
|
|
case BFD_RELOC_D30V_15:
|
case BFD_RELOC_D30V_15:
|
check_size (value, 15, fixP->fx_file, fixP->fx_line);
|
check_size (value, 15, fixP->fx_file, fixP->fx_line);
|
insn |= (value >> 3) & 0xFFF;
|
insn |= (value >> 3) & 0xFFF;
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
break;
|
break;
|
|
|
case BFD_RELOC_D30V_15_PCREL:
|
case BFD_RELOC_D30V_15_PCREL:
|
if (fixP->fx_where & 0x7)
|
if (fixP->fx_where & 0x7)
|
{
|
{
|
if (fixP->fx_done)
|
if (fixP->fx_done)
|
value += 4;
|
value += 4;
|
else
|
else
|
fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R;
|
fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R;
|
}
|
}
|
check_size (value, 15, fixP->fx_file, fixP->fx_line);
|
check_size (value, 15, fixP->fx_file, fixP->fx_line);
|
insn |= (value >> 3) & 0xFFF;
|
insn |= (value >> 3) & 0xFFF;
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
break;
|
break;
|
|
|
case BFD_RELOC_D30V_21:
|
case BFD_RELOC_D30V_21:
|
check_size (value, 21, fixP->fx_file, fixP->fx_line);
|
check_size (value, 21, fixP->fx_file, fixP->fx_line);
|
insn |= (value >> 3) & 0x3FFFF;
|
insn |= (value >> 3) & 0x3FFFF;
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
break;
|
break;
|
|
|
case BFD_RELOC_D30V_21_PCREL:
|
case BFD_RELOC_D30V_21_PCREL:
|
if (fixP->fx_where & 0x7)
|
if (fixP->fx_where & 0x7)
|
{
|
{
|
if (fixP->fx_done)
|
if (fixP->fx_done)
|
value += 4;
|
value += 4;
|
else
|
else
|
fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R;
|
fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R;
|
}
|
}
|
check_size (value, 21, fixP->fx_file, fixP->fx_line);
|
check_size (value, 21, fixP->fx_file, fixP->fx_line);
|
insn |= (value >> 3) & 0x3FFFF;
|
insn |= (value >> 3) & 0x3FFFF;
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
break;
|
break;
|
|
|
case BFD_RELOC_D30V_32:
|
case BFD_RELOC_D30V_32:
|
insn2 = bfd_getb32 ((unsigned char *) where + 4);
|
insn2 = bfd_getb32 ((unsigned char *) where + 4);
|
insn |= (value >> 26) & 0x3F; /* Top 6 bits. */
|
insn |= (value >> 26) & 0x3F; /* Top 6 bits. */
|
insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */
|
insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */
|
insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */
|
insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
|
bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
|
break;
|
break;
|
|
|
case BFD_RELOC_D30V_32_PCREL:
|
case BFD_RELOC_D30V_32_PCREL:
|
insn2 = bfd_getb32 ((unsigned char *) where + 4);
|
insn2 = bfd_getb32 ((unsigned char *) where + 4);
|
insn |= (value >> 26) & 0x3F; /* Top 6 bits. */
|
insn |= (value >> 26) & 0x3F; /* Top 6 bits. */
|
insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */
|
insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */
|
insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */
|
insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
|
bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
|
break;
|
break;
|
|
|
case BFD_RELOC_32:
|
case BFD_RELOC_32:
|
bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
|
bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
|
break;
|
break;
|
|
|
default:
|
default:
|
as_bad (_("line %d: unknown relocation type: 0x%x"),
|
as_bad (_("line %d: unknown relocation type: 0x%x"),
|
fixP->fx_line, fixP->fx_r_type);
|
fixP->fx_line, fixP->fx_r_type);
|
}
|
}
|
}
|
}
|
|
|
/* Handle the .align pseudo-op. This aligns to a power of two. We
|
/* Handle the .align pseudo-op. This aligns to a power of two. We
|
hook here to latch the current alignment. */
|
hook here to latch the current alignment. */
|
|
|
static void
|
static void
|
s_d30v_align (int ignore ATTRIBUTE_UNUSED)
|
s_d30v_align (int ignore ATTRIBUTE_UNUSED)
|
{
|
{
|
int align;
|
int align;
|
char fill, *pfill = NULL;
|
char fill, *pfill = NULL;
|
long max_alignment = 15;
|
long max_alignment = 15;
|
|
|
align = get_absolute_expression ();
|
align = get_absolute_expression ();
|
if (align > max_alignment)
|
if (align > max_alignment)
|
{
|
{
|
align = max_alignment;
|
align = max_alignment;
|
as_warn (_("Alignment too large: %d assumed"), align);
|
as_warn (_("Alignment too large: %d assumed"), align);
|
}
|
}
|
else if (align < 0)
|
else if (align < 0)
|
{
|
{
|
as_warn (_("Alignment negative: 0 assumed"));
|
as_warn (_("Alignment negative: 0 assumed"));
|
align = 0;
|
align = 0;
|
}
|
}
|
|
|
if (*input_line_pointer == ',')
|
if (*input_line_pointer == ',')
|
{
|
{
|
input_line_pointer++;
|
input_line_pointer++;
|
fill = get_absolute_expression ();
|
fill = get_absolute_expression ();
|
pfill = &fill;
|
pfill = &fill;
|
}
|
}
|
|
|
d30v_last_label = NULL;
|
d30v_last_label = NULL;
|
d30v_align (align, pfill, NULL);
|
d30v_align (align, pfill, NULL);
|
|
|
demand_empty_rest_of_line ();
|
demand_empty_rest_of_line ();
|
}
|
}
|
|
|
/* Handle the .text pseudo-op. This is like the usual one, but it
|
/* Handle the .text pseudo-op. This is like the usual one, but it
|
clears the saved last label and resets known alignment. */
|
clears the saved last label and resets known alignment. */
|
|
|
static void
|
static void
|
s_d30v_text (int i)
|
s_d30v_text (int i)
|
|
|
{
|
{
|
s_text (i);
|
s_text (i);
|
d30v_last_label = NULL;
|
d30v_last_label = NULL;
|
d30v_current_align = 0;
|
d30v_current_align = 0;
|
d30v_current_align_seg = now_seg;
|
d30v_current_align_seg = now_seg;
|
}
|
}
|
|
|
/* Handle the .data pseudo-op. This is like the usual one, but it
|
/* Handle the .data pseudo-op. This is like the usual one, but it
|
clears the saved last label and resets known alignment. */
|
clears the saved last label and resets known alignment. */
|
|
|
static void
|
static void
|
s_d30v_data (int i)
|
s_d30v_data (int i)
|
{
|
{
|
s_data (i);
|
s_data (i);
|
d30v_last_label = NULL;
|
d30v_last_label = NULL;
|
d30v_current_align = 0;
|
d30v_current_align = 0;
|
d30v_current_align_seg = now_seg;
|
d30v_current_align_seg = now_seg;
|
}
|
}
|
|
|
/* Handle the .section pseudo-op. This is like the usual one, but it
|
/* Handle the .section pseudo-op. This is like the usual one, but it
|
clears the saved last label and resets known alignment. */
|
clears the saved last label and resets known alignment. */
|
|
|
static void
|
static void
|
s_d30v_section (int ignore)
|
s_d30v_section (int ignore)
|
{
|
{
|
obj_elf_section (ignore);
|
obj_elf_section (ignore);
|
d30v_last_label = NULL;
|
d30v_last_label = NULL;
|
d30v_current_align = 0;
|
d30v_current_align = 0;
|
d30v_current_align_seg = now_seg;
|
d30v_current_align_seg = now_seg;
|
}
|
}
|
|
|
/* The target specific pseudo-ops which we support. */
|
/* The target specific pseudo-ops which we support. */
|
const pseudo_typeS md_pseudo_table[] =
|
const pseudo_typeS md_pseudo_table[] =
|
{
|
{
|
{ "word", cons, 4 },
|
{ "word", cons, 4 },
|
{ "hword", cons, 2 },
|
{ "hword", cons, 2 },
|
{ "align", s_d30v_align, 0 },
|
{ "align", s_d30v_align, 0 },
|
{ "text", s_d30v_text, 0 },
|
{ "text", s_d30v_text, 0 },
|
{ "data", s_d30v_data, 0 },
|
{ "data", s_d30v_data, 0 },
|
{ "section", s_d30v_section, 0 },
|
{ "section", s_d30v_section, 0 },
|
{ "section.s", s_d30v_section, 0 },
|
{ "section.s", s_d30v_section, 0 },
|
{ "sect", s_d30v_section, 0 },
|
{ "sect", s_d30v_section, 0 },
|
{ "sect.s", s_d30v_section, 0 },
|
{ "sect.s", s_d30v_section, 0 },
|
{ NULL, NULL, 0 }
|
{ NULL, NULL, 0 }
|
};
|
};
|
|
|
|
|
