/* tc-m32r.c -- Assembler for the Renesas M32R.
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/* tc-m32r.c -- Assembler for the Renesas M32R.
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
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2006, 2007 Free Software Foundation, Inc.
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2006, 2007 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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GAS is distributed in the hope that it will be useful,
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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Boston, MA 02110-1301, USA. */
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#include "as.h"
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#include "as.h"
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#include "safe-ctype.h"
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#include "safe-ctype.h"
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#include "subsegs.h"
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#include "subsegs.h"
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#include "symcat.h"
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#include "symcat.h"
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#include "opcodes/m32r-desc.h"
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#include "opcodes/m32r-desc.h"
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#include "opcodes/m32r-opc.h"
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#include "opcodes/m32r-opc.h"
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#include "cgen.h"
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#include "cgen.h"
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#include "elf/m32r.h"
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#include "elf/m32r.h"
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/* Linked list of symbols that are debugging symbols to be defined as the
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/* Linked list of symbols that are debugging symbols to be defined as the
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beginning of the current instruction. */
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beginning of the current instruction. */
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typedef struct sym_link
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typedef struct sym_link
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{
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{
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struct sym_link *next;
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struct sym_link *next;
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symbolS *symbol;
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symbolS *symbol;
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} sym_linkS;
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} sym_linkS;
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static sym_linkS *debug_sym_link = (sym_linkS *) 0;
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static sym_linkS *debug_sym_link = (sym_linkS *) 0;
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/* Structure to hold all of the different components describing
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/* Structure to hold all of the different components describing
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an individual instruction. */
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an individual instruction. */
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typedef struct
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typedef struct
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{
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{
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const CGEN_INSN *insn;
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const CGEN_INSN *insn;
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const CGEN_INSN *orig_insn;
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const CGEN_INSN *orig_insn;
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CGEN_FIELDS fields;
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CGEN_FIELDS fields;
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#if CGEN_INT_INSN_P
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#if CGEN_INT_INSN_P
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CGEN_INSN_INT buffer[1];
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CGEN_INSN_INT buffer[1];
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#define INSN_VALUE(buf) (*(buf))
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#define INSN_VALUE(buf) (*(buf))
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#else
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#else
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unsigned char buffer[CGEN_MAX_INSN_SIZE];
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unsigned char buffer[CGEN_MAX_INSN_SIZE];
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#define INSN_VALUE(buf) (buf)
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#define INSN_VALUE(buf) (buf)
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#endif
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#endif
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char *addr;
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char *addr;
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fragS *frag;
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fragS *frag;
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int num_fixups;
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int num_fixups;
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fixS *fixups[GAS_CGEN_MAX_FIXUPS];
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fixS *fixups[GAS_CGEN_MAX_FIXUPS];
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int indices[MAX_OPERAND_INSTANCES];
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int indices[MAX_OPERAND_INSTANCES];
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sym_linkS *debug_sym_link;
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sym_linkS *debug_sym_link;
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}
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}
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m32r_insn;
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m32r_insn;
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/* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
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/* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
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boundary (i.e. was the first of two 16 bit insns). */
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boundary (i.e. was the first of two 16 bit insns). */
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static m32r_insn prev_insn;
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static m32r_insn prev_insn;
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/* Non-zero if we've seen a relaxable insn since the last 32 bit
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/* Non-zero if we've seen a relaxable insn since the last 32 bit
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alignment request. */
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alignment request. */
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static int seen_relaxable_p = 0;
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static int seen_relaxable_p = 0;
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/* Non-zero if we are generating PIC code. */
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/* Non-zero if we are generating PIC code. */
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int pic_code;
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int pic_code;
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/* Non-zero if -relax specified, in which case sufficient relocs are output
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/* Non-zero if -relax specified, in which case sufficient relocs are output
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for the linker to do relaxing.
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for the linker to do relaxing.
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We do simple forms of relaxing internally, but they are always done.
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We do simple forms of relaxing internally, but they are always done.
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This flag does not apply to them. */
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This flag does not apply to them. */
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static int m32r_relax;
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static int m32r_relax;
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/* Non-zero if warn when a high/shigh reloc has no matching low reloc.
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/* Non-zero if warn when a high/shigh reloc has no matching low reloc.
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Each high/shigh reloc must be paired with it's low cousin in order to
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Each high/shigh reloc must be paired with it's low cousin in order to
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properly calculate the addend in a relocatable link (since there is a
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properly calculate the addend in a relocatable link (since there is a
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potential carry from the low to the high/shigh).
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potential carry from the low to the high/shigh).
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This option is off by default though for user-written assembler code it
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This option is off by default though for user-written assembler code it
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might make sense to make the default be on (i.e. have gcc pass a flag
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might make sense to make the default be on (i.e. have gcc pass a flag
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to turn it off). This warning must not be on for GCC created code as
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to turn it off). This warning must not be on for GCC created code as
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optimization may delete the low but not the high/shigh (at least we
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optimization may delete the low but not the high/shigh (at least we
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shouldn't assume or require it to). */
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shouldn't assume or require it to). */
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static int warn_unmatched_high = 0;
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static int warn_unmatched_high = 0;
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/* 1 if -m32rx has been specified, in which case support for
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/* 1 if -m32rx has been specified, in which case support for
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the extended M32RX instruction set should be enabled.
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the extended M32RX instruction set should be enabled.
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2 if -m32r2 has been specified, in which case support for
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2 if -m32r2 has been specified, in which case support for
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the extended M32R2 instruction set should be enabled. */
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the extended M32R2 instruction set should be enabled. */
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static int enable_m32rx = 0; /* Default to M32R. */
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static int enable_m32rx = 0; /* Default to M32R. */
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/* Non-zero if -m32rx -hidden has been specified, in which case support for
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/* Non-zero if -m32rx -hidden has been specified, in which case support for
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the special M32RX instruction set should be enabled. */
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the special M32RX instruction set should be enabled. */
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static int enable_special = 0;
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static int enable_special = 0;
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/* Non-zero if -bitinst has been specified, in which case support
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/* Non-zero if -bitinst has been specified, in which case support
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for extended M32R bit-field instruction set should be enabled. */
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for extended M32R bit-field instruction set should be enabled. */
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static int enable_special_m32r = 1;
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static int enable_special_m32r = 1;
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/* Non-zero if -float has been specified, in which case support for
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/* Non-zero if -float has been specified, in which case support for
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extended M32R floating point instruction set should be enabled. */
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extended M32R floating point instruction set should be enabled. */
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static int enable_special_float = 0;
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static int enable_special_float = 0;
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/* Non-zero if the programmer should be warned when an explicit parallel
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/* Non-zero if the programmer should be warned when an explicit parallel
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instruction might have constraint violations. */
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instruction might have constraint violations. */
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static int warn_explicit_parallel_conflicts = 1;
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static int warn_explicit_parallel_conflicts = 1;
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/* Non-zero if the programmer should not receive any messages about
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/* Non-zero if the programmer should not receive any messages about
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parallel instruction with potential or real constraint violations.
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parallel instruction with potential or real constraint violations.
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The ability to suppress these messages is intended only for hardware
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The ability to suppress these messages is intended only for hardware
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vendors testing the chip. It superceedes
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vendors testing the chip. It superceedes
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warn_explicit_parallel_conflicts. */
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warn_explicit_parallel_conflicts. */
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static int ignore_parallel_conflicts = 0;
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static int ignore_parallel_conflicts = 0;
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/* Non-zero if insns can be made parallel. */
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/* Non-zero if insns can be made parallel. */
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static int use_parallel = 0;
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static int use_parallel = 0;
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/* Non-zero if optimizations should be performed. */
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/* Non-zero if optimizations should be performed. */
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static int optimize;
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static int optimize;
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/* m32r er_flags. */
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/* m32r er_flags. */
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static int m32r_flags = 0;
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static int m32r_flags = 0;
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/* Stuff for .scomm symbols. */
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/* Stuff for .scomm symbols. */
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static segT sbss_section;
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static segT sbss_section;
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static asection scom_section;
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static asection scom_section;
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static asymbol scom_symbol;
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static asymbol scom_symbol;
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const char comment_chars[] = ";";
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const char comment_chars[] = ";";
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const char line_comment_chars[] = "#";
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = "!";
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const char line_separator_chars[] = "!";
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const char EXP_CHARS[] = "eE";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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const char FLT_CHARS[] = "dD";
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/* Relocations against symbols are done in two
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/* Relocations against symbols are done in two
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parts, with a HI relocation and a LO relocation. Each relocation
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parts, with a HI relocation and a LO relocation. Each relocation
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has only 16 bits of space to store an addend. This means that in
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has only 16 bits of space to store an addend. This means that in
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order for the linker to handle carries correctly, it must be able
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order for the linker to handle carries correctly, it must be able
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to locate both the HI and the LO relocation. This means that the
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to locate both the HI and the LO relocation. This means that the
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relocations must appear in order in the relocation table.
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relocations must appear in order in the relocation table.
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In order to implement this, we keep track of each unmatched HI
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In order to implement this, we keep track of each unmatched HI
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relocation. We then sort them so that they immediately precede the
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relocation. We then sort them so that they immediately precede the
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corresponding LO relocation. */
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corresponding LO relocation. */
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struct m32r_hi_fixup
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struct m32r_hi_fixup
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{
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{
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/* Next HI fixup. */
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/* Next HI fixup. */
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struct m32r_hi_fixup *next;
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struct m32r_hi_fixup *next;
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/* This fixup. */
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/* This fixup. */
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fixS *fixp;
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fixS *fixp;
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/* The section this fixup is in. */
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/* The section this fixup is in. */
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segT seg;
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segT seg;
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};
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};
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/* The list of unmatched HI relocs. */
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/* The list of unmatched HI relocs. */
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static struct m32r_hi_fixup *m32r_hi_fixup_list;
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static struct m32r_hi_fixup *m32r_hi_fixup_list;
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struct
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struct
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{
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{
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enum bfd_architecture bfd_mach;
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enum bfd_architecture bfd_mach;
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int mach_flags;
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int mach_flags;
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} mach_table[] =
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} mach_table[] =
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{
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{
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{ bfd_mach_m32r, (1<<MACH_M32R) },
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{ bfd_mach_m32r, (1<<MACH_M32R) },
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{ bfd_mach_m32rx, (1<<MACH_M32RX) },
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{ bfd_mach_m32rx, (1<<MACH_M32RX) },
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{ bfd_mach_m32r2, (1<<MACH_M32R2) }
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{ bfd_mach_m32r2, (1<<MACH_M32R2) }
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};
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};
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static void
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static void
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allow_m32rx (int on)
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allow_m32rx (int on)
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{
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{
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enable_m32rx = on;
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enable_m32rx = on;
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if (stdoutput != NULL)
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if (stdoutput != NULL)
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bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach);
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bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach);
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if (gas_cgen_cpu_desc != NULL)
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if (gas_cgen_cpu_desc != NULL)
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gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
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gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
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}
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}
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#define M32R_SHORTOPTS "O::K:"
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#define M32R_SHORTOPTS "O::K:"
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const char *md_shortopts = M32R_SHORTOPTS;
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const char *md_shortopts = M32R_SHORTOPTS;
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enum md_option_enums
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enum md_option_enums
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{
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{
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OPTION_M32R = OPTION_MD_BASE,
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OPTION_M32R = OPTION_MD_BASE,
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OPTION_M32RX,
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OPTION_M32RX,
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OPTION_M32R2,
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OPTION_M32R2,
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OPTION_BIG,
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OPTION_BIG,
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OPTION_LITTLE,
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OPTION_LITTLE,
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OPTION_PARALLEL,
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OPTION_PARALLEL,
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OPTION_NO_PARALLEL,
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OPTION_NO_PARALLEL,
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OPTION_WARN_PARALLEL,
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OPTION_WARN_PARALLEL,
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OPTION_NO_WARN_PARALLEL,
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OPTION_NO_WARN_PARALLEL,
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OPTION_IGNORE_PARALLEL,
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OPTION_IGNORE_PARALLEL,
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OPTION_NO_IGNORE_PARALLEL,
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OPTION_NO_IGNORE_PARALLEL,
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OPTION_SPECIAL,
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OPTION_SPECIAL,
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OPTION_SPECIAL_M32R,
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OPTION_SPECIAL_M32R,
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OPTION_NO_SPECIAL_M32R,
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OPTION_NO_SPECIAL_M32R,
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OPTION_SPECIAL_FLOAT,
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OPTION_SPECIAL_FLOAT,
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OPTION_WARN_UNMATCHED,
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OPTION_WARN_UNMATCHED,
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OPTION_NO_WARN_UNMATCHED
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OPTION_NO_WARN_UNMATCHED
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};
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};
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struct option md_longopts[] =
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struct option md_longopts[] =
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{
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{
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{"m32r", no_argument, NULL, OPTION_M32R},
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{"m32r", no_argument, NULL, OPTION_M32R},
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{"m32rx", no_argument, NULL, OPTION_M32RX},
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{"m32rx", no_argument, NULL, OPTION_M32RX},
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{"m32r2", no_argument, NULL, OPTION_M32R2},
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{"m32r2", no_argument, NULL, OPTION_M32R2},
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{"big", no_argument, NULL, OPTION_BIG},
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{"big", no_argument, NULL, OPTION_BIG},
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{"little", no_argument, NULL, OPTION_LITTLE},
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{"little", no_argument, NULL, OPTION_LITTLE},
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{"EB", no_argument, NULL, OPTION_BIG},
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{"EB", no_argument, NULL, OPTION_BIG},
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{"EL", no_argument, NULL, OPTION_LITTLE},
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{"EL", no_argument, NULL, OPTION_LITTLE},
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{"parallel", no_argument, NULL, OPTION_PARALLEL},
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{"parallel", no_argument, NULL, OPTION_PARALLEL},
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{"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},
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{"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},
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{"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
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{"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
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{"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
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{"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
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{"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
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{"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
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{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
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{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
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{"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL},
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{"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL},
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{"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL},
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{"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL},
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{"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
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{"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
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{"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
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{"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
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{"hidden", no_argument, NULL, OPTION_SPECIAL},
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{"hidden", no_argument, NULL, OPTION_SPECIAL},
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{"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
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{"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
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{"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R},
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{"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R},
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{"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
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{"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
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/* Sigh. I guess all warnings must now have both variants. */
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/* Sigh. I guess all warnings must now have both variants. */
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{"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
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{"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
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{"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
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{"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
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{"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
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{"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
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{"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
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{"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
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{NULL, no_argument, NULL, 0}
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{NULL, no_argument, NULL, 0}
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};
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};
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|
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size_t md_longopts_size = sizeof (md_longopts);
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size_t md_longopts_size = sizeof (md_longopts);
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|
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static void
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static void
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little (int on)
|
little (int on)
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{
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{
|
target_big_endian = ! on;
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target_big_endian = ! on;
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}
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}
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|
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/* Use parallel execution. */
|
/* Use parallel execution. */
|
|
|
static int
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static int
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parallel (void)
|
parallel (void)
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{
|
{
|
if (! enable_m32rx)
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if (! enable_m32rx)
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return 0;
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return 0;
|
|
|
if (use_parallel == 1)
|
if (use_parallel == 1)
|
return 1;
|
return 1;
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
int
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int
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md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
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md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
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{
|
{
|
switch (c)
|
switch (c)
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{
|
{
|
case 'O':
|
case 'O':
|
optimize = 1;
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optimize = 1;
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use_parallel = 1;
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use_parallel = 1;
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break;
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break;
|
|
|
case OPTION_M32R:
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case OPTION_M32R:
|
allow_m32rx (0);
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allow_m32rx (0);
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break;
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break;
|
|
|
case OPTION_M32RX:
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case OPTION_M32RX:
|
allow_m32rx (1);
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allow_m32rx (1);
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break;
|
break;
|
|
|
case OPTION_M32R2:
|
case OPTION_M32R2:
|
allow_m32rx (2);
|
allow_m32rx (2);
|
enable_special = 1;
|
enable_special = 1;
|
enable_special_m32r = 1;
|
enable_special_m32r = 1;
|
break;
|
break;
|
|
|
case OPTION_BIG:
|
case OPTION_BIG:
|
target_big_endian = 1;
|
target_big_endian = 1;
|
break;
|
break;
|
|
|
case OPTION_LITTLE:
|
case OPTION_LITTLE:
|
target_big_endian = 0;
|
target_big_endian = 0;
|
break;
|
break;
|
|
|
case OPTION_PARALLEL:
|
case OPTION_PARALLEL:
|
use_parallel = 1;
|
use_parallel = 1;
|
break;
|
break;
|
|
|
case OPTION_NO_PARALLEL:
|
case OPTION_NO_PARALLEL:
|
use_parallel = 0;
|
use_parallel = 0;
|
break;
|
break;
|
|
|
case OPTION_WARN_PARALLEL:
|
case OPTION_WARN_PARALLEL:
|
warn_explicit_parallel_conflicts = 1;
|
warn_explicit_parallel_conflicts = 1;
|
break;
|
break;
|
|
|
case OPTION_NO_WARN_PARALLEL:
|
case OPTION_NO_WARN_PARALLEL:
|
warn_explicit_parallel_conflicts = 0;
|
warn_explicit_parallel_conflicts = 0;
|
break;
|
break;
|
|
|
case OPTION_IGNORE_PARALLEL:
|
case OPTION_IGNORE_PARALLEL:
|
ignore_parallel_conflicts = 1;
|
ignore_parallel_conflicts = 1;
|
break;
|
break;
|
|
|
case OPTION_NO_IGNORE_PARALLEL:
|
case OPTION_NO_IGNORE_PARALLEL:
|
ignore_parallel_conflicts = 0;
|
ignore_parallel_conflicts = 0;
|
break;
|
break;
|
|
|
case OPTION_SPECIAL:
|
case OPTION_SPECIAL:
|
if (enable_m32rx)
|
if (enable_m32rx)
|
enable_special = 1;
|
enable_special = 1;
|
else
|
else
|
{
|
{
|
/* Pretend that we do not recognise this option. */
|
/* Pretend that we do not recognise this option. */
|
as_bad (_("Unrecognised option: -hidden"));
|
as_bad (_("Unrecognised option: -hidden"));
|
return 0;
|
return 0;
|
}
|
}
|
break;
|
break;
|
|
|
case OPTION_SPECIAL_M32R:
|
case OPTION_SPECIAL_M32R:
|
enable_special_m32r = 1;
|
enable_special_m32r = 1;
|
break;
|
break;
|
|
|
case OPTION_NO_SPECIAL_M32R:
|
case OPTION_NO_SPECIAL_M32R:
|
enable_special_m32r = 0;
|
enable_special_m32r = 0;
|
break;
|
break;
|
|
|
case OPTION_SPECIAL_FLOAT:
|
case OPTION_SPECIAL_FLOAT:
|
enable_special_float = 1;
|
enable_special_float = 1;
|
break;
|
break;
|
|
|
case OPTION_WARN_UNMATCHED:
|
case OPTION_WARN_UNMATCHED:
|
warn_unmatched_high = 1;
|
warn_unmatched_high = 1;
|
break;
|
break;
|
|
|
case OPTION_NO_WARN_UNMATCHED:
|
case OPTION_NO_WARN_UNMATCHED:
|
warn_unmatched_high = 0;
|
warn_unmatched_high = 0;
|
break;
|
break;
|
|
|
case 'K':
|
case 'K':
|
if (strcmp (arg, "PIC") != 0)
|
if (strcmp (arg, "PIC") != 0)
|
as_warn (_("Unrecognized option following -K"));
|
as_warn (_("Unrecognized option following -K"));
|
else
|
else
|
pic_code = 1;
|
pic_code = 1;
|
break;
|
break;
|
|
|
default:
|
default:
|
return 0;
|
return 0;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
void
|
void
|
md_show_usage (FILE *stream)
|
md_show_usage (FILE *stream)
|
{
|
{
|
fprintf (stream, _(" M32R specific command line options:\n"));
|
fprintf (stream, _(" M32R specific command line options:\n"));
|
|
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-m32r disable support for the m32rx instruction set\n"));
|
-m32r disable support for the m32rx instruction set\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-m32rx support the extended m32rx instruction set\n"));
|
-m32rx support the extended m32rx instruction set\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-m32r2 support the extended m32r2 instruction set\n"));
|
-m32r2 support the extended m32r2 instruction set\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-EL,-little produce little endian code and data\n"));
|
-EL,-little produce little endian code and data\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-EB,-big produce big endian code and data\n"));
|
-EB,-big produce big endian code and data\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-parallel try to combine instructions in parallel\n"));
|
-parallel try to combine instructions in parallel\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-no-parallel disable -parallel\n"));
|
-no-parallel disable -parallel\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-no-bitinst disallow the M32R2's extended bit-field instructions\n"));
|
-no-bitinst disallow the M32R2's extended bit-field instructions\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-O try to optimize code. Implies -parallel\n"));
|
-O try to optimize code. Implies -parallel\n"));
|
|
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-warn-explicit-parallel-conflicts warn when parallel instructions\n"));
|
-warn-explicit-parallel-conflicts warn when parallel instructions\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
might violate contraints\n"));
|
might violate contraints\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
|
-no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
instructions might violate contraints\n"));
|
instructions might violate contraints\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-Wp synonym for -warn-explicit-parallel-conflicts\n"));
|
-Wp synonym for -warn-explicit-parallel-conflicts\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
|
-Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-ignore-parallel-conflicts do not check parallel instructions\n"));
|
-ignore-parallel-conflicts do not check parallel instructions\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
fo contraint violations\n"));
|
fo contraint violations\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-no-ignore-parallel-conflicts check parallel instructions for\n"));
|
-no-ignore-parallel-conflicts check parallel instructions for\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
contraint violations\n"));
|
contraint violations\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-Ip synonym for -ignore-parallel-conflicts\n"));
|
-Ip synonym for -ignore-parallel-conflicts\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-nIp synonym for -no-ignore-parallel-conflicts\n"));
|
-nIp synonym for -no-ignore-parallel-conflicts\n"));
|
|
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
|
-warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-no-warn-unmatched-high do not warn about missing low relocs\n"));
|
-no-warn-unmatched-high do not warn about missing low relocs\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-Wuh synonym for -warn-unmatched-high\n"));
|
-Wuh synonym for -warn-unmatched-high\n"));
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-Wnuh synonym for -no-warn-unmatched-high\n"));
|
-Wnuh synonym for -no-warn-unmatched-high\n"));
|
|
|
fprintf (stream, _("\
|
fprintf (stream, _("\
|
-KPIC generate PIC\n"));
|
-KPIC generate PIC\n"));
|
}
|
}
|
|
|
/* Set by md_assemble for use by m32r_fill_insn. */
|
/* Set by md_assemble for use by m32r_fill_insn. */
|
static subsegT prev_subseg;
|
static subsegT prev_subseg;
|
static segT prev_seg;
|
static segT prev_seg;
|
|
|
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
|
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
|
symbolS * GOT_symbol;
|
symbolS * GOT_symbol;
|
|
|
static inline int
|
static inline int
|
m32r_PIC_related_p (symbolS *sym)
|
m32r_PIC_related_p (symbolS *sym)
|
{
|
{
|
expressionS *exp;
|
expressionS *exp;
|
|
|
if (! sym)
|
if (! sym)
|
return 0;
|
return 0;
|
|
|
if (sym == GOT_symbol)
|
if (sym == GOT_symbol)
|
return 1;
|
return 1;
|
|
|
exp = symbol_get_value_expression (sym);
|
exp = symbol_get_value_expression (sym);
|
|
|
return (exp->X_op == O_PIC_reloc
|
return (exp->X_op == O_PIC_reloc
|
|| exp->X_md == BFD_RELOC_M32R_26_PLTREL
|
|| exp->X_md == BFD_RELOC_M32R_26_PLTREL
|
|| m32r_PIC_related_p (exp->X_add_symbol)
|
|| m32r_PIC_related_p (exp->X_add_symbol)
|
|| m32r_PIC_related_p (exp->X_op_symbol));
|
|| m32r_PIC_related_p (exp->X_op_symbol));
|
}
|
}
|
|
|
static inline int
|
static inline int
|
m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
|
m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
|
{
|
{
|
expressionS *exp = main_exp;
|
expressionS *exp = main_exp;
|
|
|
if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol))
|
if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol))
|
return 1;
|
return 1;
|
|
|
if (exp->X_op == O_symbol && exp->X_add_symbol)
|
if (exp->X_op == O_symbol && exp->X_add_symbol)
|
{
|
{
|
if (exp->X_add_symbol == GOT_symbol)
|
if (exp->X_add_symbol == GOT_symbol)
|
{
|
{
|
*r_type_p = BFD_RELOC_M32R_GOTPC24;
|
*r_type_p = BFD_RELOC_M32R_GOTPC24;
|
return 0;
|
return 0;
|
}
|
}
|
}
|
}
|
else if (exp->X_op == O_add)
|
else if (exp->X_op == O_add)
|
{
|
{
|
exp = symbol_get_value_expression (exp->X_add_symbol);
|
exp = symbol_get_value_expression (exp->X_add_symbol);
|
if (! exp)
|
if (! exp)
|
return 0;
|
return 0;
|
}
|
}
|
|
|
if (exp->X_op == O_PIC_reloc)
|
if (exp->X_op == O_PIC_reloc)
|
{
|
{
|
*r_type_p = exp->X_md;
|
*r_type_p = exp->X_md;
|
if (exp == main_exp)
|
if (exp == main_exp)
|
exp->X_op = O_symbol;
|
exp->X_op = O_symbol;
|
else
|
else
|
{
|
{
|
main_exp->X_add_symbol = exp->X_add_symbol;
|
main_exp->X_add_symbol = exp->X_add_symbol;
|
main_exp->X_add_number += exp->X_add_number;
|
main_exp->X_add_number += exp->X_add_number;
|
}
|
}
|
}
|
}
|
else
|
else
|
return (m32r_PIC_related_p (exp->X_add_symbol)
|
return (m32r_PIC_related_p (exp->X_add_symbol)
|
|| m32r_PIC_related_p (exp->X_op_symbol));
|
|| m32r_PIC_related_p (exp->X_op_symbol));
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* FIXME: Should be machine generated. */
|
/* FIXME: Should be machine generated. */
|
#define NOP_INSN 0x7000
|
#define NOP_INSN 0x7000
|
#define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
|
#define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
|
|
|
/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
|
/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
|
of an rs_align_code fragment. */
|
of an rs_align_code fragment. */
|
|
|
void
|
void
|
m32r_handle_align (fragS *fragp)
|
m32r_handle_align (fragS *fragp)
|
{
|
{
|
static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
|
static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
|
static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
|
static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
|
|
|
int bytes, fix;
|
int bytes, fix;
|
char *p;
|
char *p;
|
|
|
if (fragp->fr_type != rs_align_code)
|
if (fragp->fr_type != rs_align_code)
|
return;
|
return;
|
|
|
bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
|
bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
|
p = fragp->fr_literal + fragp->fr_fix;
|
p = fragp->fr_literal + fragp->fr_fix;
|
fix = 0;
|
fix = 0;
|
|
|
if (bytes & 1)
|
if (bytes & 1)
|
{
|
{
|
fix = 1;
|
fix = 1;
|
*p++ = 0;
|
*p++ = 0;
|
bytes--;
|
bytes--;
|
}
|
}
|
|
|
if (bytes & 2)
|
if (bytes & 2)
|
{
|
{
|
memcpy (p, nop_pattern, 2);
|
memcpy (p, nop_pattern, 2);
|
p += 2;
|
p += 2;
|
bytes -= 2;
|
bytes -= 2;
|
fix += 2;
|
fix += 2;
|
}
|
}
|
|
|
memcpy (p, multi_nop_pattern, 4);
|
memcpy (p, multi_nop_pattern, 4);
|
|
|
fragp->fr_fix += fix;
|
fragp->fr_fix += fix;
|
fragp->fr_var = 4;
|
fragp->fr_var = 4;
|
}
|
}
|
|
|
/* If the last instruction was the first of 2 16 bit insns,
|
/* If the last instruction was the first of 2 16 bit insns,
|
output a nop to move the PC to a 32 bit boundary.
|
output a nop to move the PC to a 32 bit boundary.
|
|
|
This is done via an alignment specification since branch relaxing
|
This is done via an alignment specification since branch relaxing
|
may make it unnecessary.
|
may make it unnecessary.
|
|
|
Internally, we need to output one of these each time a 32 bit insn is
|
Internally, we need to output one of these each time a 32 bit insn is
|
seen after an insn that is relaxable. */
|
seen after an insn that is relaxable. */
|
|
|
static void
|
static void
|
fill_insn (int ignore ATTRIBUTE_UNUSED)
|
fill_insn (int ignore ATTRIBUTE_UNUSED)
|
{
|
{
|
frag_align_code (2, 0);
|
frag_align_code (2, 0);
|
prev_insn.insn = NULL;
|
prev_insn.insn = NULL;
|
seen_relaxable_p = 0;
|
seen_relaxable_p = 0;
|
}
|
}
|
|
|
/* Record the symbol so that when we output the insn, we can create
|
/* Record the symbol so that when we output the insn, we can create
|
a symbol that is at the start of the instruction. This is used
|
a symbol that is at the start of the instruction. This is used
|
to emit the label for the start of a breakpoint without causing
|
to emit the label for the start of a breakpoint without causing
|
the assembler to emit a NOP if the previous instruction was a
|
the assembler to emit a NOP if the previous instruction was a
|
16 bit instruction. */
|
16 bit instruction. */
|
|
|
static void
|
static void
|
debug_sym (int ignore ATTRIBUTE_UNUSED)
|
debug_sym (int ignore ATTRIBUTE_UNUSED)
|
{
|
{
|
char *name;
|
char *name;
|
char delim;
|
char delim;
|
char *end_name;
|
char *end_name;
|
symbolS *symbolP;
|
symbolS *symbolP;
|
sym_linkS *link;
|
sym_linkS *link;
|
|
|
name = input_line_pointer;
|
name = input_line_pointer;
|
delim = get_symbol_end ();
|
delim = get_symbol_end ();
|
end_name = input_line_pointer;
|
end_name = input_line_pointer;
|
|
|
if ((symbolP = symbol_find (name)) == NULL
|
if ((symbolP = symbol_find (name)) == NULL
|
&& (symbolP = md_undefined_symbol (name)) == NULL)
|
&& (symbolP = md_undefined_symbol (name)) == NULL)
|
symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
|
symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
|
|
|
symbol_table_insert (symbolP);
|
symbol_table_insert (symbolP);
|
if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
|
if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
|
|| S_IS_EXTERNAL (symbolP)
|
|| S_IS_EXTERNAL (symbolP)
|
|| S_IS_WEAK (symbolP)))
|
|| S_IS_WEAK (symbolP)))
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
|
as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
|
|
|
else
|
else
|
{
|
{
|
link = (sym_linkS *) xmalloc (sizeof (sym_linkS));
|
link = (sym_linkS *) xmalloc (sizeof (sym_linkS));
|
link->symbol = symbolP;
|
link->symbol = symbolP;
|
link->next = debug_sym_link;
|
link->next = debug_sym_link;
|
debug_sym_link = link;
|
debug_sym_link = link;
|
symbol_get_obj (symbolP)->local = 1;
|
symbol_get_obj (symbolP)->local = 1;
|
}
|
}
|
|
|
*end_name = delim;
|
*end_name = delim;
|
demand_empty_rest_of_line ();
|
demand_empty_rest_of_line ();
|
}
|
}
|
|
|
/* Second pass to expanding the debug symbols, go through linked
|
/* Second pass to expanding the debug symbols, go through linked
|
list of symbols and reassign the address. */
|
list of symbols and reassign the address. */
|
|
|
static void
|
static void
|
expand_debug_syms (sym_linkS *syms, int align)
|
expand_debug_syms (sym_linkS *syms, int align)
|
{
|
{
|
char *save_input_line = input_line_pointer;
|
char *save_input_line = input_line_pointer;
|
sym_linkS *next_syms;
|
sym_linkS *next_syms;
|
|
|
if (!syms)
|
if (!syms)
|
return;
|
return;
|
|
|
(void) frag_align_code (align, 0);
|
(void) frag_align_code (align, 0);
|
for (; syms != (sym_linkS *) 0; syms = next_syms)
|
for (; syms != (sym_linkS *) 0; syms = next_syms)
|
{
|
{
|
symbolS *symbolP = syms->symbol;
|
symbolS *symbolP = syms->symbol;
|
next_syms = syms->next;
|
next_syms = syms->next;
|
input_line_pointer = ".\n";
|
input_line_pointer = ".\n";
|
pseudo_set (symbolP);
|
pseudo_set (symbolP);
|
free ((char *) syms);
|
free ((char *) syms);
|
}
|
}
|
|
|
input_line_pointer = save_input_line;
|
input_line_pointer = save_input_line;
|
}
|
}
|
|
|
void
|
void
|
m32r_flush_pending_output (void)
|
m32r_flush_pending_output (void)
|
{
|
{
|
if (debug_sym_link)
|
if (debug_sym_link)
|
{
|
{
|
expand_debug_syms (debug_sym_link, 1);
|
expand_debug_syms (debug_sym_link, 1);
|
debug_sym_link = (sym_linkS *) 0;
|
debug_sym_link = (sym_linkS *) 0;
|
}
|
}
|
}
|
}
|
|
|
/* Cover function to fill_insn called after a label and at end of assembly.
|
/* Cover function to fill_insn called after a label and at end of assembly.
|
The result is always 1: we're called in a conditional to see if the
|
The result is always 1: we're called in a conditional to see if the
|
current line is a label. */
|
current line is a label. */
|
|
|
int
|
int
|
m32r_fill_insn (int done)
|
m32r_fill_insn (int done)
|
{
|
{
|
if (prev_seg != NULL)
|
if (prev_seg != NULL)
|
{
|
{
|
segT seg = now_seg;
|
segT seg = now_seg;
|
subsegT subseg = now_subseg;
|
subsegT subseg = now_subseg;
|
|
|
subseg_set (prev_seg, prev_subseg);
|
subseg_set (prev_seg, prev_subseg);
|
|
|
fill_insn (0);
|
fill_insn (0);
|
|
|
subseg_set (seg, subseg);
|
subseg_set (seg, subseg);
|
}
|
}
|
|
|
if (done && debug_sym_link)
|
if (done && debug_sym_link)
|
{
|
{
|
expand_debug_syms (debug_sym_link, 1);
|
expand_debug_syms (debug_sym_link, 1);
|
debug_sym_link = (sym_linkS *) 0;
|
debug_sym_link = (sym_linkS *) 0;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
/* The default target format to use. */
|
/* The default target format to use. */
|
|
|
const char *
|
const char *
|
m32r_target_format (void)
|
m32r_target_format (void)
|
{
|
{
|
#ifdef TE_LINUX
|
#ifdef TE_LINUX
|
if (target_big_endian)
|
if (target_big_endian)
|
return "elf32-m32r-linux";
|
return "elf32-m32r-linux";
|
else
|
else
|
return "elf32-m32rle-linux";
|
return "elf32-m32rle-linux";
|
#else
|
#else
|
if (target_big_endian)
|
if (target_big_endian)
|
return "elf32-m32r";
|
return "elf32-m32r";
|
else
|
else
|
return "elf32-m32rle";
|
return "elf32-m32rle";
|
#endif
|
#endif
|
}
|
}
|
|
|
void
|
void
|
md_begin (void)
|
md_begin (void)
|
{
|
{
|
flagword applicable;
|
flagword applicable;
|
segT seg;
|
segT seg;
|
subsegT subseg;
|
subsegT subseg;
|
|
|
/* Initialize the `cgen' interface. */
|
/* Initialize the `cgen' interface. */
|
|
|
/* Set the machine number and endian. */
|
/* Set the machine number and endian. */
|
gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
|
gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
|
CGEN_CPU_OPEN_ENDIAN,
|
CGEN_CPU_OPEN_ENDIAN,
|
(target_big_endian ?
|
(target_big_endian ?
|
CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE),
|
CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE),
|
CGEN_CPU_OPEN_END);
|
CGEN_CPU_OPEN_END);
|
m32r_cgen_init_asm (gas_cgen_cpu_desc);
|
m32r_cgen_init_asm (gas_cgen_cpu_desc);
|
|
|
/* The operand instance table is used during optimization to determine
|
/* The operand instance table is used during optimization to determine
|
which insns can be executed in parallel. It is also used to give
|
which insns can be executed in parallel. It is also used to give
|
warnings regarding operand interference in parallel insns. */
|
warnings regarding operand interference in parallel insns. */
|
m32r_cgen_init_opinst_table (gas_cgen_cpu_desc);
|
m32r_cgen_init_opinst_table (gas_cgen_cpu_desc);
|
|
|
/* This is a callback from cgen to gas to parse operands. */
|
/* This is a callback from cgen to gas to parse operands. */
|
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
|
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
|
|
|
/* Save the current subseg so we can restore it [it's the default one and
|
/* Save the current subseg so we can restore it [it's the default one and
|
we don't want the initial section to be .sbss]. */
|
we don't want the initial section to be .sbss]. */
|
seg = now_seg;
|
seg = now_seg;
|
subseg = now_subseg;
|
subseg = now_subseg;
|
|
|
/* The sbss section is for local .scomm symbols. */
|
/* The sbss section is for local .scomm symbols. */
|
sbss_section = subseg_new (".sbss", 0);
|
sbss_section = subseg_new (".sbss", 0);
|
seg_info (sbss_section)->bss = 1;
|
seg_info (sbss_section)->bss = 1;
|
|
|
/* This is copied from perform_an_assembly_pass. */
|
/* This is copied from perform_an_assembly_pass. */
|
applicable = bfd_applicable_section_flags (stdoutput);
|
applicable = bfd_applicable_section_flags (stdoutput);
|
bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
|
bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
|
|
|
subseg_set (seg, subseg);
|
subseg_set (seg, subseg);
|
|
|
/* We must construct a fake section similar to bfd_com_section
|
/* We must construct a fake section similar to bfd_com_section
|
but with the name .scommon. */
|
but with the name .scommon. */
|
scom_section = bfd_com_section;
|
scom_section = bfd_com_section;
|
scom_section.name = ".scommon";
|
scom_section.name = ".scommon";
|
scom_section.output_section = & scom_section;
|
scom_section.output_section = & scom_section;
|
scom_section.symbol = & scom_symbol;
|
scom_section.symbol = & scom_symbol;
|
scom_section.symbol_ptr_ptr = & scom_section.symbol;
|
scom_section.symbol_ptr_ptr = & scom_section.symbol;
|
scom_symbol = * bfd_com_section.symbol;
|
scom_symbol = * bfd_com_section.symbol;
|
scom_symbol.name = ".scommon";
|
scom_symbol.name = ".scommon";
|
scom_symbol.section = & scom_section;
|
scom_symbol.section = & scom_section;
|
|
|
allow_m32rx (enable_m32rx);
|
allow_m32rx (enable_m32rx);
|
|
|
gas_cgen_initialize_saved_fixups_array ();
|
gas_cgen_initialize_saved_fixups_array ();
|
}
|
}
|
|
|
#define OPERAND_IS_COND_BIT(operand, indices, index) \
|
#define OPERAND_IS_COND_BIT(operand, indices, index) \
|
((operand)->hw_type == HW_H_COND \
|
((operand)->hw_type == HW_H_COND \
|
|| ((operand)->hw_type == HW_H_PSW) \
|
|| ((operand)->hw_type == HW_H_PSW) \
|
|| ((operand)->hw_type == HW_H_CR \
|
|| ((operand)->hw_type == HW_H_CR \
|
&& (indices [index] == 0 || indices [index] == 1)))
|
&& (indices [index] == 0 || indices [index] == 1)))
|
|
|
/* Returns true if an output of instruction 'a' is referenced by an operand
|
/* Returns true if an output of instruction 'a' is referenced by an operand
|
of instruction 'b'. If 'check_outputs' is true then b's outputs are
|
of instruction 'b'. If 'check_outputs' is true then b's outputs are
|
checked, otherwise its inputs are examined. */
|
checked, otherwise its inputs are examined. */
|
|
|
static int
|
static int
|
first_writes_to_seconds_operands (m32r_insn *a,
|
first_writes_to_seconds_operands (m32r_insn *a,
|
m32r_insn *b,
|
m32r_insn *b,
|
const int check_outputs)
|
const int check_outputs)
|
{
|
{
|
const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
|
const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
|
const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
|
const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
|
int a_index;
|
int a_index;
|
|
|
if (ignore_parallel_conflicts)
|
if (ignore_parallel_conflicts)
|
return 0;
|
return 0;
|
|
|
/* If at least one of the instructions takes no operands, then there is
|
/* If at least one of the instructions takes no operands, then there is
|
nothing to check. There really are instructions without operands,
|
nothing to check. There really are instructions without operands,
|
eg 'nop'. */
|
eg 'nop'. */
|
if (a_operands == NULL || b_ops == NULL)
|
if (a_operands == NULL || b_ops == NULL)
|
return 0;
|
return 0;
|
|
|
/* Scan the operand list of 'a' looking for an output operand. */
|
/* Scan the operand list of 'a' looking for an output operand. */
|
for (a_index = 0;
|
for (a_index = 0;
|
a_operands->type != CGEN_OPINST_END;
|
a_operands->type != CGEN_OPINST_END;
|
a_index ++, a_operands ++)
|
a_index ++, a_operands ++)
|
{
|
{
|
if (a_operands->type == CGEN_OPINST_OUTPUT)
|
if (a_operands->type == CGEN_OPINST_OUTPUT)
|
{
|
{
|
int b_index;
|
int b_index;
|
const CGEN_OPINST *b_operands = b_ops;
|
const CGEN_OPINST *b_operands = b_ops;
|
|
|
/* Special Case:
|
/* Special Case:
|
The Condition bit 'C' is a shadow of the CBR register (control
|
The Condition bit 'C' is a shadow of the CBR register (control
|
register 1) and also a shadow of bit 31 of the program status
|
register 1) and also a shadow of bit 31 of the program status
|
word (control register 0). For now this is handled here, rather
|
word (control register 0). For now this is handled here, rather
|
than by cgen.... */
|
than by cgen.... */
|
|
|
if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
|
if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
|
{
|
{
|
/* Scan operand list of 'b' looking for another reference to the
|
/* Scan operand list of 'b' looking for another reference to the
|
condition bit, which goes in the right direction. */
|
condition bit, which goes in the right direction. */
|
for (b_index = 0;
|
for (b_index = 0;
|
b_operands->type != CGEN_OPINST_END;
|
b_operands->type != CGEN_OPINST_END;
|
b_index++, b_operands++)
|
b_index++, b_operands++)
|
{
|
{
|
if ((b_operands->type
|
if ((b_operands->type
|
== (check_outputs
|
== (check_outputs
|
? CGEN_OPINST_OUTPUT
|
? CGEN_OPINST_OUTPUT
|
: CGEN_OPINST_INPUT))
|
: CGEN_OPINST_INPUT))
|
&& OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
|
&& OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
|
return 1;
|
return 1;
|
}
|
}
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Scan operand list of 'b' looking for an operand that
|
/* Scan operand list of 'b' looking for an operand that
|
references the same hardware element, and which goes in the
|
references the same hardware element, and which goes in the
|
right direction. */
|
right direction. */
|
for (b_index = 0;
|
for (b_index = 0;
|
b_operands->type != CGEN_OPINST_END;
|
b_operands->type != CGEN_OPINST_END;
|
b_index++, b_operands++)
|
b_index++, b_operands++)
|
{
|
{
|
if ((b_operands->type
|
if ((b_operands->type
|
== (check_outputs
|
== (check_outputs
|
? CGEN_OPINST_OUTPUT
|
? CGEN_OPINST_OUTPUT
|
: CGEN_OPINST_INPUT))
|
: CGEN_OPINST_INPUT))
|
&& (b_operands->hw_type == a_operands->hw_type)
|
&& (b_operands->hw_type == a_operands->hw_type)
|
&& (a->indices[a_index] == b->indices[b_index]))
|
&& (a->indices[a_index] == b->indices[b_index]))
|
return 1;
|
return 1;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Returns true if the insn can (potentially) alter the program counter. */
|
/* Returns true if the insn can (potentially) alter the program counter. */
|
|
|
static int
|
static int
|
writes_to_pc (m32r_insn *a)
|
writes_to_pc (m32r_insn *a)
|
{
|
{
|
if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
|
if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
|
|| CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
|
|| CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
|
return 1;
|
return 1;
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Return NULL if the two 16 bit insns can be executed in parallel.
|
/* Return NULL if the two 16 bit insns can be executed in parallel.
|
Otherwise return a pointer to an error message explaining why not. */
|
Otherwise return a pointer to an error message explaining why not. */
|
|
|
static const char *
|
static const char *
|
can_make_parallel (m32r_insn *a, m32r_insn *b)
|
can_make_parallel (m32r_insn *a, m32r_insn *b)
|
{
|
{
|
PIPE_ATTR a_pipe;
|
PIPE_ATTR a_pipe;
|
PIPE_ATTR b_pipe;
|
PIPE_ATTR b_pipe;
|
|
|
/* Make sure the instructions are the right length. */
|
/* Make sure the instructions are the right length. */
|
if (CGEN_FIELDS_BITSIZE (&a->fields) != 16
|
if (CGEN_FIELDS_BITSIZE (&a->fields) != 16
|
|| CGEN_FIELDS_BITSIZE (&b->fields) != 16)
|
|| CGEN_FIELDS_BITSIZE (&b->fields) != 16)
|
abort ();
|
abort ();
|
|
|
if (first_writes_to_seconds_operands (a, b, TRUE))
|
if (first_writes_to_seconds_operands (a, b, TRUE))
|
return _("instructions write to the same destination register.");
|
return _("instructions write to the same destination register.");
|
|
|
a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
|
a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
|
b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
|
b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
|
|
|
/* Make sure that the instructions use the correct execution pipelines. */
|
/* Make sure that the instructions use the correct execution pipelines. */
|
if (a_pipe == PIPE_NONE
|
if (a_pipe == PIPE_NONE
|
|| b_pipe == PIPE_NONE)
|
|| b_pipe == PIPE_NONE)
|
return _("Instructions do not use parallel execution pipelines.");
|
return _("Instructions do not use parallel execution pipelines.");
|
|
|
/* Leave this test for last, since it is the only test that can
|
/* Leave this test for last, since it is the only test that can
|
go away if the instructions are swapped, and we want to make
|
go away if the instructions are swapped, and we want to make
|
sure that any other errors are detected before this happens. */
|
sure that any other errors are detected before this happens. */
|
if (a_pipe == PIPE_S
|
if (a_pipe == PIPE_S
|
|| b_pipe == PIPE_O
|
|| b_pipe == PIPE_O
|
|| (b_pipe == PIPE_O_OS && (enable_m32rx != 2)))
|
|| (b_pipe == PIPE_O_OS && (enable_m32rx != 2)))
|
return _("Instructions share the same execution pipeline");
|
return _("Instructions share the same execution pipeline");
|
|
|
return NULL;
|
return NULL;
|
}
|
}
|
|
|
/* Force the top bit of the second 16-bit insn to be set. */
|
/* Force the top bit of the second 16-bit insn to be set. */
|
|
|
static void
|
static void
|
make_parallel (CGEN_INSN_BYTES_PTR buffer)
|
make_parallel (CGEN_INSN_BYTES_PTR buffer)
|
{
|
{
|
#if CGEN_INT_INSN_P
|
#if CGEN_INT_INSN_P
|
*buffer |= 0x8000;
|
*buffer |= 0x8000;
|
#else
|
#else
|
buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|
buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|
|= 0x80;
|
|= 0x80;
|
#endif
|
#endif
|
}
|
}
|
|
|
/* Same as make_parallel except buffer contains the bytes in target order. */
|
/* Same as make_parallel except buffer contains the bytes in target order. */
|
|
|
static void
|
static void
|
target_make_parallel (char *buffer)
|
target_make_parallel (char *buffer)
|
{
|
{
|
buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|
buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|
|= 0x80;
|
|= 0x80;
|
}
|
}
|
|
|
/* Assemble two instructions with an explicit parallel operation (||) or
|
/* Assemble two instructions with an explicit parallel operation (||) or
|
sequential operation (->). */
|
sequential operation (->). */
|
|
|
static void
|
static void
|
assemble_two_insns (char *str1, char *str2, int parallel_p)
|
assemble_two_insns (char *str1, char *str2, int parallel_p)
|
{
|
{
|
char *str3;
|
char *str3;
|
m32r_insn first;
|
m32r_insn first;
|
m32r_insn second;
|
m32r_insn second;
|
char *errmsg;
|
char *errmsg;
|
char save_str2 = *str2;
|
char save_str2 = *str2;
|
|
|
/* Separate the two instructions. */
|
/* Separate the two instructions. */
|
*str2 = 0;
|
*str2 = 0;
|
|
|
/* Make sure the two insns begin on a 32 bit boundary.
|
/* Make sure the two insns begin on a 32 bit boundary.
|
This is also done for the serial case (foo -> bar), relaxing doesn't
|
This is also done for the serial case (foo -> bar), relaxing doesn't
|
affect insns written like this.
|
affect insns written like this.
|
Note that we must always do this as we can't assume anything about
|
Note that we must always do this as we can't assume anything about
|
whether we're currently on a 32 bit boundary or not. Relaxing may
|
whether we're currently on a 32 bit boundary or not. Relaxing may
|
change this. */
|
change this. */
|
fill_insn (0);
|
fill_insn (0);
|
|
|
first.debug_sym_link = debug_sym_link;
|
first.debug_sym_link = debug_sym_link;
|
debug_sym_link = (sym_linkS *) 0;
|
debug_sym_link = (sym_linkS *) 0;
|
|
|
/* Parse the first instruction. */
|
/* Parse the first instruction. */
|
if (! (first.insn = m32r_cgen_assemble_insn
|
if (! (first.insn = m32r_cgen_assemble_insn
|
(gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg)))
|
(gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg)))
|
{
|
{
|
as_bad (errmsg);
|
as_bad (errmsg);
|
return;
|
return;
|
}
|
}
|
|
|
/* Check it. */
|
/* Check it. */
|
if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
|
if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("not a 16 bit instruction '%s'"), str1);
|
as_bad (_("not a 16 bit instruction '%s'"), str1);
|
return;
|
return;
|
}
|
}
|
#ifdef E_M32R2_ARCH
|
#ifdef E_M32R2_ARCH
|
else if ((enable_m32rx == 1)
|
else if ((enable_m32rx == 1)
|
/* FIXME: Need standard macro to perform this test. */
|
/* FIXME: Need standard macro to perform this test. */
|
&& ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
&& ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
& (1 << MACH_M32R2))
|
& (1 << MACH_M32R2))
|
&& !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
&& !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
& (1 << MACH_M32RX)))))
|
& (1 << MACH_M32RX)))))
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("instruction '%s' is for the M32R2 only"), str1);
|
as_bad (_("instruction '%s' is for the M32R2 only"), str1);
|
return;
|
return;
|
}
|
}
|
else if ((! enable_special
|
else if ((! enable_special
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
|
|| (! enable_special_m32r
|
|| (! enable_special_m32r
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)))
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)))
|
#else
|
#else
|
else if (! enable_special
|
else if (! enable_special
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
|
#endif
|
#endif
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("unknown instruction '%s'"), str1);
|
as_bad (_("unknown instruction '%s'"), str1);
|
return;
|
return;
|
}
|
}
|
else if (! enable_m32rx
|
else if (! enable_m32rx
|
/* FIXME: Need standard macro to perform this test. */
|
/* FIXME: Need standard macro to perform this test. */
|
&& (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
&& (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
== (1 << MACH_M32RX)))
|
== (1 << MACH_M32RX)))
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("instruction '%s' is for the M32RX only"), str1);
|
as_bad (_("instruction '%s' is for the M32RX only"), str1);
|
return;
|
return;
|
}
|
}
|
|
|
/* Check to see if this is an allowable parallel insn. */
|
/* Check to see if this is an allowable parallel insn. */
|
if (parallel_p
|
if (parallel_p
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
|
as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
|
return;
|
return;
|
}
|
}
|
|
|
/* Restore the original assembly text, just in case it is needed. */
|
/* Restore the original assembly text, just in case it is needed. */
|
*str2 = save_str2;
|
*str2 = save_str2;
|
|
|
/* Save the original string pointer. */
|
/* Save the original string pointer. */
|
str3 = str1;
|
str3 = str1;
|
|
|
/* Advanced past the parsed string. */
|
/* Advanced past the parsed string. */
|
str1 = str2 + 2;
|
str1 = str2 + 2;
|
|
|
/* Remember the entire string in case it is needed for error
|
/* Remember the entire string in case it is needed for error
|
messages. */
|
messages. */
|
str2 = str3;
|
str2 = str3;
|
|
|
/* Convert the opcode to lower case. */
|
/* Convert the opcode to lower case. */
|
{
|
{
|
char *s2 = str1;
|
char *s2 = str1;
|
|
|
while (ISSPACE (*s2++))
|
while (ISSPACE (*s2++))
|
continue;
|
continue;
|
|
|
--s2;
|
--s2;
|
|
|
while (ISALNUM (*s2))
|
while (ISALNUM (*s2))
|
{
|
{
|
*s2 = TOLOWER (*s2);
|
*s2 = TOLOWER (*s2);
|
s2++;
|
s2++;
|
}
|
}
|
}
|
}
|
|
|
/* Preserve any fixups that have been generated and reset the list
|
/* Preserve any fixups that have been generated and reset the list
|
to empty. */
|
to empty. */
|
gas_cgen_save_fixups (0);
|
gas_cgen_save_fixups (0);
|
|
|
/* Get the indices of the operands of the instruction. */
|
/* Get the indices of the operands of the instruction. */
|
/* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
|
/* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
|
doesn't seem right. Perhaps allow passing fields like we do insn. */
|
doesn't seem right. Perhaps allow passing fields like we do insn. */
|
/* FIXME: ALIAS insns do not have operands, so we use this function
|
/* FIXME: ALIAS insns do not have operands, so we use this function
|
to find the equivalent insn and overwrite the value stored in our
|
to find the equivalent insn and overwrite the value stored in our
|
structure. We still need the original insn, however, since this
|
structure. We still need the original insn, however, since this
|
may have certain attributes that are not present in the unaliased
|
may have certain attributes that are not present in the unaliased
|
version (eg relaxability). When aliases behave differently this
|
version (eg relaxability). When aliases behave differently this
|
may have to change. */
|
may have to change. */
|
first.orig_insn = first.insn;
|
first.orig_insn = first.insn;
|
{
|
{
|
CGEN_FIELDS tmp_fields;
|
CGEN_FIELDS tmp_fields;
|
first.insn = cgen_lookup_get_insn_operands
|
first.insn = cgen_lookup_get_insn_operands
|
(gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
|
(gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
|
first.indices, &tmp_fields);
|
first.indices, &tmp_fields);
|
}
|
}
|
|
|
if (first.insn == NULL)
|
if (first.insn == NULL)
|
as_fatal (_("internal error: lookup/get operands failed"));
|
as_fatal (_("internal error: lookup/get operands failed"));
|
|
|
second.debug_sym_link = NULL;
|
second.debug_sym_link = NULL;
|
|
|
/* Parse the second instruction. */
|
/* Parse the second instruction. */
|
if (! (second.insn = m32r_cgen_assemble_insn
|
if (! (second.insn = m32r_cgen_assemble_insn
|
(gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg)))
|
(gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg)))
|
{
|
{
|
as_bad (errmsg);
|
as_bad (errmsg);
|
return;
|
return;
|
}
|
}
|
|
|
/* Check it. */
|
/* Check it. */
|
if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
|
if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("not a 16 bit instruction '%s'"), str1);
|
as_bad (_("not a 16 bit instruction '%s'"), str1);
|
return;
|
return;
|
}
|
}
|
#ifdef E_M32R2_ARCH
|
#ifdef E_M32R2_ARCH
|
else if ((enable_m32rx == 1)
|
else if ((enable_m32rx == 1)
|
/* FIXME: Need standard macro to perform this test. */
|
/* FIXME: Need standard macro to perform this test. */
|
&& ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
&& ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
& (1 << MACH_M32R2))
|
& (1 << MACH_M32R2))
|
&& !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
&& !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
& (1 << MACH_M32RX)))))
|
& (1 << MACH_M32RX)))))
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("instruction '%s' is for the M32R2 only"), str1);
|
as_bad (_("instruction '%s' is for the M32R2 only"), str1);
|
return;
|
return;
|
}
|
}
|
else if ((! enable_special
|
else if ((! enable_special
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
|| (! enable_special_m32r
|
|| (! enable_special_m32r
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)))
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)))
|
#else
|
#else
|
else if (! enable_special
|
else if (! enable_special
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
#endif
|
#endif
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("unknown instruction '%s'"), str1);
|
as_bad (_("unknown instruction '%s'"), str1);
|
return;
|
return;
|
}
|
}
|
else if (! enable_m32rx
|
else if (! enable_m32rx
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("instruction '%s' is for the M32RX only"), str1);
|
as_bad (_("instruction '%s' is for the M32RX only"), str1);
|
return;
|
return;
|
}
|
}
|
|
|
/* Check to see if this is an allowable parallel insn. */
|
/* Check to see if this is an allowable parallel insn. */
|
if (parallel_p
|
if (parallel_p
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
|
as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
|
return;
|
return;
|
}
|
}
|
|
|
if (parallel_p && ! enable_m32rx)
|
if (parallel_p && ! enable_m32rx)
|
{
|
{
|
if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
|
if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
|
&& CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
|
&& CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
|
as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
|
return;
|
return;
|
}
|
}
|
}
|
}
|
|
|
/* Get the indices of the operands of the instruction. */
|
/* Get the indices of the operands of the instruction. */
|
second.orig_insn = second.insn;
|
second.orig_insn = second.insn;
|
{
|
{
|
CGEN_FIELDS tmp_fields;
|
CGEN_FIELDS tmp_fields;
|
second.insn = cgen_lookup_get_insn_operands
|
second.insn = cgen_lookup_get_insn_operands
|
(gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
|
(gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
|
second.indices, &tmp_fields);
|
second.indices, &tmp_fields);
|
}
|
}
|
|
|
if (second.insn == NULL)
|
if (second.insn == NULL)
|
as_fatal (_("internal error: lookup/get operands failed"));
|
as_fatal (_("internal error: lookup/get operands failed"));
|
|
|
/* We assume that if the first instruction writes to a register that is
|
/* We assume that if the first instruction writes to a register that is
|
read by the second instruction it is because the programmer intended
|
read by the second instruction it is because the programmer intended
|
this to happen, (after all they have explicitly requested that these
|
this to happen, (after all they have explicitly requested that these
|
two instructions be executed in parallel). Although if the global
|
two instructions be executed in parallel). Although if the global
|
variable warn_explicit_parallel_conflicts is true then we do generate
|
variable warn_explicit_parallel_conflicts is true then we do generate
|
a warning message. Similarly we assume that parallel branch and jump
|
a warning message. Similarly we assume that parallel branch and jump
|
instructions are deliberate and should not produce errors. */
|
instructions are deliberate and should not produce errors. */
|
|
|
if (parallel_p && warn_explicit_parallel_conflicts)
|
if (parallel_p && warn_explicit_parallel_conflicts)
|
{
|
{
|
if (first_writes_to_seconds_operands (&first, &second, FALSE))
|
if (first_writes_to_seconds_operands (&first, &second, FALSE))
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
|
as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
|
|
|
if (first_writes_to_seconds_operands (&second, &first, FALSE))
|
if (first_writes_to_seconds_operands (&second, &first, FALSE))
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
|
as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
|
}
|
}
|
|
|
if (!parallel_p
|
if (!parallel_p
|
|| (errmsg = (char *) can_make_parallel (&first, &second)) == NULL)
|
|| (errmsg = (char *) can_make_parallel (&first, &second)) == NULL)
|
{
|
{
|
/* Get the fixups for the first instruction. */
|
/* Get the fixups for the first instruction. */
|
gas_cgen_swap_fixups (0);
|
gas_cgen_swap_fixups (0);
|
|
|
/* Write it out. */
|
/* Write it out. */
|
expand_debug_syms (first.debug_sym_link, 1);
|
expand_debug_syms (first.debug_sym_link, 1);
|
gas_cgen_finish_insn (first.orig_insn, first.buffer,
|
gas_cgen_finish_insn (first.orig_insn, first.buffer,
|
CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
|
CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
|
|
|
/* Force the top bit of the second insn to be set. */
|
/* Force the top bit of the second insn to be set. */
|
if (parallel_p)
|
if (parallel_p)
|
make_parallel (second.buffer);
|
make_parallel (second.buffer);
|
|
|
/* Get its fixups. */
|
/* Get its fixups. */
|
gas_cgen_restore_fixups (0);
|
gas_cgen_restore_fixups (0);
|
|
|
/* Write it out. */
|
/* Write it out. */
|
expand_debug_syms (second.debug_sym_link, 1);
|
expand_debug_syms (second.debug_sym_link, 1);
|
gas_cgen_finish_insn (second.orig_insn, second.buffer,
|
gas_cgen_finish_insn (second.orig_insn, second.buffer,
|
CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
|
CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
|
}
|
}
|
/* Try swapping the instructions to see if they work that way. */
|
/* Try swapping the instructions to see if they work that way. */
|
else if (can_make_parallel (&second, &first) == NULL)
|
else if (can_make_parallel (&second, &first) == NULL)
|
{
|
{
|
/* Write out the second instruction first. */
|
/* Write out the second instruction first. */
|
expand_debug_syms (second.debug_sym_link, 1);
|
expand_debug_syms (second.debug_sym_link, 1);
|
gas_cgen_finish_insn (second.orig_insn, second.buffer,
|
gas_cgen_finish_insn (second.orig_insn, second.buffer,
|
CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
|
CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
|
|
|
/* Force the top bit of the first instruction to be set. */
|
/* Force the top bit of the first instruction to be set. */
|
make_parallel (first.buffer);
|
make_parallel (first.buffer);
|
|
|
/* Get the fixups for the first instruction. */
|
/* Get the fixups for the first instruction. */
|
gas_cgen_restore_fixups (0);
|
gas_cgen_restore_fixups (0);
|
|
|
/* Write out the first instruction. */
|
/* Write out the first instruction. */
|
expand_debug_syms (first.debug_sym_link, 1);
|
expand_debug_syms (first.debug_sym_link, 1);
|
gas_cgen_finish_insn (first.orig_insn, first.buffer,
|
gas_cgen_finish_insn (first.orig_insn, first.buffer,
|
CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
|
CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
|
}
|
}
|
else
|
else
|
{
|
{
|
as_bad ("'%s': %s", str2, errmsg);
|
as_bad ("'%s': %s", str2, errmsg);
|
return;
|
return;
|
}
|
}
|
|
|
if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)
|
if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)
|
|| CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
|| CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
m32r_flags |= E_M32R_HAS_HIDDEN_INST;
|
m32r_flags |= E_M32R_HAS_HIDDEN_INST;
|
if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)
|
if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)
|
|| CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))
|
|| CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))
|
m32r_flags |= E_M32R_HAS_BIT_INST;
|
m32r_flags |= E_M32R_HAS_BIT_INST;
|
if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)
|
if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)
|
|| CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))
|
|| CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))
|
m32r_flags |= E_M32R_HAS_FLOAT_INST;
|
m32r_flags |= E_M32R_HAS_FLOAT_INST;
|
|
|
/* Set these so m32r_fill_insn can use them. */
|
/* Set these so m32r_fill_insn can use them. */
|
prev_seg = now_seg;
|
prev_seg = now_seg;
|
prev_subseg = now_subseg;
|
prev_subseg = now_subseg;
|
}
|
}
|
|
|
void
|
void
|
md_assemble (char *str)
|
md_assemble (char *str)
|
{
|
{
|
m32r_insn insn;
|
m32r_insn insn;
|
char *errmsg;
|
char *errmsg;
|
char *str2 = NULL;
|
char *str2 = NULL;
|
|
|
/* Initialize GAS's cgen interface for a new instruction. */
|
/* Initialize GAS's cgen interface for a new instruction. */
|
gas_cgen_init_parse ();
|
gas_cgen_init_parse ();
|
|
|
/* Look for a parallel instruction separator. */
|
/* Look for a parallel instruction separator. */
|
if ((str2 = strstr (str, "||")) != NULL)
|
if ((str2 = strstr (str, "||")) != NULL)
|
{
|
{
|
assemble_two_insns (str, str2, 1);
|
assemble_two_insns (str, str2, 1);
|
m32r_flags |= E_M32R_HAS_PARALLEL;
|
m32r_flags |= E_M32R_HAS_PARALLEL;
|
return;
|
return;
|
}
|
}
|
|
|
/* Also look for a sequential instruction separator. */
|
/* Also look for a sequential instruction separator. */
|
if ((str2 = strstr (str, "->")) != NULL)
|
if ((str2 = strstr (str, "->")) != NULL)
|
{
|
{
|
assemble_two_insns (str, str2, 0);
|
assemble_two_insns (str, str2, 0);
|
return;
|
return;
|
}
|
}
|
|
|
insn.debug_sym_link = debug_sym_link;
|
insn.debug_sym_link = debug_sym_link;
|
debug_sym_link = (sym_linkS *) 0;
|
debug_sym_link = (sym_linkS *) 0;
|
|
|
insn.insn = m32r_cgen_assemble_insn
|
insn.insn = m32r_cgen_assemble_insn
|
(gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg);
|
(gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg);
|
|
|
if (!insn.insn)
|
if (!insn.insn)
|
{
|
{
|
as_bad (errmsg);
|
as_bad (errmsg);
|
return;
|
return;
|
}
|
}
|
|
|
#ifdef E_M32R2_ARCH
|
#ifdef E_M32R2_ARCH
|
if ((enable_m32rx == 1)
|
if ((enable_m32rx == 1)
|
/* FIXME: Need standard macro to perform this test. */
|
/* FIXME: Need standard macro to perform this test. */
|
&& ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
|
&& ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
|
& (1 << MACH_M32R2))
|
& (1 << MACH_M32R2))
|
&& !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
|
&& !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
|
& (1 << MACH_M32RX)))))
|
& (1 << MACH_M32RX)))))
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("instruction '%s' is for the M32R2 only"), str);
|
as_bad (_("instruction '%s' is for the M32R2 only"), str);
|
return;
|
return;
|
}
|
}
|
else if ((! enable_special
|
else if ((! enable_special
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
|| (! enable_special_m32r
|
|| (! enable_special_m32r
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))
|
#else
|
#else
|
if (! enable_special
|
if (! enable_special
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
#endif
|
#endif
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("unknown instruction '%s'"), str);
|
as_bad (_("unknown instruction '%s'"), str);
|
return;
|
return;
|
}
|
}
|
else if (! enable_m32rx
|
else if (! enable_m32rx
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("instruction '%s' is for the M32RX only"), str);
|
as_bad (_("instruction '%s' is for the M32RX only"), str);
|
return;
|
return;
|
}
|
}
|
|
|
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
m32r_flags |= E_M32R_HAS_HIDDEN_INST;
|
m32r_flags |= E_M32R_HAS_HIDDEN_INST;
|
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))
|
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))
|
m32r_flags |= E_M32R_HAS_BIT_INST;
|
m32r_flags |= E_M32R_HAS_BIT_INST;
|
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))
|
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))
|
m32r_flags |= E_M32R_HAS_FLOAT_INST;
|
m32r_flags |= E_M32R_HAS_FLOAT_INST;
|
|
|
if (CGEN_INSN_BITSIZE (insn.insn) == 32)
|
if (CGEN_INSN_BITSIZE (insn.insn) == 32)
|
{
|
{
|
/* 32 bit insns must live on 32 bit boundaries. */
|
/* 32 bit insns must live on 32 bit boundaries. */
|
if (prev_insn.insn || seen_relaxable_p)
|
if (prev_insn.insn || seen_relaxable_p)
|
{
|
{
|
/* ??? If calling fill_insn too many times turns us into a memory
|
/* ??? If calling fill_insn too many times turns us into a memory
|
pig, can we call a fn to assemble a nop instead of
|
pig, can we call a fn to assemble a nop instead of
|
!seen_relaxable_p? */
|
!seen_relaxable_p? */
|
fill_insn (0);
|
fill_insn (0);
|
}
|
}
|
|
|
expand_debug_syms (insn.debug_sym_link, 2);
|
expand_debug_syms (insn.debug_sym_link, 2);
|
|
|
/* Doesn't really matter what we pass for RELAX_P here. */
|
/* Doesn't really matter what we pass for RELAX_P here. */
|
gas_cgen_finish_insn (insn.insn, insn.buffer,
|
gas_cgen_finish_insn (insn.insn, insn.buffer,
|
CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL);
|
CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL);
|
}
|
}
|
else
|
else
|
{
|
{
|
int on_32bit_boundary_p;
|
int on_32bit_boundary_p;
|
int swap = FALSE;
|
int swap = FALSE;
|
|
|
if (CGEN_INSN_BITSIZE (insn.insn) != 16)
|
if (CGEN_INSN_BITSIZE (insn.insn) != 16)
|
abort ();
|
abort ();
|
|
|
insn.orig_insn = insn.insn;
|
insn.orig_insn = insn.insn;
|
|
|
/* If the previous insn was relaxable, then it may be expanded
|
/* If the previous insn was relaxable, then it may be expanded
|
to fill the current 16 bit slot. Emit a NOP here to occupy
|
to fill the current 16 bit slot. Emit a NOP here to occupy
|
this slot, so that we can start at optimizing at a 32 bit
|
this slot, so that we can start at optimizing at a 32 bit
|
boundary. */
|
boundary. */
|
if (prev_insn.insn && seen_relaxable_p && optimize)
|
if (prev_insn.insn && seen_relaxable_p && optimize)
|
fill_insn (0);
|
fill_insn (0);
|
|
|
if (enable_m32rx)
|
if (enable_m32rx)
|
{
|
{
|
/* Get the indices of the operands of the instruction.
|
/* Get the indices of the operands of the instruction.
|
FIXME: See assemble_parallel for notes on orig_insn. */
|
FIXME: See assemble_parallel for notes on orig_insn. */
|
{
|
{
|
CGEN_FIELDS tmp_fields;
|
CGEN_FIELDS tmp_fields;
|
insn.insn = cgen_lookup_get_insn_operands
|
insn.insn = cgen_lookup_get_insn_operands
|
(gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
|
(gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
|
16, insn.indices, &tmp_fields);
|
16, insn.indices, &tmp_fields);
|
}
|
}
|
|
|
if (insn.insn == NULL)
|
if (insn.insn == NULL)
|
as_fatal (_("internal error: lookup/get operands failed"));
|
as_fatal (_("internal error: lookup/get operands failed"));
|
}
|
}
|
|
|
/* Compute whether we're on a 32 bit boundary or not.
|
/* Compute whether we're on a 32 bit boundary or not.
|
prev_insn.insn is NULL when we're on a 32 bit boundary. */
|
prev_insn.insn is NULL when we're on a 32 bit boundary. */
|
on_32bit_boundary_p = prev_insn.insn == NULL;
|
on_32bit_boundary_p = prev_insn.insn == NULL;
|
|
|
/* Change a frag to, if each insn to swap is in a different frag.
|
/* Change a frag to, if each insn to swap is in a different frag.
|
It must keep only one instruction in a frag. */
|
It must keep only one instruction in a frag. */
|
if (parallel() && on_32bit_boundary_p)
|
if (parallel() && on_32bit_boundary_p)
|
{
|
{
|
frag_wane (frag_now);
|
frag_wane (frag_now);
|
frag_new (0);
|
frag_new (0);
|
}
|
}
|
|
|
/* Look to see if this instruction can be combined with the
|
/* Look to see if this instruction can be combined with the
|
previous instruction to make one, parallel, 32 bit instruction.
|
previous instruction to make one, parallel, 32 bit instruction.
|
If the previous instruction (potentially) changed the flow of
|
If the previous instruction (potentially) changed the flow of
|
program control, then it cannot be combined with the current
|
program control, then it cannot be combined with the current
|
instruction. If the current instruction is relaxable, then it
|
instruction. If the current instruction is relaxable, then it
|
might be replaced with a longer version, so we cannot combine it.
|
might be replaced with a longer version, so we cannot combine it.
|
Also if the output of the previous instruction is used as an
|
Also if the output of the previous instruction is used as an
|
input to the current instruction then it cannot be combined.
|
input to the current instruction then it cannot be combined.
|
Otherwise call can_make_parallel() with both orderings of the
|
Otherwise call can_make_parallel() with both orderings of the
|
instructions to see if they can be combined. */
|
instructions to see if they can be combined. */
|
if (! on_32bit_boundary_p
|
if (! on_32bit_boundary_p
|
&& parallel ()
|
&& parallel ()
|
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
|
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
|
&& ! writes_to_pc (&prev_insn)
|
&& ! writes_to_pc (&prev_insn)
|
&& ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
|
&& ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
|
{
|
{
|
if (can_make_parallel (&prev_insn, &insn) == NULL)
|
if (can_make_parallel (&prev_insn, &insn) == NULL)
|
make_parallel (insn.buffer);
|
make_parallel (insn.buffer);
|
else if (can_make_parallel (&insn, &prev_insn) == NULL)
|
else if (can_make_parallel (&insn, &prev_insn) == NULL)
|
swap = TRUE;
|
swap = TRUE;
|
}
|
}
|
|
|
expand_debug_syms (insn.debug_sym_link, 1);
|
expand_debug_syms (insn.debug_sym_link, 1);
|
|
|
{
|
{
|
int i;
|
int i;
|
finished_insnS fi;
|
finished_insnS fi;
|
|
|
/* Ensure each pair of 16 bit insns is in the same frag. */
|
/* Ensure each pair of 16 bit insns is in the same frag. */
|
frag_grow (4);
|
frag_grow (4);
|
|
|
gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
|
gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
|
CGEN_FIELDS_BITSIZE (&insn.fields),
|
CGEN_FIELDS_BITSIZE (&insn.fields),
|
1 /* relax_p */, &fi);
|
1 /* relax_p */, &fi);
|
insn.addr = fi.addr;
|
insn.addr = fi.addr;
|
insn.frag = fi.frag;
|
insn.frag = fi.frag;
|
insn.num_fixups = fi.num_fixups;
|
insn.num_fixups = fi.num_fixups;
|
for (i = 0; i < fi.num_fixups; ++i)
|
for (i = 0; i < fi.num_fixups; ++i)
|
insn.fixups[i] = fi.fixups[i];
|
insn.fixups[i] = fi.fixups[i];
|
}
|
}
|
|
|
if (swap)
|
if (swap)
|
{
|
{
|
int i, tmp;
|
int i, tmp;
|
|
|
#define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
|
#define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
|
|
|
/* Swap the two insns */
|
/* Swap the two insns */
|
SWAP_BYTES (prev_insn.addr[0], insn.addr[0]);
|
SWAP_BYTES (prev_insn.addr[0], insn.addr[0]);
|
SWAP_BYTES (prev_insn.addr[1], insn.addr[1]);
|
SWAP_BYTES (prev_insn.addr[1], insn.addr[1]);
|
|
|
target_make_parallel (insn.addr);
|
target_make_parallel (insn.addr);
|
|
|
/* Swap any relaxable frags recorded for the two insns. */
|
/* Swap any relaxable frags recorded for the two insns. */
|
/* FIXME: Clarify. relaxation precludes parallel insns */
|
/* FIXME: Clarify. relaxation precludes parallel insns */
|
if (prev_insn.frag->fr_opcode == prev_insn.addr)
|
if (prev_insn.frag->fr_opcode == prev_insn.addr)
|
prev_insn.frag->fr_opcode = insn.addr;
|
prev_insn.frag->fr_opcode = insn.addr;
|
else if (insn.frag->fr_opcode == insn.addr)
|
else if (insn.frag->fr_opcode == insn.addr)
|
insn.frag->fr_opcode = prev_insn.addr;
|
insn.frag->fr_opcode = prev_insn.addr;
|
|
|
/* Change a frag to, if each insn is in a different frag.
|
/* Change a frag to, if each insn is in a different frag.
|
It must keep only one instruction in a frag. */
|
It must keep only one instruction in a frag. */
|
if (prev_insn.frag != insn.frag)
|
if (prev_insn.frag != insn.frag)
|
{
|
{
|
for (i = 0; i < prev_insn.num_fixups; ++i)
|
for (i = 0; i < prev_insn.num_fixups; ++i)
|
prev_insn.fixups[i]->fx_frag = insn.frag;
|
prev_insn.fixups[i]->fx_frag = insn.frag;
|
for (i = 0; i < insn.num_fixups; ++i)
|
for (i = 0; i < insn.num_fixups; ++i)
|
insn.fixups[i]->fx_frag = prev_insn.frag;
|
insn.fixups[i]->fx_frag = prev_insn.frag;
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Update the addresses in any fixups.
|
/* Update the addresses in any fixups.
|
Note that we don't have to handle the case where each insn is in
|
Note that we don't have to handle the case where each insn is in
|
a different frag as we ensure they're in the same frag above. */
|
a different frag as we ensure they're in the same frag above. */
|
for (i = 0; i < prev_insn.num_fixups; ++i)
|
for (i = 0; i < prev_insn.num_fixups; ++i)
|
prev_insn.fixups[i]->fx_where += 2;
|
prev_insn.fixups[i]->fx_where += 2;
|
for (i = 0; i < insn.num_fixups; ++i)
|
for (i = 0; i < insn.num_fixups; ++i)
|
insn.fixups[i]->fx_where -= 2;
|
insn.fixups[i]->fx_where -= 2;
|
}
|
}
|
}
|
}
|
|
|
/* Keep track of whether we've seen a pair of 16 bit insns.
|
/* Keep track of whether we've seen a pair of 16 bit insns.
|
prev_insn.insn is NULL when we're on a 32 bit boundary. */
|
prev_insn.insn is NULL when we're on a 32 bit boundary. */
|
if (on_32bit_boundary_p)
|
if (on_32bit_boundary_p)
|
prev_insn = insn;
|
prev_insn = insn;
|
else
|
else
|
prev_insn.insn = NULL;
|
prev_insn.insn = NULL;
|
|
|
/* If the insn needs the following one to be on a 32 bit boundary
|
/* If the insn needs the following one to be on a 32 bit boundary
|
(e.g. subroutine calls), fill this insn's slot. */
|
(e.g. subroutine calls), fill this insn's slot. */
|
if (on_32bit_boundary_p
|
if (on_32bit_boundary_p
|
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
|
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
|
fill_insn (0);
|
fill_insn (0);
|
|
|
/* If this is a relaxable insn (can be replaced with a larger version)
|
/* If this is a relaxable insn (can be replaced with a larger version)
|
mark the fact so that we can emit an alignment directive for a
|
mark the fact so that we can emit an alignment directive for a
|
following 32 bit insn if we see one. */
|
following 32 bit insn if we see one. */
|
if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
|
if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
|
seen_relaxable_p = 1;
|
seen_relaxable_p = 1;
|
}
|
}
|
|
|
/* Set these so m32r_fill_insn can use them. */
|
/* Set these so m32r_fill_insn can use them. */
|
prev_seg = now_seg;
|
prev_seg = now_seg;
|
prev_subseg = now_subseg;
|
prev_subseg = now_subseg;
|
}
|
}
|
|
|
/* The syntax in the manual says constants begin with '#'.
|
/* The syntax in the manual says constants begin with '#'.
|
We just ignore it. */
|
We just ignore it. */
|
|
|
void
|
void
|
md_operand (expressionS *expressionP)
|
md_operand (expressionS *expressionP)
|
{
|
{
|
if (*input_line_pointer == '#')
|
if (*input_line_pointer == '#')
|
{
|
{
|
input_line_pointer++;
|
input_line_pointer++;
|
expression (expressionP);
|
expression (expressionP);
|
}
|
}
|
}
|
}
|
|
|
valueT
|
valueT
|
md_section_align (segT segment, valueT size)
|
md_section_align (segT segment, valueT size)
|
{
|
{
|
int align = bfd_get_section_alignment (stdoutput, segment);
|
int align = bfd_get_section_alignment (stdoutput, segment);
|
|
|
return ((size + (1 << align) - 1) & (-1 << align));
|
return ((size + (1 << align) - 1) & (-1 << align));
|
}
|
}
|
|
|
symbolS *
|
symbolS *
|
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
|
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
|
{
|
{
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* .scomm pseudo-op handler.
|
/* .scomm pseudo-op handler.
|
|
|
This is a new pseudo-op to handle putting objects in .scommon.
|
This is a new pseudo-op to handle putting objects in .scommon.
|
By doing this the linker won't need to do any work,
|
By doing this the linker won't need to do any work,
|
and more importantly it removes the implicit -G arg necessary to
|
and more importantly it removes the implicit -G arg necessary to
|
correctly link the object file. */
|
correctly link the object file. */
|
|
|
static void
|
static void
|
m32r_scomm (int ignore ATTRIBUTE_UNUSED)
|
m32r_scomm (int ignore ATTRIBUTE_UNUSED)
|
{
|
{
|
char *name;
|
char *name;
|
char c;
|
char c;
|
char *p;
|
char *p;
|
offsetT size;
|
offsetT size;
|
symbolS *symbolP;
|
symbolS *symbolP;
|
offsetT align;
|
offsetT align;
|
int align2;
|
int align2;
|
|
|
name = input_line_pointer;
|
name = input_line_pointer;
|
c = get_symbol_end ();
|
c = get_symbol_end ();
|
|
|
/* Just after name is now '\0'. */
|
/* Just after name is now '\0'. */
|
p = input_line_pointer;
|
p = input_line_pointer;
|
*p = c;
|
*p = c;
|
SKIP_WHITESPACE ();
|
SKIP_WHITESPACE ();
|
if (*input_line_pointer != ',')
|
if (*input_line_pointer != ',')
|
{
|
{
|
as_bad (_("Expected comma after symbol-name: rest of line ignored."));
|
as_bad (_("Expected comma after symbol-name: rest of line ignored."));
|
ignore_rest_of_line ();
|
ignore_rest_of_line ();
|
return;
|
return;
|
}
|
}
|
|
|
/* Skip ','. */
|
/* Skip ','. */
|
input_line_pointer++;
|
input_line_pointer++;
|
if ((size = get_absolute_expression ()) < 0)
|
if ((size = get_absolute_expression ()) < 0)
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
|
as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
|
ignore_rest_of_line ();
|
ignore_rest_of_line ();
|
return;
|
return;
|
}
|
}
|
|
|
/* The third argument to .scomm is the alignment. */
|
/* The third argument to .scomm is the alignment. */
|
if (*input_line_pointer != ',')
|
if (*input_line_pointer != ',')
|
align = 8;
|
align = 8;
|
else
|
else
|
{
|
{
|
++input_line_pointer;
|
++input_line_pointer;
|
align = get_absolute_expression ();
|
align = get_absolute_expression ();
|
if (align <= 0)
|
if (align <= 0)
|
{
|
{
|
as_warn (_("ignoring bad alignment"));
|
as_warn (_("ignoring bad alignment"));
|
align = 8;
|
align = 8;
|
}
|
}
|
}
|
}
|
|
|
/* Convert to a power of 2 alignment. */
|
/* Convert to a power of 2 alignment. */
|
if (align)
|
if (align)
|
{
|
{
|
for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
|
for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
|
continue;
|
continue;
|
if (align != 1)
|
if (align != 1)
|
{
|
{
|
as_bad (_("Common alignment not a power of 2"));
|
as_bad (_("Common alignment not a power of 2"));
|
ignore_rest_of_line ();
|
ignore_rest_of_line ();
|
return;
|
return;
|
}
|
}
|
}
|
}
|
else
|
else
|
align2 = 0;
|
align2 = 0;
|
|
|
*p = 0;
|
*p = 0;
|
symbolP = symbol_find_or_make (name);
|
symbolP = symbol_find_or_make (name);
|
*p = c;
|
*p = c;
|
|
|
if (S_IS_DEFINED (symbolP))
|
if (S_IS_DEFINED (symbolP))
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("Ignoring attempt to re-define symbol `%s'."),
|
as_bad (_("Ignoring attempt to re-define symbol `%s'."),
|
S_GET_NAME (symbolP));
|
S_GET_NAME (symbolP));
|
ignore_rest_of_line ();
|
ignore_rest_of_line ();
|
return;
|
return;
|
}
|
}
|
|
|
if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
|
if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
|
{
|
{
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
|
as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
|
S_GET_NAME (symbolP),
|
S_GET_NAME (symbolP),
|
(long) S_GET_VALUE (symbolP),
|
(long) S_GET_VALUE (symbolP),
|
(long) size);
|
(long) size);
|
|
|
ignore_rest_of_line ();
|
ignore_rest_of_line ();
|
return;
|
return;
|
}
|
}
|
|
|
if (symbol_get_obj (symbolP)->local)
|
if (symbol_get_obj (symbolP)->local)
|
{
|
{
|
segT old_sec = now_seg;
|
segT old_sec = now_seg;
|
int old_subsec = now_subseg;
|
int old_subsec = now_subseg;
|
char *pfrag;
|
char *pfrag;
|
|
|
record_alignment (sbss_section, align2);
|
record_alignment (sbss_section, align2);
|
subseg_set (sbss_section, 0);
|
subseg_set (sbss_section, 0);
|
|
|
if (align2)
|
if (align2)
|
frag_align (align2, 0, 0);
|
frag_align (align2, 0, 0);
|
|
|
if (S_GET_SEGMENT (symbolP) == sbss_section)
|
if (S_GET_SEGMENT (symbolP) == sbss_section)
|
symbol_get_frag (symbolP)->fr_symbol = 0;
|
symbol_get_frag (symbolP)->fr_symbol = 0;
|
|
|
symbol_set_frag (symbolP, frag_now);
|
symbol_set_frag (symbolP, frag_now);
|
|
|
pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
|
pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
|
(char *) 0);
|
(char *) 0);
|
*pfrag = 0;
|
*pfrag = 0;
|
S_SET_SIZE (symbolP, size);
|
S_SET_SIZE (symbolP, size);
|
S_SET_SEGMENT (symbolP, sbss_section);
|
S_SET_SEGMENT (symbolP, sbss_section);
|
S_CLEAR_EXTERNAL (symbolP);
|
S_CLEAR_EXTERNAL (symbolP);
|
subseg_set (old_sec, old_subsec);
|
subseg_set (old_sec, old_subsec);
|
}
|
}
|
else
|
else
|
{
|
{
|
S_SET_VALUE (symbolP, (valueT) size);
|
S_SET_VALUE (symbolP, (valueT) size);
|
S_SET_ALIGN (symbolP, align2);
|
S_SET_ALIGN (symbolP, align2);
|
S_SET_EXTERNAL (symbolP);
|
S_SET_EXTERNAL (symbolP);
|
S_SET_SEGMENT (symbolP, &scom_section);
|
S_SET_SEGMENT (symbolP, &scom_section);
|
}
|
}
|
|
|
demand_empty_rest_of_line ();
|
demand_empty_rest_of_line ();
|
}
|
}
|
|
|
/* The target specific pseudo-ops which we support. */
|
/* The target specific pseudo-ops which we support. */
|
const pseudo_typeS md_pseudo_table[] =
|
const pseudo_typeS md_pseudo_table[] =
|
{
|
{
|
{ "word", cons, 4 },
|
{ "word", cons, 4 },
|
{ "fillinsn", fill_insn, 0 },
|
{ "fillinsn", fill_insn, 0 },
|
{ "scomm", m32r_scomm, 0 },
|
{ "scomm", m32r_scomm, 0 },
|
{ "debugsym", debug_sym, 0 },
|
{ "debugsym", debug_sym, 0 },
|
{ "m32r", allow_m32rx, 0 },
|
{ "m32r", allow_m32rx, 0 },
|
{ "m32rx", allow_m32rx, 1 },
|
{ "m32rx", allow_m32rx, 1 },
|
{ "m32r2", allow_m32rx, 2 },
|
{ "m32r2", allow_m32rx, 2 },
|
{ "little", little, 1 },
|
{ "little", little, 1 },
|
{ "big", little, 0 },
|
{ "big", little, 0 },
|
{ NULL, NULL, 0 }
|
{ NULL, NULL, 0 }
|
};
|
};
|
|
|
/* Interface to relax_segment. */
|
/* Interface to relax_segment. */
|
|
|
/* FIXME: Build table by hand, get it working, then machine generate. */
|
/* FIXME: Build table by hand, get it working, then machine generate. */
|
|
|
const relax_typeS md_relax_table[] =
|
const relax_typeS md_relax_table[] =
|
{
|
{
|
/* The fields are:
|
/* The fields are:
|
1) most positive reach of this state,
|
1) most positive reach of this state,
|
2) most negative reach of this state,
|
2) most negative reach of this state,
|
3) how many bytes this mode will add to the size of the current frag
|
3) how many bytes this mode will add to the size of the current frag
|
4) which index into the table to try if we can't fit into this one. */
|
4) which index into the table to try if we can't fit into this one. */
|
|
|
/* The first entry must be unused because an `rlx_more' value of zero ends
|
/* The first entry must be unused because an `rlx_more' value of zero ends
|
each list. */
|
each list. */
|
{1, 1, 0, 0},
|
{1, 1, 0, 0},
|
|
|
/* The displacement used by GAS is from the end of the 2 byte insn,
|
/* The displacement used by GAS is from the end of the 2 byte insn,
|
so we subtract 2 from the following. */
|
so we subtract 2 from the following. */
|
/* 16 bit insn, 8 bit disp -> 10 bit range.
|
/* 16 bit insn, 8 bit disp -> 10 bit range.
|
This doesn't handle a branch in the right slot at the border:
|
This doesn't handle a branch in the right slot at the border:
|
the "& -4" isn't taken into account. It's not important enough to
|
the "& -4" isn't taken into account. It's not important enough to
|
complicate things over it, so we subtract an extra 2 (or + 2 in -ve
|
complicate things over it, so we subtract an extra 2 (or + 2 in -ve
|
case). */
|
case). */
|
{511 - 2 - 2, -512 - 2 + 2, 0, 2 },
|
{511 - 2 - 2, -512 - 2 + 2, 0, 2 },
|
/* 32 bit insn, 24 bit disp -> 26 bit range. */
|
/* 32 bit insn, 24 bit disp -> 26 bit range. */
|
{0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
|
{0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
|
/* Same thing, but with leading nop for alignment. */
|
/* Same thing, but with leading nop for alignment. */
|
{0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
|
{0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
|
};
|
};
|
|
|
long
|
long
|
m32r_relax_frag (segT segment, fragS *fragP, long stretch)
|
m32r_relax_frag (segT segment, fragS *fragP, long stretch)
|
{
|
{
|
/* Address of branch insn. */
|
/* Address of branch insn. */
|
long address = fragP->fr_address + fragP->fr_fix - 2;
|
long address = fragP->fr_address + fragP->fr_fix - 2;
|
long growth = 0;
|
long growth = 0;
|
|
|
/* Keep 32 bit insns aligned on 32 bit boundaries. */
|
/* Keep 32 bit insns aligned on 32 bit boundaries. */
|
if (fragP->fr_subtype == 2)
|
if (fragP->fr_subtype == 2)
|
{
|
{
|
if ((address & 3) != 0)
|
if ((address & 3) != 0)
|
{
|
{
|
fragP->fr_subtype = 3;
|
fragP->fr_subtype = 3;
|
growth = 2;
|
growth = 2;
|
}
|
}
|
}
|
}
|
else if (fragP->fr_subtype == 3)
|
else if (fragP->fr_subtype == 3)
|
{
|
{
|
if ((address & 3) == 0)
|
if ((address & 3) == 0)
|
{
|
{
|
fragP->fr_subtype = 2;
|
fragP->fr_subtype = 2;
|
growth = -2;
|
growth = -2;
|
}
|
}
|
}
|
}
|
else
|
else
|
{
|
{
|
growth = relax_frag (segment, fragP, stretch);
|
growth = relax_frag (segment, fragP, stretch);
|
|
|
/* Long jump on odd halfword boundary? */
|
/* Long jump on odd halfword boundary? */
|
if (fragP->fr_subtype == 2 && (address & 3) != 0)
|
if (fragP->fr_subtype == 2 && (address & 3) != 0)
|
{
|
{
|
fragP->fr_subtype = 3;
|
fragP->fr_subtype = 3;
|
growth += 2;
|
growth += 2;
|
}
|
}
|
}
|
}
|
|
|
return growth;
|
return growth;
|
}
|
}
|
|
|
/* Return an initial guess of the length by which a fragment must grow to
|
/* Return an initial guess of the length by which a fragment must grow to
|
hold a branch to reach its destination.
|
hold a branch to reach its destination.
|
Also updates fr_type/fr_subtype as necessary.
|
Also updates fr_type/fr_subtype as necessary.
|
|
|
Called just before doing relaxation.
|
Called just before doing relaxation.
|
Any symbol that is now undefined will not become defined.
|
Any symbol that is now undefined will not become defined.
|
The guess for fr_var is ACTUALLY the growth beyond fr_fix.
|
The guess for fr_var is ACTUALLY the growth beyond fr_fix.
|
Whatever we do to grow fr_fix or fr_var contributes to our returned value.
|
Whatever we do to grow fr_fix or fr_var contributes to our returned value.
|
Although it may not be explicit in the frag, pretend fr_var starts
|
Although it may not be explicit in the frag, pretend fr_var starts
|
with a 0 value. */
|
with a 0 value. */
|
|
|
int
|
int
|
md_estimate_size_before_relax (fragS *fragP, segT segment)
|
md_estimate_size_before_relax (fragS *fragP, segT segment)
|
{
|
{
|
/* The only thing we have to handle here are symbols outside of the
|
/* The only thing we have to handle here are symbols outside of the
|
current segment. They may be undefined or in a different segment in
|
current segment. They may be undefined or in a different segment in
|
which case linker scripts may place them anywhere.
|
which case linker scripts may place them anywhere.
|
However, we can't finish the fragment here and emit the reloc as insn
|
However, we can't finish the fragment here and emit the reloc as insn
|
alignment requirements may move the insn about. */
|
alignment requirements may move the insn about. */
|
if (S_GET_SEGMENT (fragP->fr_symbol) != segment
|
if (S_GET_SEGMENT (fragP->fr_symbol) != segment
|
|| S_IS_EXTERNAL (fragP->fr_symbol)
|
|| S_IS_EXTERNAL (fragP->fr_symbol)
|
|| S_IS_WEAK (fragP->fr_symbol))
|
|| S_IS_WEAK (fragP->fr_symbol))
|
{
|
{
|
/* The symbol is undefined in this segment.
|
/* The symbol is undefined in this segment.
|
Change the relaxation subtype to the max allowable and leave
|
Change the relaxation subtype to the max allowable and leave
|
all further handling to md_convert_frag. */
|
all further handling to md_convert_frag. */
|
fragP->fr_subtype = 2;
|
fragP->fr_subtype = 2;
|
|
|
{
|
{
|
const CGEN_INSN *insn;
|
const CGEN_INSN *insn;
|
int i;
|
int i;
|
|
|
/* Update the recorded insn.
|
/* Update the recorded insn.
|
Fortunately we don't have to look very far.
|
Fortunately we don't have to look very far.
|
FIXME: Change this to record in the instruction the next higher
|
FIXME: Change this to record in the instruction the next higher
|
relaxable insn to use. */
|
relaxable insn to use. */
|
for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
|
for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
|
{
|
{
|
if ((strcmp (CGEN_INSN_MNEMONIC (insn),
|
if ((strcmp (CGEN_INSN_MNEMONIC (insn),
|
CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
|
CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
|
== 0)
|
== 0)
|
&& CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
|
&& CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
|
break;
|
break;
|
}
|
}
|
if (i == 4)
|
if (i == 4)
|
abort ();
|
abort ();
|
|
|
fragP->fr_cgen.insn = insn;
|
fragP->fr_cgen.insn = insn;
|
return 2;
|
return 2;
|
}
|
}
|
}
|
}
|
|
|
return md_relax_table[fragP->fr_subtype].rlx_length;
|
return md_relax_table[fragP->fr_subtype].rlx_length;
|
}
|
}
|
|
|
/* *FRAGP has been relaxed to its final size, and now needs to have
|
/* *FRAGP has been relaxed to its final size, and now needs to have
|
the bytes inside it modified to conform to the new size.
|
the bytes inside it modified to conform to the new size.
|
|
|
Called after relaxation is finished.
|
Called after relaxation is finished.
|
fragP->fr_type == rs_machine_dependent.
|
fragP->fr_type == rs_machine_dependent.
|
fragP->fr_subtype is the subtype of what the address relaxed to. */
|
fragP->fr_subtype is the subtype of what the address relaxed to. */
|
|
|
void
|
void
|
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
|
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
|
segT sec,
|
segT sec,
|
fragS *fragP)
|
fragS *fragP)
|
{
|
{
|
char *opcode;
|
char *opcode;
|
char *displacement;
|
char *displacement;
|
int target_address;
|
int target_address;
|
int opcode_address;
|
int opcode_address;
|
int extension;
|
int extension;
|
int addend;
|
int addend;
|
|
|
opcode = fragP->fr_opcode;
|
opcode = fragP->fr_opcode;
|
|
|
/* Address opcode resides at in file space. */
|
/* Address opcode resides at in file space. */
|
opcode_address = fragP->fr_address + fragP->fr_fix - 2;
|
opcode_address = fragP->fr_address + fragP->fr_fix - 2;
|
|
|
switch (fragP->fr_subtype)
|
switch (fragP->fr_subtype)
|
{
|
{
|
case 1:
|
case 1:
|
extension = 0;
|
extension = 0;
|
displacement = &opcode[1];
|
displacement = &opcode[1];
|
break;
|
break;
|
case 2:
|
case 2:
|
opcode[0] |= 0x80;
|
opcode[0] |= 0x80;
|
extension = 2;
|
extension = 2;
|
displacement = &opcode[1];
|
displacement = &opcode[1];
|
break;
|
break;
|
case 3:
|
case 3:
|
opcode[2] = opcode[0] | 0x80;
|
opcode[2] = opcode[0] | 0x80;
|
md_number_to_chars (opcode, PAR_NOP_INSN, 2);
|
md_number_to_chars (opcode, PAR_NOP_INSN, 2);
|
opcode_address += 2;
|
opcode_address += 2;
|
extension = 4;
|
extension = 4;
|
displacement = &opcode[3];
|
displacement = &opcode[3];
|
break;
|
break;
|
default:
|
default:
|
abort ();
|
abort ();
|
}
|
}
|
|
|
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|
|| S_IS_EXTERNAL (fragP->fr_symbol)
|
|| S_IS_EXTERNAL (fragP->fr_symbol)
|
|| S_IS_WEAK (fragP->fr_symbol))
|
|| S_IS_WEAK (fragP->fr_symbol))
|
{
|
{
|
/* Symbol must be resolved by linker. */
|
/* Symbol must be resolved by linker. */
|
if (fragP->fr_offset & 3)
|
if (fragP->fr_offset & 3)
|
as_warn (_("Addend to unresolved symbol not on word boundary."));
|
as_warn (_("Addend to unresolved symbol not on word boundary."));
|
#ifdef USE_M32R_OLD_RELOC
|
#ifdef USE_M32R_OLD_RELOC
|
addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */
|
addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */
|
#else
|
#else
|
addend = 0;
|
addend = 0;
|
#endif
|
#endif
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Address we want to reach in file space. */
|
/* Address we want to reach in file space. */
|
target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
|
target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
|
addend = (target_address - (opcode_address & -4)) >> 2;
|
addend = (target_address - (opcode_address & -4)) >> 2;
|
}
|
}
|
|
|
/* Create a relocation for symbols that must be resolved by the linker.
|
/* Create a relocation for symbols that must be resolved by the linker.
|
Otherwise output the completed insn. */
|
Otherwise output the completed insn. */
|
|
|
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|
|| S_IS_EXTERNAL (fragP->fr_symbol)
|
|| S_IS_EXTERNAL (fragP->fr_symbol)
|
|| S_IS_WEAK (fragP->fr_symbol))
|
|| S_IS_WEAK (fragP->fr_symbol))
|
{
|
{
|
fixS *fixP;
|
fixS *fixP;
|
|
|
assert (fragP->fr_subtype != 1);
|
assert (fragP->fr_subtype != 1);
|
assert (fragP->fr_cgen.insn != 0);
|
assert (fragP->fr_cgen.insn != 0);
|
|
|
fixP = gas_cgen_record_fixup (fragP,
|
fixP = gas_cgen_record_fixup (fragP,
|
/* Offset of branch insn in frag. */
|
/* Offset of branch insn in frag. */
|
fragP->fr_fix + extension - 4,
|
fragP->fr_fix + extension - 4,
|
fragP->fr_cgen.insn,
|
fragP->fr_cgen.insn,
|
4 /* Length. */,
|
4 /* Length. */,
|
/* FIXME: quick hack. */
|
/* FIXME: quick hack. */
|
cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
|
cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
|
M32R_OPERAND_DISP24),
|
M32R_OPERAND_DISP24),
|
fragP->fr_cgen.opinfo,
|
fragP->fr_cgen.opinfo,
|
fragP->fr_symbol, fragP->fr_offset);
|
fragP->fr_symbol, fragP->fr_offset);
|
if (fragP->fr_cgen.opinfo)
|
if (fragP->fr_cgen.opinfo)
|
fixP->fx_r_type = fragP->fr_cgen.opinfo;
|
fixP->fx_r_type = fragP->fr_cgen.opinfo;
|
}
|
}
|
|
|
#define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
|
#define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
|
|
|
md_number_to_chars (displacement, (valueT) addend,
|
md_number_to_chars (displacement, (valueT) addend,
|
SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
|
SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
|
|
|
fragP->fr_fix += extension;
|
fragP->fr_fix += extension;
|
}
|
}
|
|
|
/* Functions concerning relocs. */
|
/* Functions concerning relocs. */
|
|
|
/* The location from which a PC relative jump should be calculated,
|
/* The location from which a PC relative jump should be calculated,
|
given a PC relative reloc. */
|
given a PC relative reloc. */
|
|
|
long
|
long
|
md_pcrel_from_section (fixS *fixP, segT sec)
|
md_pcrel_from_section (fixS *fixP, segT sec)
|
{
|
{
|
if (fixP->fx_addsy != (symbolS *) NULL
|
if (fixP->fx_addsy != (symbolS *) NULL
|
&& (! S_IS_DEFINED (fixP->fx_addsy)
|
&& (! S_IS_DEFINED (fixP->fx_addsy)
|
|| S_GET_SEGMENT (fixP->fx_addsy) != sec
|
|| S_GET_SEGMENT (fixP->fx_addsy) != sec
|
|| S_IS_EXTERNAL (fixP->fx_addsy)
|
|| S_IS_EXTERNAL (fixP->fx_addsy)
|
|| S_IS_WEAK (fixP->fx_addsy)))
|
|| S_IS_WEAK (fixP->fx_addsy)))
|
{
|
{
|
if (S_GET_SEGMENT (fixP->fx_addsy) != sec
|
if (S_GET_SEGMENT (fixP->fx_addsy) != sec
|
&& S_IS_DEFINED (fixP->fx_addsy)
|
&& S_IS_DEFINED (fixP->fx_addsy)
|
&& ! S_IS_EXTERNAL (fixP->fx_addsy)
|
&& ! S_IS_EXTERNAL (fixP->fx_addsy)
|
&& ! S_IS_WEAK (fixP->fx_addsy))
|
&& ! S_IS_WEAK (fixP->fx_addsy))
|
return fixP->fx_offset;
|
return fixP->fx_offset;
|
|
|
/* The symbol is undefined (or is defined but not in this section).
|
/* The symbol is undefined (or is defined but not in this section).
|
Let the linker figure it out. */
|
Let the linker figure it out. */
|
return 0;
|
return 0;
|
}
|
}
|
|
|
return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
|
return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
|
}
|
}
|
|
|
/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
|
/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
|
Returns BFD_RELOC_NONE if no reloc type can be found.
|
Returns BFD_RELOC_NONE if no reloc type can be found.
|
*FIXP may be modified if desired. */
|
*FIXP may be modified if desired. */
|
|
|
bfd_reloc_code_real_type
|
bfd_reloc_code_real_type
|
md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
|
md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
|
const CGEN_OPERAND *operand,
|
const CGEN_OPERAND *operand,
|
fixS *fixP)
|
fixS *fixP)
|
{
|
{
|
switch (operand->type)
|
switch (operand->type)
|
{
|
{
|
case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL;
|
case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL;
|
case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL;
|
case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL;
|
case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL;
|
case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL;
|
case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24;
|
case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24;
|
case M32R_OPERAND_HI16:
|
case M32R_OPERAND_HI16:
|
case M32R_OPERAND_SLO16:
|
case M32R_OPERAND_SLO16:
|
case M32R_OPERAND_ULO16:
|
case M32R_OPERAND_ULO16:
|
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
|
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
|
if (fixP->fx_cgen.opinfo != 0)
|
if (fixP->fx_cgen.opinfo != 0)
|
return fixP->fx_cgen.opinfo;
|
return fixP->fx_cgen.opinfo;
|
break;
|
break;
|
default:
|
default:
|
/* Avoid -Wall warning. */
|
/* Avoid -Wall warning. */
|
break;
|
break;
|
}
|
}
|
return BFD_RELOC_NONE;
|
return BFD_RELOC_NONE;
|
}
|
}
|
|
|
/* Record a HI16 reloc for later matching with its LO16 cousin. */
|
/* Record a HI16 reloc for later matching with its LO16 cousin. */
|
|
|
static void
|
static void
|
m32r_record_hi16 (int reloc_type,
|
m32r_record_hi16 (int reloc_type,
|
fixS *fixP,
|
fixS *fixP,
|
segT seg ATTRIBUTE_UNUSED)
|
segT seg ATTRIBUTE_UNUSED)
|
{
|
{
|
struct m32r_hi_fixup *hi_fixup;
|
struct m32r_hi_fixup *hi_fixup;
|
|
|
assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
|
assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
|
|| reloc_type == BFD_RELOC_M32R_HI16_ULO);
|
|| reloc_type == BFD_RELOC_M32R_HI16_ULO);
|
|
|
hi_fixup = xmalloc (sizeof (* hi_fixup));
|
hi_fixup = xmalloc (sizeof (* hi_fixup));
|
hi_fixup->fixp = fixP;
|
hi_fixup->fixp = fixP;
|
hi_fixup->seg = now_seg;
|
hi_fixup->seg = now_seg;
|
hi_fixup->next = m32r_hi_fixup_list;
|
hi_fixup->next = m32r_hi_fixup_list;
|
|
|
m32r_hi_fixup_list = hi_fixup;
|
m32r_hi_fixup_list = hi_fixup;
|
}
|
}
|
|
|
/* Called while parsing an instruction to create a fixup.
|
/* Called while parsing an instruction to create a fixup.
|
We need to check for HI16 relocs and queue them up for later sorting. */
|
We need to check for HI16 relocs and queue them up for later sorting. */
|
|
|
fixS *
|
fixS *
|
m32r_cgen_record_fixup_exp (fragS *frag,
|
m32r_cgen_record_fixup_exp (fragS *frag,
|
int where,
|
int where,
|
const CGEN_INSN *insn,
|
const CGEN_INSN *insn,
|
int length,
|
int length,
|
const CGEN_OPERAND *operand,
|
const CGEN_OPERAND *operand,
|
int opinfo,
|
int opinfo,
|
expressionS *exp)
|
expressionS *exp)
|
{
|
{
|
fixS *fixP;
|
fixS *fixP;
|
bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
|
bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
|
|
|
if (m32r_check_fixup (exp, &r_type))
|
if (m32r_check_fixup (exp, &r_type))
|
as_bad (_("Invalid PIC expression."));
|
as_bad (_("Invalid PIC expression."));
|
|
|
fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
|
fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
|
operand, opinfo, exp);
|
operand, opinfo, exp);
|
|
|
switch (operand->type)
|
switch (operand->type)
|
{
|
{
|
case M32R_OPERAND_HI16:
|
case M32R_OPERAND_HI16:
|
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
|
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
|
|| fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
|| fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
|
m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
|
break;
|
break;
|
|
|
default:
|
default:
|
/* Avoid -Wall warning. */
|
/* Avoid -Wall warning. */
|
break;
|
break;
|
}
|
}
|
|
|
switch (r_type)
|
switch (r_type)
|
{
|
{
|
case BFD_RELOC_UNUSED:
|
case BFD_RELOC_UNUSED:
|
default:
|
default:
|
return fixP;
|
return fixP;
|
|
|
case BFD_RELOC_M32R_GOTPC24:
|
case BFD_RELOC_M32R_GOTPC24:
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
|
r_type = BFD_RELOC_M32R_GOTPC_HI_SLO;
|
r_type = BFD_RELOC_M32R_GOTPC_HI_SLO;
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
r_type = BFD_RELOC_M32R_GOTPC_HI_ULO;
|
r_type = BFD_RELOC_M32R_GOTPC_HI_ULO;
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
|
r_type = BFD_RELOC_M32R_GOTPC_LO;
|
r_type = BFD_RELOC_M32R_GOTPC_LO;
|
break;
|
break;
|
|
|
case BFD_RELOC_M32R_GOT24:
|
case BFD_RELOC_M32R_GOT24:
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
|
r_type = BFD_RELOC_M32R_GOT16_HI_SLO;
|
r_type = BFD_RELOC_M32R_GOT16_HI_SLO;
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
r_type = BFD_RELOC_M32R_GOT16_HI_ULO;
|
r_type = BFD_RELOC_M32R_GOT16_HI_ULO;
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
|
r_type = BFD_RELOC_M32R_GOT16_LO;
|
r_type = BFD_RELOC_M32R_GOT16_LO;
|
break;
|
break;
|
|
|
case BFD_RELOC_M32R_GOTOFF:
|
case BFD_RELOC_M32R_GOTOFF:
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
|
r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO;
|
r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO;
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO;
|
r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO;
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
|
r_type = BFD_RELOC_M32R_GOTOFF_LO;
|
r_type = BFD_RELOC_M32R_GOTOFF_LO;
|
break;
|
break;
|
|
|
case BFD_RELOC_M32R_26_PLTREL:
|
case BFD_RELOC_M32R_26_PLTREL:
|
as_bad (_("Invalid PIC expression."));
|
as_bad (_("Invalid PIC expression."));
|
break;
|
break;
|
}
|
}
|
|
|
fixP->fx_r_type = r_type;
|
fixP->fx_r_type = r_type;
|
|
|
return fixP;
|
return fixP;
|
}
|
}
|
|
|
/* Return BFD reloc type from opinfo field in a fixS.
|
/* Return BFD reloc type from opinfo field in a fixS.
|
It's tricky using fx_r_type in m32r_frob_file because the values
|
It's tricky using fx_r_type in m32r_frob_file because the values
|
are BFD_RELOC_UNUSED + operand number. */
|
are BFD_RELOC_UNUSED + operand number. */
|
#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
|
#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
|
|
|
/* Sort any unmatched HI16 relocs so that they immediately precede
|
/* Sort any unmatched HI16 relocs so that they immediately precede
|
the corresponding LO16 reloc. This is called before md_apply_fix and
|
the corresponding LO16 reloc. This is called before md_apply_fix and
|
tc_gen_reloc. */
|
tc_gen_reloc. */
|
|
|
void
|
void
|
m32r_frob_file (void)
|
m32r_frob_file (void)
|
{
|
{
|
struct m32r_hi_fixup *l;
|
struct m32r_hi_fixup *l;
|
|
|
for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
|
for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
|
{
|
{
|
segment_info_type *seginfo;
|
segment_info_type *seginfo;
|
int pass;
|
int pass;
|
|
|
assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
|
assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
|
|| FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
|
|| FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
|
|
|
/* Check quickly whether the next fixup happens to be a matching low. */
|
/* Check quickly whether the next fixup happens to be a matching low. */
|
if (l->fixp->fx_next != NULL
|
if (l->fixp->fx_next != NULL
|
&& FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
|
&& FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
|
&& l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
|
&& l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
|
&& l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
|
&& l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
|
continue;
|
continue;
|
|
|
/* Look through the fixups for this segment for a matching `low'.
|
/* Look through the fixups for this segment for a matching `low'.
|
When we find one, move the high/shigh just in front of it. We do
|
When we find one, move the high/shigh just in front of it. We do
|
this in two passes. In the first pass, we try to find a
|
this in two passes. In the first pass, we try to find a
|
unique `low'. In the second pass, we permit multiple high's
|
unique `low'. In the second pass, we permit multiple high's
|
relocs for a single `low'. */
|
relocs for a single `low'. */
|
seginfo = seg_info (l->seg);
|
seginfo = seg_info (l->seg);
|
for (pass = 0; pass < 2; pass++)
|
for (pass = 0; pass < 2; pass++)
|
{
|
{
|
fixS *f;
|
fixS *f;
|
fixS *prev;
|
fixS *prev;
|
|
|
prev = NULL;
|
prev = NULL;
|
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
{
|
{
|
/* Check whether this is a `low' fixup which matches l->fixp. */
|
/* Check whether this is a `low' fixup which matches l->fixp. */
|
if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
|
if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
|
&& f->fx_addsy == l->fixp->fx_addsy
|
&& f->fx_addsy == l->fixp->fx_addsy
|
&& f->fx_offset == l->fixp->fx_offset
|
&& f->fx_offset == l->fixp->fx_offset
|
&& (pass == 1
|
&& (pass == 1
|
|| prev == NULL
|
|| prev == NULL
|
|| (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
|
|| (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
|
&& FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
|
&& FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
|
|| prev->fx_addsy != f->fx_addsy
|
|| prev->fx_addsy != f->fx_addsy
|
|| prev->fx_offset != f->fx_offset))
|
|| prev->fx_offset != f->fx_offset))
|
{
|
{
|
fixS **pf;
|
fixS **pf;
|
|
|
/* Move l->fixp before f. */
|
/* Move l->fixp before f. */
|
for (pf = &seginfo->fix_root;
|
for (pf = &seginfo->fix_root;
|
*pf != l->fixp;
|
*pf != l->fixp;
|
pf = & (*pf)->fx_next)
|
pf = & (*pf)->fx_next)
|
assert (*pf != NULL);
|
assert (*pf != NULL);
|
|
|
*pf = l->fixp->fx_next;
|
*pf = l->fixp->fx_next;
|
|
|
l->fixp->fx_next = f;
|
l->fixp->fx_next = f;
|
if (prev == NULL)
|
if (prev == NULL)
|
seginfo->fix_root = l->fixp;
|
seginfo->fix_root = l->fixp;
|
else
|
else
|
prev->fx_next = l->fixp;
|
prev->fx_next = l->fixp;
|
|
|
break;
|
break;
|
}
|
}
|
|
|
prev = f;
|
prev = f;
|
}
|
}
|
|
|
if (f != NULL)
|
if (f != NULL)
|
break;
|
break;
|
|
|
if (pass == 1
|
if (pass == 1
|
&& warn_unmatched_high)
|
&& warn_unmatched_high)
|
as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
|
as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
|
_("Unmatched high/shigh reloc"));
|
_("Unmatched high/shigh reloc"));
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* See whether we need to force a relocation into the output file.
|
/* See whether we need to force a relocation into the output file.
|
This is used to force out switch and PC relative relocations when
|
This is used to force out switch and PC relative relocations when
|
relaxing. */
|
relaxing. */
|
|
|
int
|
int
|
m32r_force_relocation (fixS *fix)
|
m32r_force_relocation (fixS *fix)
|
{
|
{
|
if (generic_force_reloc (fix))
|
if (generic_force_reloc (fix))
|
return 1;
|
return 1;
|
|
|
if (! m32r_relax)
|
if (! m32r_relax)
|
return 0;
|
return 0;
|
|
|
return fix->fx_pcrel;
|
return fix->fx_pcrel;
|
}
|
}
|
|
|
/* Write a value out to the object file, using the appropriate endianness. */
|
/* Write a value out to the object file, using the appropriate endianness. */
|
|
|
void
|
void
|
md_number_to_chars (char *buf, valueT val, int n)
|
md_number_to_chars (char *buf, valueT val, int n)
|
{
|
{
|
if (target_big_endian)
|
if (target_big_endian)
|
number_to_chars_bigendian (buf, val, n);
|
number_to_chars_bigendian (buf, val, n);
|
else
|
else
|
number_to_chars_littleendian (buf, val, n);
|
number_to_chars_littleendian (buf, val, n);
|
}
|
}
|
|
|
/* Turn a string in input_line_pointer into a floating point constant
|
/* Turn a string in input_line_pointer into a floating point constant
|
of type TYPE, and store the appropriate bytes in *LITP. The number
|
of type TYPE, and store the appropriate bytes in *LITP. The number
|
of LITTLENUMS emitted is stored in *SIZEP. An error message is
|
of LITTLENUMS emitted is stored in *SIZEP. An error message is
|
returned, or NULL on OK. */
|
returned, or NULL on OK. */
|
|
|
/* Equal to MAX_PRECISION in atof-ieee.c. */
|
/* Equal to MAX_PRECISION in atof-ieee.c. */
|
#define MAX_LITTLENUMS 6
|
#define MAX_LITTLENUMS 6
|
|
|
char *
|
char *
|
md_atof (int type, char *litP, int *sizeP)
|
md_atof (int type, char *litP, int *sizeP)
|
{
|
{
|
return ieee_md_atof (type, litP, sizeP, target_big_endian);
|
return ieee_md_atof (type, litP, sizeP, target_big_endian);
|
}
|
}
|
|
|
void
|
void
|
m32r_elf_section_change_hook (void)
|
m32r_elf_section_change_hook (void)
|
{
|
{
|
/* If we have reached the end of a section and we have just emitted a
|
/* If we have reached the end of a section and we have just emitted a
|
16 bit insn, then emit a nop to make sure that the section ends on
|
16 bit insn, then emit a nop to make sure that the section ends on
|
a 32 bit boundary. */
|
a 32 bit boundary. */
|
|
|
if (prev_insn.insn || seen_relaxable_p)
|
if (prev_insn.insn || seen_relaxable_p)
|
(void) m32r_fill_insn (0);
|
(void) m32r_fill_insn (0);
|
}
|
}
|
|
|
/* Return true if can adjust the reloc to be relative to its section
|
/* Return true if can adjust the reloc to be relative to its section
|
(such as .data) instead of relative to some symbol. */
|
(such as .data) instead of relative to some symbol. */
|
|
|
bfd_boolean
|
bfd_boolean
|
m32r_fix_adjustable (fixS *fixP)
|
m32r_fix_adjustable (fixS *fixP)
|
{
|
{
|
bfd_reloc_code_real_type reloc_type;
|
bfd_reloc_code_real_type reloc_type;
|
|
|
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
|
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
|
{
|
{
|
const CGEN_INSN *insn = NULL;
|
const CGEN_INSN *insn = NULL;
|
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
|
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
|
const CGEN_OPERAND *operand =
|
const CGEN_OPERAND *operand =
|
cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
|
cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
|
|
|
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
|
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
|
}
|
}
|
else
|
else
|
reloc_type = fixP->fx_r_type;
|
reloc_type = fixP->fx_r_type;
|
|
|
if (fixP->fx_addsy == NULL)
|
if (fixP->fx_addsy == NULL)
|
return 1;
|
return 1;
|
|
|
/* Prevent all adjustments to global symbols. */
|
/* Prevent all adjustments to global symbols. */
|
if (S_IS_EXTERNAL (fixP->fx_addsy))
|
if (S_IS_EXTERNAL (fixP->fx_addsy))
|
return 0;
|
return 0;
|
if (S_IS_WEAK (fixP->fx_addsy))
|
if (S_IS_WEAK (fixP->fx_addsy))
|
return 0;
|
return 0;
|
|
|
if (pic_code
|
if (pic_code
|
&& (reloc_type == BFD_RELOC_M32R_24
|
&& (reloc_type == BFD_RELOC_M32R_24
|
|| reloc_type == BFD_RELOC_M32R_26_PCREL
|
|| reloc_type == BFD_RELOC_M32R_26_PCREL
|
|| reloc_type == BFD_RELOC_M32R_HI16_SLO
|
|| reloc_type == BFD_RELOC_M32R_HI16_SLO
|
|| reloc_type == BFD_RELOC_M32R_HI16_ULO
|
|| reloc_type == BFD_RELOC_M32R_HI16_ULO
|
|| reloc_type == BFD_RELOC_M32R_LO16))
|
|| reloc_type == BFD_RELOC_M32R_LO16))
|
return 0;
|
return 0;
|
|
|
if (reloc_type == BFD_RELOC_M32R_GOT24
|
if (reloc_type == BFD_RELOC_M32R_GOT24
|
|| reloc_type == BFD_RELOC_M32R_26_PLTREL
|
|| reloc_type == BFD_RELOC_M32R_26_PLTREL
|
|| reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO
|
|| reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO
|
|| reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO
|
|| reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO
|
|| reloc_type == BFD_RELOC_M32R_GOTPC_LO
|
|| reloc_type == BFD_RELOC_M32R_GOTPC_LO
|
|| reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO
|
|| reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO
|
|| reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO
|
|| reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO
|
|| reloc_type == BFD_RELOC_M32R_GOT16_LO)
|
|| reloc_type == BFD_RELOC_M32R_GOT16_LO)
|
return 0;
|
return 0;
|
|
|
/* We need the symbol name for the VTABLE entries. */
|
/* We need the symbol name for the VTABLE entries. */
|
if (reloc_type == BFD_RELOC_VTABLE_INHERIT
|
if (reloc_type == BFD_RELOC_VTABLE_INHERIT
|
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
|
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
|
return 0;
|
return 0;
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
void
|
void
|
m32r_elf_final_processing (void)
|
m32r_elf_final_processing (void)
|
{
|
{
|
if (use_parallel)
|
if (use_parallel)
|
m32r_flags |= E_M32R_HAS_PARALLEL;
|
m32r_flags |= E_M32R_HAS_PARALLEL;
|
elf_elfheader (stdoutput)->e_flags |= m32r_flags;
|
elf_elfheader (stdoutput)->e_flags |= m32r_flags;
|
}
|
}
|
|
|
/* Translate internal representation of relocation info to BFD target
|
/* Translate internal representation of relocation info to BFD target
|
format. */
|
format. */
|
|
|
arelent *
|
arelent *
|
tc_gen_reloc (asection * section, fixS * fixP)
|
tc_gen_reloc (asection * section, fixS * fixP)
|
{
|
{
|
arelent * reloc;
|
arelent * reloc;
|
bfd_reloc_code_real_type code;
|
bfd_reloc_code_real_type code;
|
|
|
reloc = xmalloc (sizeof (* reloc));
|
reloc = xmalloc (sizeof (* reloc));
|
|
|
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
|
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
|
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
|
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
|
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
|
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
|
|
|
if (fixP->fx_pcrel)
|
if (fixP->fx_pcrel)
|
{
|
{
|
if (fixP->fx_r_type == BFD_RELOC_32)
|
if (fixP->fx_r_type == BFD_RELOC_32)
|
fixP->fx_r_type = BFD_RELOC_32_PCREL;
|
fixP->fx_r_type = BFD_RELOC_32_PCREL;
|
else if (fixP->fx_r_type == BFD_RELOC_16)
|
else if (fixP->fx_r_type == BFD_RELOC_16)
|
{
|
{
|
fixP->fx_r_type = BFD_RELOC_16_PCREL;
|
fixP->fx_r_type = BFD_RELOC_16_PCREL;
|
bfd_set_error (bfd_error_bad_value);
|
bfd_set_error (bfd_error_bad_value);
|
}
|
}
|
}
|
}
|
|
|
code = fixP->fx_r_type;
|
code = fixP->fx_r_type;
|
if (pic_code)
|
if (pic_code)
|
{
|
{
|
#ifdef DEBUG_PIC
|
#ifdef DEBUG_PIC
|
printf("%s",bfd_get_reloc_code_name(code));
|
printf("%s",bfd_get_reloc_code_name(code));
|
#endif
|
#endif
|
switch (code)
|
switch (code)
|
{
|
{
|
case BFD_RELOC_M32R_26_PCREL:
|
case BFD_RELOC_M32R_26_PCREL:
|
code = BFD_RELOC_M32R_26_PLTREL;
|
code = BFD_RELOC_M32R_26_PLTREL;
|
break;
|
break;
|
|
|
case BFD_RELOC_M32R_24:
|
case BFD_RELOC_M32R_24:
|
if (fixP->fx_addsy != NULL
|
if (fixP->fx_addsy != NULL
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
code = BFD_RELOC_M32R_GOTPC24;
|
code = BFD_RELOC_M32R_GOTPC24;
|
else
|
else
|
code = BFD_RELOC_M32R_GOT24;
|
code = BFD_RELOC_M32R_GOT24;
|
break;
|
break;
|
|
|
case BFD_RELOC_M32R_HI16_ULO:
|
case BFD_RELOC_M32R_HI16_ULO:
|
if (fixP->fx_addsy != NULL
|
if (fixP->fx_addsy != NULL
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
code = BFD_RELOC_M32R_GOTPC_HI_ULO;
|
code = BFD_RELOC_M32R_GOTPC_HI_ULO;
|
else
|
else
|
code = BFD_RELOC_M32R_GOT16_HI_ULO;
|
code = BFD_RELOC_M32R_GOT16_HI_ULO;
|
break;
|
break;
|
|
|
case BFD_RELOC_M32R_HI16_SLO:
|
case BFD_RELOC_M32R_HI16_SLO:
|
if (fixP->fx_addsy != NULL
|
if (fixP->fx_addsy != NULL
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
code = BFD_RELOC_M32R_GOTPC_HI_SLO;
|
code = BFD_RELOC_M32R_GOTPC_HI_SLO;
|
else
|
else
|
code = BFD_RELOC_M32R_GOT16_HI_SLO;
|
code = BFD_RELOC_M32R_GOT16_HI_SLO;
|
break;
|
break;
|
|
|
case BFD_RELOC_M32R_LO16:
|
case BFD_RELOC_M32R_LO16:
|
if (fixP->fx_addsy != NULL
|
if (fixP->fx_addsy != NULL
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
code = BFD_RELOC_M32R_GOTPC_LO;
|
code = BFD_RELOC_M32R_GOTPC_LO;
|
else
|
else
|
code = BFD_RELOC_M32R_GOT16_LO;
|
code = BFD_RELOC_M32R_GOT16_LO;
|
break;
|
break;
|
|
|
default:
|
default:
|
break;
|
break;
|
}
|
}
|
#ifdef DEBUG_PIC
|
#ifdef DEBUG_PIC
|
printf(" => %s",bfd_get_reloc_code_name(code));
|
printf(" => %s",bfd_get_reloc_code_name(code));
|
#endif
|
#endif
|
}
|
}
|
|
|
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
|
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
|
|
|
#ifdef DEBUG_PIC
|
#ifdef DEBUG_PIC
|
printf(" => %s\n",reloc->howto->name);
|
printf(" => %s\n",reloc->howto->name);
|
#endif
|
#endif
|
|
|
if (reloc->howto == (reloc_howto_type *) NULL)
|
if (reloc->howto == (reloc_howto_type *) NULL)
|
{
|
{
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
_("internal error: can't export reloc type %d (`%s')"),
|
_("internal error: can't export reloc type %d (`%s')"),
|
fixP->fx_r_type, bfd_get_reloc_code_name (code));
|
fixP->fx_r_type, bfd_get_reloc_code_name (code));
|
return NULL;
|
return NULL;
|
}
|
}
|
|
|
/* Use fx_offset for these cases. */
|
/* Use fx_offset for these cases. */
|
if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
|
if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
|
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
|| fixP->fx_r_type == BFD_RELOC_32_PCREL)
|
|| fixP->fx_r_type == BFD_RELOC_32_PCREL)
|
reloc->addend = fixP->fx_offset;
|
reloc->addend = fixP->fx_offset;
|
else if ((!pic_code
|
else if ((!pic_code
|
&& code != BFD_RELOC_M32R_26_PLTREL)
|
&& code != BFD_RELOC_M32R_26_PLTREL)
|
&& fixP->fx_pcrel
|
&& fixP->fx_pcrel
|
&& fixP->fx_addsy != NULL
|
&& fixP->fx_addsy != NULL
|
&& (S_GET_SEGMENT(fixP->fx_addsy) != section)
|
&& (S_GET_SEGMENT(fixP->fx_addsy) != section)
|
&& S_IS_DEFINED (fixP->fx_addsy)
|
&& S_IS_DEFINED (fixP->fx_addsy)
|
&& ! S_IS_EXTERNAL(fixP->fx_addsy)
|
&& ! S_IS_EXTERNAL(fixP->fx_addsy)
|
&& ! S_IS_WEAK(fixP->fx_addsy))
|
&& ! S_IS_WEAK(fixP->fx_addsy))
|
/* Already used fx_offset in the opcode field itseld. */
|
/* Already used fx_offset in the opcode field itseld. */
|
reloc->addend = fixP->fx_offset;
|
reloc->addend = fixP->fx_offset;
|
else
|
else
|
reloc->addend = fixP->fx_addnumber;
|
reloc->addend = fixP->fx_addnumber;
|
|
|
return reloc;
|
return reloc;
|
}
|
}
|
|
|
inline static char *
|
inline static char *
|
m32r_end_of_match (char *cont, char *what)
|
m32r_end_of_match (char *cont, char *what)
|
{
|
{
|
int len = strlen (what);
|
int len = strlen (what);
|
|
|
if (strncasecmp (cont, what, strlen (what)) == 0
|
if (strncasecmp (cont, what, strlen (what)) == 0
|
&& ! is_part_of_name (cont[len]))
|
&& ! is_part_of_name (cont[len]))
|
return cont + len;
|
return cont + len;
|
|
|
return NULL;
|
return NULL;
|
}
|
}
|
|
|
int
|
int
|
m32r_parse_name (char const *name,
|
m32r_parse_name (char const *name,
|
expressionS *exprP,
|
expressionS *exprP,
|
enum expr_mode mode,
|
enum expr_mode mode,
|
char *nextcharP)
|
char *nextcharP)
|
{
|
{
|
char *next = input_line_pointer;
|
char *next = input_line_pointer;
|
char *next_end;
|
char *next_end;
|
int reloc_type;
|
int reloc_type;
|
operatorT op_type;
|
operatorT op_type;
|
segT segment;
|
segT segment;
|
|
|
exprP->X_op_symbol = NULL;
|
exprP->X_op_symbol = NULL;
|
exprP->X_md = BFD_RELOC_UNUSED;
|
exprP->X_md = BFD_RELOC_UNUSED;
|
|
|
if (strcmp (name, GOT_NAME) == 0)
|
if (strcmp (name, GOT_NAME) == 0)
|
{
|
{
|
if (! GOT_symbol)
|
if (! GOT_symbol)
|
GOT_symbol = symbol_find_or_make (name);
|
GOT_symbol = symbol_find_or_make (name);
|
|
|
exprP->X_add_symbol = GOT_symbol;
|
exprP->X_add_symbol = GOT_symbol;
|
no_suffix:
|
no_suffix:
|
/* If we have an absolute symbol or a
|
/* If we have an absolute symbol or a
|
reg, then we know its value now. */
|
reg, then we know its value now. */
|
segment = S_GET_SEGMENT (exprP->X_add_symbol);
|
segment = S_GET_SEGMENT (exprP->X_add_symbol);
|
if (mode != expr_defer && segment == absolute_section)
|
if (mode != expr_defer && segment == absolute_section)
|
{
|
{
|
exprP->X_op = O_constant;
|
exprP->X_op = O_constant;
|
exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
|
exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
|
exprP->X_add_symbol = NULL;
|
exprP->X_add_symbol = NULL;
|
}
|
}
|
else if (mode != expr_defer && segment == reg_section)
|
else if (mode != expr_defer && segment == reg_section)
|
{
|
{
|
exprP->X_op = O_register;
|
exprP->X_op = O_register;
|
exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
|
exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
|
exprP->X_add_symbol = NULL;
|
exprP->X_add_symbol = NULL;
|
}
|
}
|
else
|
else
|
{
|
{
|
exprP->X_op = O_symbol;
|
exprP->X_op = O_symbol;
|
exprP->X_add_number = 0;
|
exprP->X_add_number = 0;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
exprP->X_add_symbol = symbol_find_or_make (name);
|
exprP->X_add_symbol = symbol_find_or_make (name);
|
|
|
if (*nextcharP != '@')
|
if (*nextcharP != '@')
|
goto no_suffix;
|
goto no_suffix;
|
else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF")))
|
else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF")))
|
{
|
{
|
reloc_type = BFD_RELOC_M32R_GOTOFF;
|
reloc_type = BFD_RELOC_M32R_GOTOFF;
|
op_type = O_PIC_reloc;
|
op_type = O_PIC_reloc;
|
}
|
}
|
else if ((next_end = m32r_end_of_match (next + 1, "GOT")))
|
else if ((next_end = m32r_end_of_match (next + 1, "GOT")))
|
{
|
{
|
reloc_type = BFD_RELOC_M32R_GOT24;
|
reloc_type = BFD_RELOC_M32R_GOT24;
|
op_type = O_PIC_reloc;
|
op_type = O_PIC_reloc;
|
}
|
}
|
else if ((next_end = m32r_end_of_match (next + 1, "PLT")))
|
else if ((next_end = m32r_end_of_match (next + 1, "PLT")))
|
{
|
{
|
reloc_type = BFD_RELOC_M32R_26_PLTREL;
|
reloc_type = BFD_RELOC_M32R_26_PLTREL;
|
op_type = O_PIC_reloc;
|
op_type = O_PIC_reloc;
|
}
|
}
|
else
|
else
|
goto no_suffix;
|
goto no_suffix;
|
|
|
*input_line_pointer = *nextcharP;
|
*input_line_pointer = *nextcharP;
|
input_line_pointer = next_end;
|
input_line_pointer = next_end;
|
*nextcharP = *input_line_pointer;
|
*nextcharP = *input_line_pointer;
|
*input_line_pointer = '\0';
|
*input_line_pointer = '\0';
|
|
|
exprP->X_op = op_type;
|
exprP->X_op = op_type;
|
exprP->X_add_number = 0;
|
exprP->X_add_number = 0;
|
exprP->X_md = reloc_type;
|
exprP->X_md = reloc_type;
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
int
|
int
|
m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp)
|
m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp)
|
{
|
{
|
if (exp->X_op == O_PIC_reloc
|
if (exp->X_op == O_PIC_reloc
|
&& exp->X_md == BFD_RELOC_M32R_26_PLTREL)
|
&& exp->X_md == BFD_RELOC_M32R_26_PLTREL)
|
{
|
{
|
exp->X_op = O_symbol;
|
exp->X_op = O_symbol;
|
opinfo = exp->X_md;
|
opinfo = exp->X_md;
|
}
|
}
|
|
|
return opinfo;
|
return opinfo;
|
}
|
}
|
|
|
