/* tc-mep.c -- Assembler for the Toshiba Media Processor.
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/* tc-mep.c -- Assembler for the Toshiba Media Processor.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007
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Free Software Foundation. Inc.
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Free Software Foundation. Inc.
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This file is part of GAS, the GNU Assembler.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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GAS is distributed in the hope that it will be useful,
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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Boston, MA 02110-1301, USA. */
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#include <stdio.h>
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#include <stdio.h>
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#include "as.h"
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#include "as.h"
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#include "dwarf2dbg.h"
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#include "dwarf2dbg.h"
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#include "subsegs.h"
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#include "subsegs.h"
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#include "symcat.h"
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#include "symcat.h"
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#include "opcodes/mep-desc.h"
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#include "opcodes/mep-desc.h"
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#include "opcodes/mep-opc.h"
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#include "opcodes/mep-opc.h"
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#include "cgen.h"
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#include "cgen.h"
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#include "elf/common.h"
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#include "elf/common.h"
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#include "elf/mep.h"
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#include "elf/mep.h"
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#include "libbfd.h"
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#include "libbfd.h"
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#include "xregex.h"
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#include "xregex.h"
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/* Structure to hold all of the different components describing
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/* Structure to hold all of the different components describing
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an individual instruction. */
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an individual instruction. */
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typedef struct
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typedef struct
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{
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{
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const CGEN_INSN * insn;
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const CGEN_INSN * insn;
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const CGEN_INSN * orig_insn;
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const CGEN_INSN * orig_insn;
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CGEN_FIELDS fields;
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CGEN_FIELDS fields;
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#if CGEN_INT_INSN_P
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#if CGEN_INT_INSN_P
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CGEN_INSN_INT buffer [1];
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CGEN_INSN_INT buffer [1];
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#define INSN_VALUE(buf) (*(buf))
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#define INSN_VALUE(buf) (*(buf))
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#else
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#else
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unsigned char buffer [CGEN_MAX_INSN_SIZE];
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unsigned char buffer [CGEN_MAX_INSN_SIZE];
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#define INSN_VALUE(buf) (buf)
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#define INSN_VALUE(buf) (buf)
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#endif
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#endif
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char * addr;
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char * addr;
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fragS * frag;
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fragS * frag;
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int num_fixups;
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int num_fixups;
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fixS * fixups [GAS_CGEN_MAX_FIXUPS];
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fixS * fixups [GAS_CGEN_MAX_FIXUPS];
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int indices [MAX_OPERAND_INSTANCES];
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int indices [MAX_OPERAND_INSTANCES];
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} mep_insn;
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} mep_insn;
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static int mode = CORE; /* Start in core mode. */
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static int mode = CORE; /* Start in core mode. */
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static int pluspresent = 0;
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static int pluspresent = 0;
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static int allow_disabled_registers = 0;
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static int allow_disabled_registers = 0;
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static int library_flag = 0;
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static int library_flag = 0;
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/* We're going to need to store all of the instructions along with
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/* We're going to need to store all of the instructions along with
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their fixups so that we can parallelization grouping rules. */
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their fixups so that we can parallelization grouping rules. */
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static mep_insn saved_insns[MAX_SAVED_FIXUP_CHAINS];
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static mep_insn saved_insns[MAX_SAVED_FIXUP_CHAINS];
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static int num_insns_saved = 0;
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static int num_insns_saved = 0;
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const char comment_chars[] = "#";
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const char comment_chars[] = "#";
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const char line_comment_chars[] = ";#";
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const char line_comment_chars[] = ";#";
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const char line_separator_chars[] = ";";
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const char line_separator_chars[] = ";";
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const char EXP_CHARS[] = "eE";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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const char FLT_CHARS[] = "dD";
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static void mep_switch_to_vliw_mode (int);
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static void mep_switch_to_vliw_mode (int);
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static void mep_switch_to_core_mode (int);
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static void mep_switch_to_core_mode (int);
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static void mep_s_vtext (int);
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static void mep_s_vtext (int);
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static void mep_noregerr (int);
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static void mep_noregerr (int);
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/* The target specific pseudo-ops which we support. */
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/* The target specific pseudo-ops which we support. */
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const pseudo_typeS md_pseudo_table[] =
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const pseudo_typeS md_pseudo_table[] =
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{
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{
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{ "word", cons, 4 },
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{ "word", cons, 4 },
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{ "file", (void (*) (int)) dwarf2_directive_file, 0 },
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{ "file", (void (*) (int)) dwarf2_directive_file, 0 },
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{ "loc", dwarf2_directive_loc, 0 },
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{ "loc", dwarf2_directive_loc, 0 },
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{ "vliw", mep_switch_to_vliw_mode, 0 },
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{ "vliw", mep_switch_to_vliw_mode, 0 },
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{ "core", mep_switch_to_core_mode, 0 },
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{ "core", mep_switch_to_core_mode, 0 },
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{ "vtext", mep_s_vtext, 0 },
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{ "vtext", mep_s_vtext, 0 },
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{ "noregerr", mep_noregerr, 0 },
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{ "noregerr", mep_noregerr, 0 },
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{ NULL, NULL, 0 }
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{ NULL, NULL, 0 }
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};
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};
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/* Relocations against symbols are done in two
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/* Relocations against symbols are done in two
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parts, with a HI relocation and a LO relocation. Each relocation
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parts, with a HI relocation and a LO relocation. Each relocation
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has only 16 bits of space to store an addend. This means that in
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has only 16 bits of space to store an addend. This means that in
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order for the linker to handle carries correctly, it must be able
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order for the linker to handle carries correctly, it must be able
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to locate both the HI and the LO relocation. This means that the
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to locate both the HI and the LO relocation. This means that the
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relocations must appear in order in the relocation table.
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relocations must appear in order in the relocation table.
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In order to implement this, we keep track of each unmatched HI
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In order to implement this, we keep track of each unmatched HI
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relocation. We then sort them so that they immediately precede the
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relocation. We then sort them so that they immediately precede the
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corresponding LO relocation. */
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corresponding LO relocation. */
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struct mep_hi_fixup
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struct mep_hi_fixup
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{
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{
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struct mep_hi_fixup * next; /* Next HI fixup. */
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struct mep_hi_fixup * next; /* Next HI fixup. */
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fixS * fixp; /* This fixup. */
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fixS * fixp; /* This fixup. */
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segT seg; /* The section this fixup is in. */
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segT seg; /* The section this fixup is in. */
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};
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};
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/* The list of unmatched HI relocs. */
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/* The list of unmatched HI relocs. */
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static struct mep_hi_fixup * mep_hi_fixup_list;
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static struct mep_hi_fixup * mep_hi_fixup_list;
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#define OPTION_EB (OPTION_MD_BASE + 0)
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#define OPTION_EB (OPTION_MD_BASE + 0)
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#define OPTION_EL (OPTION_MD_BASE + 1)
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#define OPTION_EL (OPTION_MD_BASE + 1)
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#define OPTION_CONFIG (OPTION_MD_BASE + 2)
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#define OPTION_CONFIG (OPTION_MD_BASE + 2)
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#define OPTION_AVERAGE (OPTION_MD_BASE + 3)
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#define OPTION_AVERAGE (OPTION_MD_BASE + 3)
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#define OPTION_NOAVERAGE (OPTION_MD_BASE + 4)
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#define OPTION_NOAVERAGE (OPTION_MD_BASE + 4)
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#define OPTION_MULT (OPTION_MD_BASE + 5)
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#define OPTION_MULT (OPTION_MD_BASE + 5)
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#define OPTION_NOMULT (OPTION_MD_BASE + 6)
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#define OPTION_NOMULT (OPTION_MD_BASE + 6)
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#define OPTION_DIV (OPTION_MD_BASE + 7)
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#define OPTION_DIV (OPTION_MD_BASE + 7)
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#define OPTION_NODIV (OPTION_MD_BASE + 8)
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#define OPTION_NODIV (OPTION_MD_BASE + 8)
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#define OPTION_BITOPS (OPTION_MD_BASE + 9)
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#define OPTION_BITOPS (OPTION_MD_BASE + 9)
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#define OPTION_NOBITOPS (OPTION_MD_BASE + 10)
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#define OPTION_NOBITOPS (OPTION_MD_BASE + 10)
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#define OPTION_LEADZ (OPTION_MD_BASE + 11)
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#define OPTION_LEADZ (OPTION_MD_BASE + 11)
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#define OPTION_NOLEADZ (OPTION_MD_BASE + 12)
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#define OPTION_NOLEADZ (OPTION_MD_BASE + 12)
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#define OPTION_ABSDIFF (OPTION_MD_BASE + 13)
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#define OPTION_ABSDIFF (OPTION_MD_BASE + 13)
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#define OPTION_NOABSDIFF (OPTION_MD_BASE + 14)
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#define OPTION_NOABSDIFF (OPTION_MD_BASE + 14)
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#define OPTION_MINMAX (OPTION_MD_BASE + 15)
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#define OPTION_MINMAX (OPTION_MD_BASE + 15)
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#define OPTION_NOMINMAX (OPTION_MD_BASE + 16)
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#define OPTION_NOMINMAX (OPTION_MD_BASE + 16)
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#define OPTION_CLIP (OPTION_MD_BASE + 17)
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#define OPTION_CLIP (OPTION_MD_BASE + 17)
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#define OPTION_NOCLIP (OPTION_MD_BASE + 18)
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#define OPTION_NOCLIP (OPTION_MD_BASE + 18)
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#define OPTION_SATUR (OPTION_MD_BASE + 19)
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#define OPTION_SATUR (OPTION_MD_BASE + 19)
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#define OPTION_NOSATUR (OPTION_MD_BASE + 20)
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#define OPTION_NOSATUR (OPTION_MD_BASE + 20)
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#define OPTION_COP32 (OPTION_MD_BASE + 21)
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#define OPTION_COP32 (OPTION_MD_BASE + 21)
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#define OPTION_REPEAT (OPTION_MD_BASE + 25)
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#define OPTION_REPEAT (OPTION_MD_BASE + 25)
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#define OPTION_NOREPEAT (OPTION_MD_BASE + 26)
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#define OPTION_NOREPEAT (OPTION_MD_BASE + 26)
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#define OPTION_DEBUG (OPTION_MD_BASE + 27)
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#define OPTION_DEBUG (OPTION_MD_BASE + 27)
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#define OPTION_NODEBUG (OPTION_MD_BASE + 28)
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#define OPTION_NODEBUG (OPTION_MD_BASE + 28)
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#define OPTION_LIBRARY (OPTION_MD_BASE + 29)
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#define OPTION_LIBRARY (OPTION_MD_BASE + 29)
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struct option md_longopts[] = {
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struct option md_longopts[] = {
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{ "EB", no_argument, NULL, OPTION_EB},
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{ "EB", no_argument, NULL, OPTION_EB},
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{ "EL", no_argument, NULL, OPTION_EL},
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{ "EL", no_argument, NULL, OPTION_EL},
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{ "mconfig", required_argument, NULL, OPTION_CONFIG},
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{ "mconfig", required_argument, NULL, OPTION_CONFIG},
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{ "maverage", no_argument, NULL, OPTION_AVERAGE},
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{ "maverage", no_argument, NULL, OPTION_AVERAGE},
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{ "mno-average", no_argument, NULL, OPTION_NOAVERAGE},
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{ "mno-average", no_argument, NULL, OPTION_NOAVERAGE},
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{ "mmult", no_argument, NULL, OPTION_MULT},
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{ "mmult", no_argument, NULL, OPTION_MULT},
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{ "mno-mult", no_argument, NULL, OPTION_NOMULT},
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{ "mno-mult", no_argument, NULL, OPTION_NOMULT},
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{ "mdiv", no_argument, NULL, OPTION_DIV},
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{ "mdiv", no_argument, NULL, OPTION_DIV},
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{ "mno-div", no_argument, NULL, OPTION_NODIV},
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{ "mno-div", no_argument, NULL, OPTION_NODIV},
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{ "mbitops", no_argument, NULL, OPTION_BITOPS},
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{ "mbitops", no_argument, NULL, OPTION_BITOPS},
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{ "mno-bitops", no_argument, NULL, OPTION_NOBITOPS},
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{ "mno-bitops", no_argument, NULL, OPTION_NOBITOPS},
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{ "mleadz", no_argument, NULL, OPTION_LEADZ},
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{ "mleadz", no_argument, NULL, OPTION_LEADZ},
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{ "mno-leadz", no_argument, NULL, OPTION_NOLEADZ},
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{ "mno-leadz", no_argument, NULL, OPTION_NOLEADZ},
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{ "mabsdiff", no_argument, NULL, OPTION_ABSDIFF},
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{ "mabsdiff", no_argument, NULL, OPTION_ABSDIFF},
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{ "mno-absdiff", no_argument, NULL, OPTION_NOABSDIFF},
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{ "mno-absdiff", no_argument, NULL, OPTION_NOABSDIFF},
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{ "mminmax", no_argument, NULL, OPTION_MINMAX},
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{ "mminmax", no_argument, NULL, OPTION_MINMAX},
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{ "mno-minmax", no_argument, NULL, OPTION_NOMINMAX},
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{ "mno-minmax", no_argument, NULL, OPTION_NOMINMAX},
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{ "mclip", no_argument, NULL, OPTION_CLIP},
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{ "mclip", no_argument, NULL, OPTION_CLIP},
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{ "mno-clip", no_argument, NULL, OPTION_NOCLIP},
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{ "mno-clip", no_argument, NULL, OPTION_NOCLIP},
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{ "msatur", no_argument, NULL, OPTION_SATUR},
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{ "msatur", no_argument, NULL, OPTION_SATUR},
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{ "mno-satur", no_argument, NULL, OPTION_NOSATUR},
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{ "mno-satur", no_argument, NULL, OPTION_NOSATUR},
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{ "mcop32", no_argument, NULL, OPTION_COP32},
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{ "mcop32", no_argument, NULL, OPTION_COP32},
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{ "mdebug", no_argument, NULL, OPTION_DEBUG},
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{ "mdebug", no_argument, NULL, OPTION_DEBUG},
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{ "mno-debug", no_argument, NULL, OPTION_NODEBUG},
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{ "mno-debug", no_argument, NULL, OPTION_NODEBUG},
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{ "mlibrary", no_argument, NULL, OPTION_LIBRARY},
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{ "mlibrary", no_argument, NULL, OPTION_LIBRARY},
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{ NULL, 0, NULL, 0 } };
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{ NULL, 0, NULL, 0 } };
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size_t md_longopts_size = sizeof (md_longopts);
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size_t md_longopts_size = sizeof (md_longopts);
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const char * md_shortopts = "";
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const char * md_shortopts = "";
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static int optbits = 0;
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static int optbits = 0;
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static int optbitset = 0;
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static int optbitset = 0;
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int
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int
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md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
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md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
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{
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{
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int i, idx;
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int i, idx;
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switch (c)
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switch (c)
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{
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{
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case OPTION_EB:
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case OPTION_EB:
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target_big_endian = 1;
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target_big_endian = 1;
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break;
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break;
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case OPTION_EL:
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case OPTION_EL:
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target_big_endian = 0;
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target_big_endian = 0;
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break;
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break;
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case OPTION_CONFIG:
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case OPTION_CONFIG:
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idx = 0;
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idx = 0;
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for (i=1; mep_config_map[i].name; i++)
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for (i=1; mep_config_map[i].name; i++)
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if (strcmp (mep_config_map[i].name, arg) == 0)
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if (strcmp (mep_config_map[i].name, arg) == 0)
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{
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{
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idx = i;
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idx = i;
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break;
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break;
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}
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}
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if (!idx)
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if (!idx)
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{
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{
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fprintf (stderr, "Error: unknown configuration %s\n", arg);
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fprintf (stderr, "Error: unknown configuration %s\n", arg);
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return 0;
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return 0;
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}
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}
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mep_config_index = idx;
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mep_config_index = idx;
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target_big_endian = mep_config_map[idx].big_endian;
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target_big_endian = mep_config_map[idx].big_endian;
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break;
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break;
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case OPTION_AVERAGE:
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case OPTION_AVERAGE:
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optbits |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
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optbits |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
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break;
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break;
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case OPTION_NOAVERAGE:
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case OPTION_NOAVERAGE:
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_AVE_INSN);
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_AVE_INSN);
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optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
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break;
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break;
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case OPTION_MULT:
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case OPTION_MULT:
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optbits |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
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optbits |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
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break;
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break;
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case OPTION_NOMULT:
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case OPTION_NOMULT:
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_MUL_INSN);
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_MUL_INSN);
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optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
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break;
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break;
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case OPTION_DIV:
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case OPTION_DIV:
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optbits |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
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optbits |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
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break;
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break;
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case OPTION_NODIV:
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case OPTION_NODIV:
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_DIV_INSN);
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_DIV_INSN);
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optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
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break;
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break;
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case OPTION_BITOPS:
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case OPTION_BITOPS:
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optbits |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
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optbits |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
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break;
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break;
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case OPTION_NOBITOPS:
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case OPTION_NOBITOPS:
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_BIT_INSN);
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_BIT_INSN);
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optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
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break;
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break;
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case OPTION_LEADZ:
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case OPTION_LEADZ:
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optbits |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
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optbits |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
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break;
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break;
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case OPTION_NOLEADZ:
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case OPTION_NOLEADZ:
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_LDZ_INSN);
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_LDZ_INSN);
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optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
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break;
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break;
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case OPTION_ABSDIFF:
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case OPTION_ABSDIFF:
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optbits |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
|
optbits |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
|
break;
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break;
|
case OPTION_NOABSDIFF:
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case OPTION_NOABSDIFF:
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optbits &= ~(1 << CGEN_INSN_OPTIONAL_ABS_INSN);
|
optbits &= ~(1 << CGEN_INSN_OPTIONAL_ABS_INSN);
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optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
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break;
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break;
|
case OPTION_MINMAX:
|
case OPTION_MINMAX:
|
optbits |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
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optbits |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
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optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
|
break;
|
break;
|
case OPTION_NOMINMAX:
|
case OPTION_NOMINMAX:
|
optbits &= ~(1 << CGEN_INSN_OPTIONAL_MINMAX_INSN);
|
optbits &= ~(1 << CGEN_INSN_OPTIONAL_MINMAX_INSN);
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
|
break;
|
break;
|
case OPTION_CLIP:
|
case OPTION_CLIP:
|
optbits |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
|
optbits |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
|
break;
|
break;
|
case OPTION_NOCLIP:
|
case OPTION_NOCLIP:
|
optbits &= ~(1 << CGEN_INSN_OPTIONAL_CLIP_INSN);
|
optbits &= ~(1 << CGEN_INSN_OPTIONAL_CLIP_INSN);
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
|
break;
|
break;
|
case OPTION_SATUR:
|
case OPTION_SATUR:
|
optbits |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
|
optbits |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
|
break;
|
break;
|
case OPTION_NOSATUR:
|
case OPTION_NOSATUR:
|
optbits &= ~(1 << CGEN_INSN_OPTIONAL_SAT_INSN);
|
optbits &= ~(1 << CGEN_INSN_OPTIONAL_SAT_INSN);
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
|
break;
|
break;
|
case OPTION_COP32:
|
case OPTION_COP32:
|
optbits |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
|
optbits |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
|
break;
|
break;
|
case OPTION_DEBUG:
|
case OPTION_DEBUG:
|
optbits |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
|
optbits |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
|
break;
|
break;
|
case OPTION_NODEBUG:
|
case OPTION_NODEBUG:
|
optbits &= ~(1 << CGEN_INSN_OPTIONAL_DEBUG_INSN);
|
optbits &= ~(1 << CGEN_INSN_OPTIONAL_DEBUG_INSN);
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
|
optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
|
break;
|
break;
|
case OPTION_LIBRARY:
|
case OPTION_LIBRARY:
|
library_flag = EF_MEP_LIBRARY;
|
library_flag = EF_MEP_LIBRARY;
|
break;
|
break;
|
case OPTION_REPEAT:
|
case OPTION_REPEAT:
|
case OPTION_NOREPEAT:
|
case OPTION_NOREPEAT:
|
break;
|
break;
|
default:
|
default:
|
return 0;
|
return 0;
|
}
|
}
|
return 1;
|
return 1;
|
}
|
}
|
|
|
void
|
void
|
md_show_usage (FILE *stream)
|
md_show_usage (FILE *stream)
|
{
|
{
|
fprintf (stream, _("MeP specific command line options:\n\
|
fprintf (stream, _("MeP specific command line options:\n\
|
-EB assemble for a big endian system (default)\n\
|
-EB assemble for a big endian system (default)\n\
|
-EL assemble for a little endian system\n\
|
-EL assemble for a little endian system\n\
|
-mconfig=<name> specify a chip configuration to use\n\
|
-mconfig=<name> specify a chip configuration to use\n\
|
-maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n\
|
-maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n\
|
-mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n\
|
-mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n\
|
-mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n\
|
-mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n\
|
enable/disable the given opcodes\n\
|
enable/disable the given opcodes\n\
|
\n\
|
\n\
|
If -mconfig is given, the other -m options modify it. Otherwise,\n\
|
If -mconfig is given, the other -m options modify it. Otherwise,\n\
|
if no -m options are given, all core opcodes are enabled;\n\
|
if no -m options are given, all core opcodes are enabled;\n\
|
if any enabling -m options are given, only those are enabled;\n\
|
if any enabling -m options are given, only those are enabled;\n\
|
if only disabling -m options are given, only those are disabled.\n\
|
if only disabling -m options are given, only those are disabled.\n\
|
"));
|
"));
|
if (mep_config_map[1].name)
|
if (mep_config_map[1].name)
|
{
|
{
|
int i;
|
int i;
|
fprintf (stream, " -mconfig=STR specify the configuration to use\n");
|
fprintf (stream, " -mconfig=STR specify the configuration to use\n");
|
fprintf (stream, " Configurations:");
|
fprintf (stream, " Configurations:");
|
for (i=0; mep_config_map[i].name; i++)
|
for (i=0; mep_config_map[i].name; i++)
|
fprintf (stream, " %s", mep_config_map[i].name);
|
fprintf (stream, " %s", mep_config_map[i].name);
|
fprintf (stream, "\n");
|
fprintf (stream, "\n");
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
static void
|
static void
|
mep_check_for_disabled_registers (mep_insn *insn)
|
mep_check_for_disabled_registers (mep_insn *insn)
|
{
|
{
|
static int initted = 0;
|
static int initted = 0;
|
static int has_mul_div = 0;
|
static int has_mul_div = 0;
|
static int has_cop = 0;
|
static int has_cop = 0;
|
static int has_debug = 0;
|
static int has_debug = 0;
|
unsigned int b, r;
|
unsigned int b, r;
|
|
|
if (allow_disabled_registers)
|
if (allow_disabled_registers)
|
return;
|
return;
|
|
|
#if !CGEN_INT_INSN_P
|
#if !CGEN_INT_INSN_P
|
if (target_big_endian)
|
if (target_big_endian)
|
b = insn->buffer[0] * 256 + insn->buffer[1];
|
b = insn->buffer[0] * 256 + insn->buffer[1];
|
else
|
else
|
b = insn->buffer[1] * 256 + insn->buffer[0];
|
b = insn->buffer[1] * 256 + insn->buffer[0];
|
#else
|
#else
|
b = insn->buffer[0];
|
b = insn->buffer[0];
|
#endif
|
#endif
|
|
|
if ((b & 0xfffff00e) == 0x7008 /* stc */
|
if ((b & 0xfffff00e) == 0x7008 /* stc */
|
|| (b & 0xfffff00e) == 0x700a /* ldc */)
|
|| (b & 0xfffff00e) == 0x700a /* ldc */)
|
{
|
{
|
if (!initted)
|
if (!initted)
|
{
|
{
|
initted = 1;
|
initted = 1;
|
if ((MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_MUL_INSN))
|
if ((MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_MUL_INSN))
|
|| (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)))
|
|| (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)))
|
has_mul_div = 1;
|
has_mul_div = 1;
|
if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN))
|
if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN))
|
has_debug = 1;
|
has_debug = 1;
|
if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_CP_INSN))
|
if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_CP_INSN))
|
has_cop = 1;
|
has_cop = 1;
|
}
|
}
|
|
|
r = ((b & 0x00f0) >> 4) | ((b & 0x0001) << 4);
|
r = ((b & 0x00f0) >> 4) | ((b & 0x0001) << 4);
|
switch (r)
|
switch (r)
|
{
|
{
|
case 7: /* $hi */
|
case 7: /* $hi */
|
case 8: /* $lo */
|
case 8: /* $lo */
|
if (!has_mul_div)
|
if (!has_mul_div)
|
as_bad ("$hi and $lo are disabled when MUL and DIV are off");
|
as_bad ("$hi and $lo are disabled when MUL and DIV are off");
|
break;
|
break;
|
case 12: /* $mb0 */
|
case 12: /* $mb0 */
|
case 13: /* $me0 */
|
case 13: /* $me0 */
|
case 14: /* $mb1 */
|
case 14: /* $mb1 */
|
case 15: /* $me1 */
|
case 15: /* $me1 */
|
if (!has_cop)
|
if (!has_cop)
|
as_bad ("$mb0, $me0, $mb1, and $me1 are disabled when COP is off");
|
as_bad ("$mb0, $me0, $mb1, and $me1 are disabled when COP is off");
|
break;
|
break;
|
case 24: /* $dbg */
|
case 24: /* $dbg */
|
case 25: /* $depc */
|
case 25: /* $depc */
|
if (!has_debug)
|
if (!has_debug)
|
as_bad ("$dbg and $depc are disabled when DEBUG is off");
|
as_bad ("$dbg and $depc are disabled when DEBUG is off");
|
break;
|
break;
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
static int
|
static int
|
mep_machine (void)
|
mep_machine (void)
|
{
|
{
|
switch (MEP_CPU)
|
switch (MEP_CPU)
|
{
|
{
|
default: break;
|
default: break;
|
case EF_MEP_CPU_C2: return bfd_mach_mep;
|
case EF_MEP_CPU_C2: return bfd_mach_mep;
|
case EF_MEP_CPU_C3: return bfd_mach_mep;
|
case EF_MEP_CPU_C3: return bfd_mach_mep;
|
case EF_MEP_CPU_C4: return bfd_mach_mep;
|
case EF_MEP_CPU_C4: return bfd_mach_mep;
|
case EF_MEP_CPU_H1: return bfd_mach_mep_h1;
|
case EF_MEP_CPU_H1: return bfd_mach_mep_h1;
|
}
|
}
|
|
|
return bfd_mach_mep;
|
return bfd_mach_mep;
|
}
|
}
|
|
|
/* The MeP version of the cgen parse_operand function. The only difference
|
/* The MeP version of the cgen parse_operand function. The only difference
|
from the standard version is that we want to avoid treating '$foo' and
|
from the standard version is that we want to avoid treating '$foo' and
|
'($foo...)' as references to a symbol called '$foo'. The chances are
|
'($foo...)' as references to a symbol called '$foo'. The chances are
|
that '$foo' is really a misspelt register. */
|
that '$foo' is really a misspelt register. */
|
|
|
static const char *
|
static const char *
|
mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
|
mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
|
const char **strP, int opindex, int opinfo,
|
const char **strP, int opindex, int opinfo,
|
enum cgen_parse_operand_result *resultP, bfd_vma *valueP)
|
enum cgen_parse_operand_result *resultP, bfd_vma *valueP)
|
{
|
{
|
if (want == CGEN_PARSE_OPERAND_INTEGER || want == CGEN_PARSE_OPERAND_ADDRESS)
|
if (want == CGEN_PARSE_OPERAND_INTEGER || want == CGEN_PARSE_OPERAND_ADDRESS)
|
{
|
{
|
const char *next;
|
const char *next;
|
|
|
next = *strP;
|
next = *strP;
|
while (*next == '(')
|
while (*next == '(')
|
next++;
|
next++;
|
if (*next == '$')
|
if (*next == '$')
|
return "Not a valid literal";
|
return "Not a valid literal";
|
}
|
}
|
return gas_cgen_parse_operand (cd, want, strP, opindex, opinfo,
|
return gas_cgen_parse_operand (cd, want, strP, opindex, opinfo,
|
resultP, valueP);
|
resultP, valueP);
|
}
|
}
|
|
|
void
|
void
|
md_begin ()
|
md_begin ()
|
{
|
{
|
/* Initialize the `cgen' interface. */
|
/* Initialize the `cgen' interface. */
|
|
|
/* If the user specifies no options, we default to allowing
|
/* If the user specifies no options, we default to allowing
|
everything. If the user specifies any enabling options, we
|
everything. If the user specifies any enabling options, we
|
default to allowing only what is specified. If the user
|
default to allowing only what is specified. If the user
|
specifies only disabling options, we only disable what is
|
specifies only disabling options, we only disable what is
|
specified. If the user specifies options and a config, the
|
specified. If the user specifies options and a config, the
|
options modify the config. */
|
options modify the config. */
|
if (optbits && mep_config_index == 0)
|
if (optbits && mep_config_index == 0)
|
MEP_OMASK = optbits;
|
MEP_OMASK = optbits;
|
else
|
else
|
MEP_OMASK = (MEP_OMASK & ~optbitset) | optbits;
|
MEP_OMASK = (MEP_OMASK & ~optbitset) | optbits;
|
|
|
/* Set the machine number and endian. */
|
/* Set the machine number and endian. */
|
gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
|
gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
|
CGEN_CPU_OPEN_ENDIAN,
|
CGEN_CPU_OPEN_ENDIAN,
|
target_big_endian
|
target_big_endian
|
? CGEN_ENDIAN_BIG
|
? CGEN_ENDIAN_BIG
|
: CGEN_ENDIAN_LITTLE,
|
: CGEN_ENDIAN_LITTLE,
|
CGEN_CPU_OPEN_ISAS, 0,
|
CGEN_CPU_OPEN_ISAS, 0,
|
CGEN_CPU_OPEN_END);
|
CGEN_CPU_OPEN_END);
|
mep_cgen_init_asm (gas_cgen_cpu_desc);
|
mep_cgen_init_asm (gas_cgen_cpu_desc);
|
|
|
/* This is a callback from cgen to gas to parse operands. */
|
/* This is a callback from cgen to gas to parse operands. */
|
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, mep_parse_operand);
|
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, mep_parse_operand);
|
|
|
/* Identify the architecture. */
|
/* Identify the architecture. */
|
bfd_default_set_arch_mach (stdoutput, bfd_arch_mep, mep_machine ());
|
bfd_default_set_arch_mach (stdoutput, bfd_arch_mep, mep_machine ());
|
|
|
/* Store the configuration number and core. */
|
/* Store the configuration number and core. */
|
bfd_set_private_flags (stdoutput, MEP_CPU | MEP_CONFIG | library_flag);
|
bfd_set_private_flags (stdoutput, MEP_CPU | MEP_CONFIG | library_flag);
|
|
|
/* Initialize the array we'll be using to store fixups. */
|
/* Initialize the array we'll be using to store fixups. */
|
gas_cgen_initialize_saved_fixups_array();
|
gas_cgen_initialize_saved_fixups_array();
|
}
|
}
|
|
|
/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
|
/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
|
coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */
|
coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */
|
|
|
static const CGEN_INSN *
|
static const CGEN_INSN *
|
mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd,
|
mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd,
|
const char *str,
|
const char *str,
|
CGEN_FIELDS *fields,
|
CGEN_FIELDS *fields,
|
CGEN_INSN_BYTES_PTR buf,
|
CGEN_INSN_BYTES_PTR buf,
|
const struct cgen_insn *pinsn)
|
const struct cgen_insn *pinsn)
|
{
|
{
|
const char *start;
|
const char *start;
|
CGEN_INSN_LIST *ilist;
|
CGEN_INSN_LIST *ilist;
|
const char *errmsg = NULL;
|
const char *errmsg = NULL;
|
|
|
/* The instructions are stored in hashed lists. */
|
/* The instructions are stored in hashed lists. */
|
ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc,
|
ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc,
|
CGEN_INSN_MNEMONIC (pinsn));
|
CGEN_INSN_MNEMONIC (pinsn));
|
|
|
start = str;
|
start = str;
|
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
|
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
|
{
|
{
|
const CGEN_INSN *insn = ilist->insn;
|
const CGEN_INSN *insn = ilist->insn;
|
if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn),
|
if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn),
|
CGEN_INSN_MNEMONIC (pinsn)) == 0
|
CGEN_INSN_MNEMONIC (pinsn)) == 0
|
&& MEP_INSN_COP_P (ilist->insn)
|
&& MEP_INSN_COP_P (ilist->insn)
|
&& mep_cgen_insn_supported (cd, insn))
|
&& mep_cgen_insn_supported (cd, insn))
|
{
|
{
|
str = start;
|
str = start;
|
|
|
/* skip this insn if str doesn't look right lexically */
|
/* skip this insn if str doesn't look right lexically */
|
if (CGEN_INSN_RX (insn) != NULL &&
|
if (CGEN_INSN_RX (insn) != NULL &&
|
regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
|
regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
|
continue;
|
continue;
|
|
|
/* Allow parse/insert handlers to obtain length of insn. */
|
/* Allow parse/insert handlers to obtain length of insn. */
|
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
|
|
errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
|
errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
|
if (errmsg != NULL)
|
if (errmsg != NULL)
|
continue;
|
continue;
|
|
|
errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
|
errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
|
(bfd_vma) 0);
|
(bfd_vma) 0);
|
if (errmsg != NULL)
|
if (errmsg != NULL)
|
continue;
|
continue;
|
|
|
return insn;
|
return insn;
|
}
|
}
|
}
|
}
|
return pinsn;
|
return pinsn;
|
}
|
}
|
|
|
static void
|
static void
|
mep_save_insn (mep_insn insn)
|
mep_save_insn (mep_insn insn)
|
{
|
{
|
/* Consider change MAX_SAVED_FIXUP_CHAINS to MAX_PARALLEL_INSNS. */
|
/* Consider change MAX_SAVED_FIXUP_CHAINS to MAX_PARALLEL_INSNS. */
|
if (num_insns_saved < 0 || num_insns_saved >= MAX_SAVED_FIXUP_CHAINS)
|
if (num_insns_saved < 0 || num_insns_saved >= MAX_SAVED_FIXUP_CHAINS)
|
{
|
{
|
as_fatal("index into saved_insns[] out of bounds.");
|
as_fatal("index into saved_insns[] out of bounds.");
|
return;
|
return;
|
}
|
}
|
saved_insns[num_insns_saved] = insn;
|
saved_insns[num_insns_saved] = insn;
|
gas_cgen_save_fixups(num_insns_saved);
|
gas_cgen_save_fixups(num_insns_saved);
|
num_insns_saved++;
|
num_insns_saved++;
|
}
|
}
|
|
|
static void
|
static void
|
mep_check_parallel32_scheduling (void)
|
mep_check_parallel32_scheduling (void)
|
{
|
{
|
int insn0iscopro, insn1iscopro, insn0length, insn1length;
|
int insn0iscopro, insn1iscopro, insn0length, insn1length;
|
|
|
/* More than two instructions means that either someone is referring to
|
/* More than two instructions means that either someone is referring to
|
an internally parallel core or an internally parallel coprocessor,
|
an internally parallel core or an internally parallel coprocessor,
|
neither of which are supported at this time. */
|
neither of which are supported at this time. */
|
if ( num_insns_saved > 2 )
|
if ( num_insns_saved > 2 )
|
as_fatal("Internally paralled cores and coprocessors not supported.");
|
as_fatal("Internally paralled cores and coprocessors not supported.");
|
|
|
/* If there are no insns saved, that's ok. Just return. This will
|
/* If there are no insns saved, that's ok. Just return. This will
|
happen when mep_process_saved_insns is called when the end of the
|
happen when mep_process_saved_insns is called when the end of the
|
source file is reached and there are no insns left to be processed. */
|
source file is reached and there are no insns left to be processed. */
|
if (num_insns_saved == 0)
|
if (num_insns_saved == 0)
|
return;
|
return;
|
|
|
/* Check some of the attributes of the first insn. */
|
/* Check some of the attributes of the first insn. */
|
insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
|
insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
|
insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
|
insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
|
|
|
if (num_insns_saved == 2)
|
if (num_insns_saved == 2)
|
{
|
{
|
/* Check some of the attributes of the first insn. */
|
/* Check some of the attributes of the first insn. */
|
insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
|
insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
|
insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
|
insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
|
|
|
if ((insn0iscopro && !insn1iscopro)
|
if ((insn0iscopro && !insn1iscopro)
|
|| (insn1iscopro && !insn0iscopro))
|
|| (insn1iscopro && !insn0iscopro))
|
{
|
{
|
/* We have one core and one copro insn. If their sizes
|
/* We have one core and one copro insn. If their sizes
|
add up to 32, then the combination is valid. */
|
add up to 32, then the combination is valid. */
|
if (insn0length + insn1length == 32)
|
if (insn0length + insn1length == 32)
|
return;
|
return;
|
else
|
else
|
as_bad ("core and copro insn lengths must total 32 bits.");
|
as_bad ("core and copro insn lengths must total 32 bits.");
|
}
|
}
|
else
|
else
|
as_bad ("vliw group must consist of 1 core and 1 copro insn.");
|
as_bad ("vliw group must consist of 1 core and 1 copro insn.");
|
}
|
}
|
else
|
else
|
{
|
{
|
/* If we arrive here, we have one saved instruction. There are a
|
/* If we arrive here, we have one saved instruction. There are a
|
number of possible cases:
|
number of possible cases:
|
|
|
1. The instruction is a 32 bit core or coprocessor insn and
|
1. The instruction is a 32 bit core or coprocessor insn and
|
can be executed by itself. Valid.
|
can be executed by itself. Valid.
|
|
|
2. The instrucion is a core instruction for which a cop nop
|
2. The instrucion is a core instruction for which a cop nop
|
exists. In this case, insert the cop nop into the saved
|
exists. In this case, insert the cop nop into the saved
|
insn array after the core insn and return. Valid.
|
insn array after the core insn and return. Valid.
|
|
|
3. The instruction is a coprocessor insn for which a core nop
|
3. The instruction is a coprocessor insn for which a core nop
|
exists. In this case, move the coprocessor insn to the
|
exists. In this case, move the coprocessor insn to the
|
second element of the array and put the nop in the first
|
second element of the array and put the nop in the first
|
element then return. Valid.
|
element then return. Valid.
|
|
|
4. The instruction is a core or coprocessor instruction for
|
4. The instruction is a core or coprocessor instruction for
|
which there is no matching coprocessor or core nop to use
|
which there is no matching coprocessor or core nop to use
|
to form a valid vliw insn combination. In this case, we
|
to form a valid vliw insn combination. In this case, we
|
we have to abort. */
|
we have to abort. */
|
|
|
if (insn0length > 32)
|
if (insn0length > 32)
|
as_fatal ("Cannot use 48- or 64-bit insns with a 32 bit datapath.");
|
as_fatal ("Cannot use 48- or 64-bit insns with a 32 bit datapath.");
|
|
|
if (insn0length == 32)
|
if (insn0length == 32)
|
return;
|
return;
|
|
|
/* Insn is smaller than datapath. If there are no matching
|
/* Insn is smaller than datapath. If there are no matching
|
nops for this insn, then terminate assembly. */
|
nops for this insn, then terminate assembly. */
|
if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
|
if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
|
CGEN_INSN_VLIW32_NO_MATCHING_NOP))
|
CGEN_INSN_VLIW32_NO_MATCHING_NOP))
|
as_fatal ("No valid nop.");
|
as_fatal ("No valid nop.");
|
|
|
/* At this point we know that we have a single 16-bit insn that has
|
/* At this point we know that we have a single 16-bit insn that has
|
a matching nop. We have to assemble it and put it into the saved
|
a matching nop. We have to assemble it and put it into the saved
|
insn and fixup chain arrays. */
|
insn and fixup chain arrays. */
|
|
|
if (insn0iscopro)
|
if (insn0iscopro)
|
{
|
{
|
char *errmsg;
|
char *errmsg;
|
mep_insn insn;
|
mep_insn insn;
|
|
|
/* Move the insn and it's fixups to the second element of the
|
/* Move the insn and it's fixups to the second element of the
|
saved insns arrary and insert a 16 bit core nope into the
|
saved insns arrary and insert a 16 bit core nope into the
|
first element. */
|
first element. */
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
|
&insn.fields, insn.buffer,
|
&insn.fields, insn.buffer,
|
&errmsg);
|
&errmsg);
|
if (!insn.insn)
|
if (!insn.insn)
|
{
|
{
|
as_bad ("%s", errmsg);
|
as_bad ("%s", errmsg);
|
return;
|
return;
|
}
|
}
|
|
|
/* Move the insn in element 0 to element 1 and insert the
|
/* Move the insn in element 0 to element 1 and insert the
|
nop into element 0. Move the fixups in element 0 to
|
nop into element 0. Move the fixups in element 0 to
|
element 1 and save the current fixups to element 0.
|
element 1 and save the current fixups to element 0.
|
Really there aren't any fixups at this point because we're
|
Really there aren't any fixups at this point because we're
|
inserting a nop but we might as well be general so that
|
inserting a nop but we might as well be general so that
|
if there's ever a need to insert a general insn, we'll
|
if there's ever a need to insert a general insn, we'll
|
have an example. */
|
have an example. */
|
saved_insns[1] = saved_insns[0];
|
saved_insns[1] = saved_insns[0];
|
saved_insns[0] = insn;
|
saved_insns[0] = insn;
|
num_insns_saved++;
|
num_insns_saved++;
|
gas_cgen_swap_fixups (0);
|
gas_cgen_swap_fixups (0);
|
gas_cgen_save_fixups (1);
|
gas_cgen_save_fixups (1);
|
}
|
}
|
else
|
else
|
{
|
{
|
char * errmsg;
|
char * errmsg;
|
mep_insn insn;
|
mep_insn insn;
|
int insn_num = saved_insns[0].insn->base->num;
|
int insn_num = saved_insns[0].insn->base->num;
|
|
|
/* Use 32 bit branches and skip the nop. */
|
/* Use 32 bit branches and skip the nop. */
|
if (insn_num == MEP_INSN_BSR12
|
if (insn_num == MEP_INSN_BSR12
|
|| insn_num == MEP_INSN_BEQZ
|
|| insn_num == MEP_INSN_BEQZ
|
|| insn_num == MEP_INSN_BNEZ)
|
|| insn_num == MEP_INSN_BNEZ)
|
return;
|
return;
|
|
|
/* Insert a 16-bit coprocessor nop. Note that at the time */
|
/* Insert a 16-bit coprocessor nop. Note that at the time */
|
/* this was done, no 16-bit coprocessor nop was defined. */
|
/* this was done, no 16-bit coprocessor nop was defined. */
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
|
&insn.fields, insn.buffer,
|
&insn.fields, insn.buffer,
|
&errmsg);
|
&errmsg);
|
if (!insn.insn)
|
if (!insn.insn)
|
{
|
{
|
as_bad ("%s", errmsg);
|
as_bad ("%s", errmsg);
|
return;
|
return;
|
}
|
}
|
|
|
/* Now put the insn and fixups into the arrays. */
|
/* Now put the insn and fixups into the arrays. */
|
mep_save_insn (insn);
|
mep_save_insn (insn);
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
static void
|
static void
|
mep_check_parallel64_scheduling (void)
|
mep_check_parallel64_scheduling (void)
|
{
|
{
|
int insn0iscopro, insn1iscopro, insn0length, insn1length;
|
int insn0iscopro, insn1iscopro, insn0length, insn1length;
|
|
|
/* More than two instructions means that someone is referring to an
|
/* More than two instructions means that someone is referring to an
|
internally parallel core or an internally parallel coprocessor. */
|
internally parallel core or an internally parallel coprocessor. */
|
/* These are not currently supported. */
|
/* These are not currently supported. */
|
if (num_insns_saved > 2)
|
if (num_insns_saved > 2)
|
as_fatal ("Internally parallel cores of coprocessors not supported.");
|
as_fatal ("Internally parallel cores of coprocessors not supported.");
|
|
|
/* If there are no insns saved, that's ok. Just return. This will
|
/* If there are no insns saved, that's ok. Just return. This will
|
happen when mep_process_saved_insns is called when the end of the
|
happen when mep_process_saved_insns is called when the end of the
|
source file is reached and there are no insns left to be processed. */
|
source file is reached and there are no insns left to be processed. */
|
if (num_insns_saved == 0)
|
if (num_insns_saved == 0)
|
return;
|
return;
|
|
|
/* Check some of the attributes of the first insn. */
|
/* Check some of the attributes of the first insn. */
|
insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
|
insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
|
insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
|
insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
|
|
|
if (num_insns_saved == 2)
|
if (num_insns_saved == 2)
|
{
|
{
|
/* Check some of the attributes of the first insn. */
|
/* Check some of the attributes of the first insn. */
|
insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
|
insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
|
insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
|
insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
|
|
|
if ((insn0iscopro && !insn1iscopro)
|
if ((insn0iscopro && !insn1iscopro)
|
|| (insn1iscopro && !insn0iscopro))
|
|| (insn1iscopro && !insn0iscopro))
|
{
|
{
|
/* We have one core and one copro insn. If their sizes
|
/* We have one core and one copro insn. If their sizes
|
add up to 64, then the combination is valid. */
|
add up to 64, then the combination is valid. */
|
if (insn0length + insn1length == 64)
|
if (insn0length + insn1length == 64)
|
return;
|
return;
|
else
|
else
|
as_bad ("core and copro insn lengths must total 64 bits.");
|
as_bad ("core and copro insn lengths must total 64 bits.");
|
}
|
}
|
else
|
else
|
as_bad ("vliw group must consist of 1 core and 1 copro insn.");
|
as_bad ("vliw group must consist of 1 core and 1 copro insn.");
|
}
|
}
|
else
|
else
|
{
|
{
|
/* If we arrive here, we have one saved instruction. There are a
|
/* If we arrive here, we have one saved instruction. There are a
|
number of possible cases:
|
number of possible cases:
|
|
|
1. The instruction is a 64 bit coprocessor insn and can be
|
1. The instruction is a 64 bit coprocessor insn and can be
|
executed by itself. Valid.
|
executed by itself. Valid.
|
|
|
2. The instrucion is a core instruction for which a cop nop
|
2. The instrucion is a core instruction for which a cop nop
|
exists. In this case, insert the cop nop into the saved
|
exists. In this case, insert the cop nop into the saved
|
insn array after the core insn and return. Valid.
|
insn array after the core insn and return. Valid.
|
|
|
3. The instruction is a coprocessor insn for which a core nop
|
3. The instruction is a coprocessor insn for which a core nop
|
exists. In this case, move the coprocessor insn to the
|
exists. In this case, move the coprocessor insn to the
|
second element of the array and put the nop in the first
|
second element of the array and put the nop in the first
|
element then return. Valid.
|
element then return. Valid.
|
|
|
4. The instruction is a core or coprocessor instruction for
|
4. The instruction is a core or coprocessor instruction for
|
which there is no matching coprocessor or core nop to use
|
which there is no matching coprocessor or core nop to use
|
to form a valid vliw insn combination. In this case, we
|
to form a valid vliw insn combination. In this case, we
|
we have to abort. */
|
we have to abort. */
|
|
|
/* If the insn is 64 bits long, it can run alone. The size check
|
/* If the insn is 64 bits long, it can run alone. The size check
|
is done indepependantly of whether the insn is core or copro
|
is done indepependantly of whether the insn is core or copro
|
in case 64 bit coprocessor insns are added later. */
|
in case 64 bit coprocessor insns are added later. */
|
if (insn0length == 64)
|
if (insn0length == 64)
|
return;
|
return;
|
|
|
/* Insn is smaller than datapath. If there are no matching
|
/* Insn is smaller than datapath. If there are no matching
|
nops for this insn, then terminate assembly. */
|
nops for this insn, then terminate assembly. */
|
if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
|
if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
|
CGEN_INSN_VLIW64_NO_MATCHING_NOP))
|
CGEN_INSN_VLIW64_NO_MATCHING_NOP))
|
as_fatal ("No valid nop.");
|
as_fatal ("No valid nop.");
|
|
|
if (insn0iscopro)
|
if (insn0iscopro)
|
{
|
{
|
char *errmsg;
|
char *errmsg;
|
mep_insn insn;
|
mep_insn insn;
|
int i;
|
int i;
|
|
|
/* Initialize the insn buffer. */
|
/* Initialize the insn buffer. */
|
for (i = 0; i < 64; i++)
|
for (i = 0; i < 64; i++)
|
insn.buffer[i] = '\0';
|
insn.buffer[i] = '\0';
|
|
|
/* We have a coprocessor insn. At this point in time there
|
/* We have a coprocessor insn. At this point in time there
|
are is 32-bit core nop. There is only a 16-bit core
|
are is 32-bit core nop. There is only a 16-bit core
|
nop. The idea is to allow for a relatively arbitrary
|
nop. The idea is to allow for a relatively arbitrary
|
coprocessor to be specified. We aren't looking at
|
coprocessor to be specified. We aren't looking at
|
trying to cover future changes in the core at this time
|
trying to cover future changes in the core at this time
|
since it is assumed that the core will remain fairly
|
since it is assumed that the core will remain fairly
|
static. If there ever are 32 or 48 bit core nops added,
|
static. If there ever are 32 or 48 bit core nops added,
|
they will require entries below. */
|
they will require entries below. */
|
|
|
if (insn0length == 48)
|
if (insn0length == 48)
|
{
|
{
|
/* Move the insn and fixups to the second element of the
|
/* Move the insn and fixups to the second element of the
|
arrays then assemble and insert a 16 bit core nop. */
|
arrays then assemble and insert a 16 bit core nop. */
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
|
& insn.fields, insn.buffer,
|
& insn.fields, insn.buffer,
|
& errmsg);
|
& errmsg);
|
}
|
}
|
else
|
else
|
{
|
{
|
/* If this is reached, then we have a single coprocessor
|
/* If this is reached, then we have a single coprocessor
|
insn that is not 48 bits long, but for which the assembler
|
insn that is not 48 bits long, but for which the assembler
|
thinks there is a matching core nop. If a 32-bit core
|
thinks there is a matching core nop. If a 32-bit core
|
nop has been added, then make the necessary changes and
|
nop has been added, then make the necessary changes and
|
handle its assembly and insertion here. Otherwise,
|
handle its assembly and insertion here. Otherwise,
|
go figure out why either:
|
go figure out why either:
|
|
|
1. The assembler thinks that there is a 32-bit core nop
|
1. The assembler thinks that there is a 32-bit core nop
|
to match a 32-bit coprocessor insn, or
|
to match a 32-bit coprocessor insn, or
|
2. The assembler thinks that there is a 48-bit core nop
|
2. The assembler thinks that there is a 48-bit core nop
|
to match a 16-bit coprocessor insn. */
|
to match a 16-bit coprocessor insn. */
|
|
|
as_fatal ("Assembler expects a non-existent core nop.");
|
as_fatal ("Assembler expects a non-existent core nop.");
|
}
|
}
|
|
|
if (!insn.insn)
|
if (!insn.insn)
|
{
|
{
|
as_bad ("%s", errmsg);
|
as_bad ("%s", errmsg);
|
return;
|
return;
|
}
|
}
|
|
|
/* Move the insn in element 0 to element 1 and insert the
|
/* Move the insn in element 0 to element 1 and insert the
|
nop into element 0. Move the fixups in element 0 to
|
nop into element 0. Move the fixups in element 0 to
|
element 1 and save the current fixups to element 0.
|
element 1 and save the current fixups to element 0.
|
Really there aren't any fixups at this point because we're
|
Really there aren't any fixups at this point because we're
|
inserting a nop but we might as well be general so that
|
inserting a nop but we might as well be general so that
|
if there's ever a need to insert a general insn, we'll
|
if there's ever a need to insert a general insn, we'll
|
have an example. */
|
have an example. */
|
|
|
saved_insns[1] = saved_insns[0];
|
saved_insns[1] = saved_insns[0];
|
saved_insns[0] = insn;
|
saved_insns[0] = insn;
|
num_insns_saved++;
|
num_insns_saved++;
|
gas_cgen_swap_fixups(0);
|
gas_cgen_swap_fixups(0);
|
gas_cgen_save_fixups(1);
|
gas_cgen_save_fixups(1);
|
|
|
}
|
}
|
else
|
else
|
{
|
{
|
char * errmsg;
|
char * errmsg;
|
mep_insn insn;
|
mep_insn insn;
|
int i;
|
int i;
|
|
|
/* Initialize the insn buffer */
|
/* Initialize the insn buffer */
|
for (i = 0; i < 64; i++)
|
for (i = 0; i < 64; i++)
|
insn.buffer[i] = '\0';
|
insn.buffer[i] = '\0';
|
|
|
/* We have a core insn. We have to handle all possible nop
|
/* We have a core insn. We have to handle all possible nop
|
lengths. If a coprocessor doesn't have a nop of a certain
|
lengths. If a coprocessor doesn't have a nop of a certain
|
length but there exists core insns that when combined with
|
length but there exists core insns that when combined with
|
a nop of that length would fill the datapath, those core
|
a nop of that length would fill the datapath, those core
|
insns will be flagged with the VLIW_NO_CORRESPONDING_NOP
|
insns will be flagged with the VLIW_NO_CORRESPONDING_NOP
|
attribute. That will ensure that when used in a way that
|
attribute. That will ensure that when used in a way that
|
requires a nop to be inserted, assembly will terminate
|
requires a nop to be inserted, assembly will terminate
|
before reaching this section of code. This guarantees
|
before reaching this section of code. This guarantees
|
that cases below which would result in the attempted
|
that cases below which would result in the attempted
|
insertion of nop that doesn't exist will never be entered. */
|
insertion of nop that doesn't exist will never be entered. */
|
if (insn0length == 16)
|
if (insn0length == 16)
|
{
|
{
|
/* Insert 48 bit coprocessor nop. */
|
/* Insert 48 bit coprocessor nop. */
|
/* Assemble it and put it into the arrays. */
|
/* Assemble it and put it into the arrays. */
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop48",
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop48",
|
&insn.fields, insn.buffer,
|
&insn.fields, insn.buffer,
|
&errmsg);
|
&errmsg);
|
}
|
}
|
else if (insn0length == 32)
|
else if (insn0length == 32)
|
{
|
{
|
/* Insert 32 bit coprocessor nop. */
|
/* Insert 32 bit coprocessor nop. */
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop32",
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop32",
|
&insn.fields, insn.buffer,
|
&insn.fields, insn.buffer,
|
&errmsg);
|
&errmsg);
|
}
|
}
|
else if (insn0length == 48)
|
else if (insn0length == 48)
|
{
|
{
|
/* Insert 16 bit coprocessor nop. */
|
/* Insert 16 bit coprocessor nop. */
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
|
&insn.fields, insn.buffer,
|
&insn.fields, insn.buffer,
|
&errmsg);
|
&errmsg);
|
}
|
}
|
else
|
else
|
/* Core insn has an invalid length. Something has gone wrong. */
|
/* Core insn has an invalid length. Something has gone wrong. */
|
as_fatal ("Core insn has invalid length! Something is wrong!");
|
as_fatal ("Core insn has invalid length! Something is wrong!");
|
|
|
if (!insn.insn)
|
if (!insn.insn)
|
{
|
{
|
as_bad ("%s", errmsg);
|
as_bad ("%s", errmsg);
|
return;
|
return;
|
}
|
}
|
|
|
/* Now put the insn and fixups into the arrays. */
|
/* Now put the insn and fixups into the arrays. */
|
mep_save_insn (insn);
|
mep_save_insn (insn);
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* The scheduling functions are just filters for invalid combinations.
|
/* The scheduling functions are just filters for invalid combinations.
|
If there is a violation, they terminate assembly. Otherise they
|
If there is a violation, they terminate assembly. Otherise they
|
just fall through. Succesful combinations cause no side effects
|
just fall through. Succesful combinations cause no side effects
|
other than valid nop insertion. */
|
other than valid nop insertion. */
|
|
|
static void
|
static void
|
mep_check_parallel_scheduling (void)
|
mep_check_parallel_scheduling (void)
|
{
|
{
|
/* This is where we will eventually read the config information
|
/* This is where we will eventually read the config information
|
and choose which scheduling checking function to call. */
|
and choose which scheduling checking function to call. */
|
if (MEP_VLIW64)
|
if (MEP_VLIW64)
|
mep_check_parallel64_scheduling ();
|
mep_check_parallel64_scheduling ();
|
else
|
else
|
mep_check_parallel32_scheduling ();
|
mep_check_parallel32_scheduling ();
|
}
|
}
|
|
|
static void
|
static void
|
mep_process_saved_insns (void)
|
mep_process_saved_insns (void)
|
{
|
{
|
int i;
|
int i;
|
|
|
gas_cgen_save_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
|
gas_cgen_save_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
|
|
|
/* We have to check for valid scheduling here. */
|
/* We have to check for valid scheduling here. */
|
mep_check_parallel_scheduling ();
|
mep_check_parallel_scheduling ();
|
|
|
/* If the last call didn't cause assembly to terminate, we have
|
/* If the last call didn't cause assembly to terminate, we have
|
a valid vliw insn/insn pair saved. Restore this instructions'
|
a valid vliw insn/insn pair saved. Restore this instructions'
|
fixups and process the insns. */
|
fixups and process the insns. */
|
for (i = 0;i<num_insns_saved;i++)
|
for (i = 0;i<num_insns_saved;i++)
|
{
|
{
|
gas_cgen_restore_fixups (i);
|
gas_cgen_restore_fixups (i);
|
gas_cgen_finish_insn (saved_insns[i].insn, saved_insns[i].buffer,
|
gas_cgen_finish_insn (saved_insns[i].insn, saved_insns[i].buffer,
|
CGEN_FIELDS_BITSIZE (& saved_insns[i].fields),
|
CGEN_FIELDS_BITSIZE (& saved_insns[i].fields),
|
1, NULL);
|
1, NULL);
|
}
|
}
|
gas_cgen_restore_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
|
gas_cgen_restore_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
|
|
|
/* Clear the fixups and reset the number insn saved to 0. */
|
/* Clear the fixups and reset the number insn saved to 0. */
|
gas_cgen_initialize_saved_fixups_array ();
|
gas_cgen_initialize_saved_fixups_array ();
|
num_insns_saved = 0;
|
num_insns_saved = 0;
|
listing_prev_line ();
|
listing_prev_line ();
|
}
|
}
|
|
|
void
|
void
|
md_assemble (char * str)
|
md_assemble (char * str)
|
{
|
{
|
static CGEN_BITSET* isas = NULL;
|
static CGEN_BITSET* isas = NULL;
|
char * errmsg;
|
char * errmsg;
|
|
|
/* Initialize GAS's cgen interface for a new instruction. */
|
/* Initialize GAS's cgen interface for a new instruction. */
|
gas_cgen_init_parse ();
|
gas_cgen_init_parse ();
|
|
|
/* There are two possible modes: core and vliw. We have to assemble
|
/* There are two possible modes: core and vliw. We have to assemble
|
differently for each.
|
differently for each.
|
|
|
Core Mode: We assemble normally. All instructions are on a
|
Core Mode: We assemble normally. All instructions are on a
|
single line and are made up of one mnemonic and one
|
single line and are made up of one mnemonic and one
|
set of operands.
|
set of operands.
|
VLIW Mode: Vliw combinations are indicated as follows:
|
VLIW Mode: Vliw combinations are indicated as follows:
|
|
|
core insn
|
core insn
|
+ copro insn
|
+ copro insn
|
|
|
We want to handle the general case where more than
|
We want to handle the general case where more than
|
one instruction can be preceeded by a +. This will
|
one instruction can be preceeded by a +. This will
|
happen later if we add support for internally parallel
|
happen later if we add support for internally parallel
|
coprocessors. We'll make the parsing nice and general
|
coprocessors. We'll make the parsing nice and general
|
so that it can handle an arbitrary number of insns
|
so that it can handle an arbitrary number of insns
|
with leading +'s. The actual checking for valid
|
with leading +'s. The actual checking for valid
|
combinations is done elsewhere. */
|
combinations is done elsewhere. */
|
|
|
/* Initialize the isa to refer to the core. */
|
/* Initialize the isa to refer to the core. */
|
if (isas == NULL)
|
if (isas == NULL)
|
isas = cgen_bitset_copy (& MEP_CORE_ISA);
|
isas = cgen_bitset_copy (& MEP_CORE_ISA);
|
else
|
else
|
{
|
{
|
cgen_bitset_clear (isas);
|
cgen_bitset_clear (isas);
|
cgen_bitset_union (isas, & MEP_CORE_ISA, isas);
|
cgen_bitset_union (isas, & MEP_CORE_ISA, isas);
|
}
|
}
|
gas_cgen_cpu_desc->isas = isas;
|
gas_cgen_cpu_desc->isas = isas;
|
|
|
if (mode == VLIW)
|
if (mode == VLIW)
|
{
|
{
|
/* VLIW mode. */
|
/* VLIW mode. */
|
|
|
int thisInsnIsCopro = 0;
|
int thisInsnIsCopro = 0;
|
mep_insn insn;
|
mep_insn insn;
|
int i;
|
int i;
|
|
|
/* Initialize the insn buffer */
|
/* Initialize the insn buffer */
|
|
|
if (! CGEN_INT_INSN_P)
|
if (! CGEN_INT_INSN_P)
|
for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
|
for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
|
insn.buffer[i]='\0';
|
insn.buffer[i]='\0';
|
|
|
/* Can't tell core / copro insns apart at parse time! */
|
/* Can't tell core / copro insns apart at parse time! */
|
cgen_bitset_union (isas, & MEP_COP_ISA, isas);
|
cgen_bitset_union (isas, & MEP_COP_ISA, isas);
|
|
|
/* Assemble the insn so we can examine its attributes. */
|
/* Assemble the insn so we can examine its attributes. */
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, str,
|
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, str,
|
&insn.fields, insn.buffer,
|
&insn.fields, insn.buffer,
|
&errmsg);
|
&errmsg);
|
if (!insn.insn)
|
if (!insn.insn)
|
{
|
{
|
as_bad ("%s", errmsg);
|
as_bad ("%s", errmsg);
|
return;
|
return;
|
}
|
}
|
mep_check_for_disabled_registers (&insn);
|
mep_check_for_disabled_registers (&insn);
|
|
|
/* Check to see if it's a coprocessor instruction. */
|
/* Check to see if it's a coprocessor instruction. */
|
thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
|
thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
|
|
|
if (!thisInsnIsCopro)
|
if (!thisInsnIsCopro)
|
{
|
{
|
insn.insn = mep_cgen_assemble_cop_insn (gas_cgen_cpu_desc, str,
|
insn.insn = mep_cgen_assemble_cop_insn (gas_cgen_cpu_desc, str,
|
&insn.fields, insn.buffer,
|
&insn.fields, insn.buffer,
|
insn.insn);
|
insn.insn);
|
thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
|
thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
|
mep_check_for_disabled_registers (&insn);
|
mep_check_for_disabled_registers (&insn);
|
}
|
}
|
|
|
if (pluspresent)
|
if (pluspresent)
|
{
|
{
|
/* A plus was present. */
|
/* A plus was present. */
|
/* Check for a + with a core insn and abort if found. */
|
/* Check for a + with a core insn and abort if found. */
|
if (!thisInsnIsCopro)
|
if (!thisInsnIsCopro)
|
{
|
{
|
as_fatal("A core insn cannot be preceeded by a +.\n");
|
as_fatal("A core insn cannot be preceeded by a +.\n");
|
return;
|
return;
|
}
|
}
|
|
|
if (num_insns_saved > 0)
|
if (num_insns_saved > 0)
|
{
|
{
|
/* There are insns in the queue. Add this one. */
|
/* There are insns in the queue. Add this one. */
|
mep_save_insn (insn);
|
mep_save_insn (insn);
|
}
|
}
|
else
|
else
|
{
|
{
|
/* There are no insns in the queue and a plus is present.
|
/* There are no insns in the queue and a plus is present.
|
This is a syntax error. Let's not tolerate this.
|
This is a syntax error. Let's not tolerate this.
|
We can relax this later if necessary. */
|
We can relax this later if necessary. */
|
as_bad (_("Invalid use of parallelization operator."));
|
as_bad (_("Invalid use of parallelization operator."));
|
return;
|
return;
|
}
|
}
|
}
|
}
|
else
|
else
|
{
|
{
|
/* No plus was present. */
|
/* No plus was present. */
|
if (num_insns_saved > 0)
|
if (num_insns_saved > 0)
|
{
|
{
|
/* There are insns saved and we came across an insn without a
|
/* There are insns saved and we came across an insn without a
|
leading +. That's the signal to process the saved insns
|
leading +. That's the signal to process the saved insns
|
before proceeding then treat the current insn as the first
|
before proceeding then treat the current insn as the first
|
in a new vliw group. */
|
in a new vliw group. */
|
mep_process_saved_insns ();
|
mep_process_saved_insns ();
|
num_insns_saved = 0;
|
num_insns_saved = 0;
|
/* mep_save_insn (insn); */
|
/* mep_save_insn (insn); */
|
}
|
}
|
mep_save_insn (insn);
|
mep_save_insn (insn);
|
#if 0
|
#if 0
|
else
|
else
|
{
|
{
|
|
|
/* Core Insn. Add it to the beginning of the queue. */
|
/* Core Insn. Add it to the beginning of the queue. */
|
mep_save_insn (insn);
|
mep_save_insn (insn);
|
/* gas_cgen_save_fixups(num_insns_saved); */
|
/* gas_cgen_save_fixups(num_insns_saved); */
|
}
|
}
|
#endif
|
#endif
|
}
|
}
|
|
|
pluspresent = 0;
|
pluspresent = 0;
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Core mode. */
|
/* Core mode. */
|
|
|
/* Only single instructions are assembled in core mode. */
|
/* Only single instructions are assembled in core mode. */
|
mep_insn insn;
|
mep_insn insn;
|
|
|
/* If a leading '+' was present, issue an error.
|
/* If a leading '+' was present, issue an error.
|
That's not allowed in core mode. */
|
That's not allowed in core mode. */
|
if (pluspresent)
|
if (pluspresent)
|
{
|
{
|
as_bad (_("Leading plus sign not allowed in core mode"));
|
as_bad (_("Leading plus sign not allowed in core mode"));
|
return;
|
return;
|
}
|
}
|
|
|
insn.insn = mep_cgen_assemble_insn
|
insn.insn = mep_cgen_assemble_insn
|
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
|
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
|
|
|
if (!insn.insn)
|
if (!insn.insn)
|
{
|
{
|
as_bad ("%s", errmsg);
|
as_bad ("%s", errmsg);
|
return;
|
return;
|
}
|
}
|
gas_cgen_finish_insn (insn.insn, insn.buffer,
|
gas_cgen_finish_insn (insn.insn, insn.buffer,
|
CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
|
CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
|
mep_check_for_disabled_registers (&insn);
|
mep_check_for_disabled_registers (&insn);
|
}
|
}
|
}
|
}
|
|
|
valueT
|
valueT
|
md_section_align (segT segment, valueT size)
|
md_section_align (segT segment, valueT size)
|
{
|
{
|
int align = bfd_get_section_alignment (stdoutput, segment);
|
int align = bfd_get_section_alignment (stdoutput, segment);
|
return ((size + (1 << align) - 1) & (-1 << align));
|
return ((size + (1 << align) - 1) & (-1 << align));
|
}
|
}
|
|
|
|
|
symbolS *
|
symbolS *
|
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
|
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
|
{
|
{
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Interface to relax_segment. */
|
/* Interface to relax_segment. */
|
|
|
|
|
const relax_typeS md_relax_table[] =
|
const relax_typeS md_relax_table[] =
|
{
|
{
|
/* The fields are:
|
/* The fields are:
|
1) most positive reach of this state,
|
1) most positive reach of this state,
|
2) most negative reach of this state,
|
2) most negative reach of this state,
|
3) how many bytes this mode will have in the variable part of the frag
|
3) how many bytes this mode will have in the variable part of the frag
|
4) which index into the table to try if we can't fit into this one. */
|
4) which index into the table to try if we can't fit into this one. */
|
/* Note that we use "beq" because "jmp" has a peculiarity - it cannot
|
/* Note that we use "beq" because "jmp" has a peculiarity - it cannot
|
jump to addresses with any bits 27..24 set. So, we use beq as a
|
jump to addresses with any bits 27..24 set. So, we use beq as a
|
17-bit pc-relative branch to avoid using jmp, just in case. */
|
17-bit pc-relative branch to avoid using jmp, just in case. */
|
|
|
/* 0 */ { 0, 0, 0, 0 }, /* unused */
|
/* 0 */ { 0, 0, 0, 0 }, /* unused */
|
/* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
|
/* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
|
|
|
/* 2 */ { 2047, -2048, 0, 3 }, /* bsr12 */
|
/* 2 */ { 2047, -2048, 0, 3 }, /* bsr12 */
|
/* 3 */ { 0, 0, 2, 0 }, /* bsr16 */
|
/* 3 */ { 0, 0, 2, 0 }, /* bsr16 */
|
|
|
/* 4 */ { 2047, -2048, 0, 5 }, /* bra */
|
/* 4 */ { 2047, -2048, 0, 5 }, /* bra */
|
/* 5 */ { 65535, -65536, 2, 6 }, /* beq $0,$0 */
|
/* 5 */ { 65535, -65536, 2, 6 }, /* beq $0,$0 */
|
/* 6 */ { 0, 0, 2, 0 }, /* jmp24 */
|
/* 6 */ { 0, 0, 2, 0 }, /* jmp24 */
|
|
|
/* 7 */ { 65535, -65536, 0, 8 }, /* beqi */
|
/* 7 */ { 65535, -65536, 0, 8 }, /* beqi */
|
/* 8 */ { 0, 0, 4, 0 }, /* bnei/jmp */
|
/* 8 */ { 0, 0, 4, 0 }, /* bnei/jmp */
|
|
|
/* 9 */ { 127, -128, 0, 10 }, /* beqz */
|
/* 9 */ { 127, -128, 0, 10 }, /* beqz */
|
/* 10 */ { 65535, -65536, 2, 11 }, /* beqi */
|
/* 10 */ { 65535, -65536, 2, 11 }, /* beqi */
|
/* 11 */ { 0, 0, 4, 0 }, /* bnei/jmp */
|
/* 11 */ { 0, 0, 4, 0 }, /* bnei/jmp */
|
|
|
/* 12 */ { 65535, -65536, 0, 13 }, /* bnei */
|
/* 12 */ { 65535, -65536, 0, 13 }, /* bnei */
|
/* 13 */ { 0, 0, 4, 0 }, /* beqi/jmp */
|
/* 13 */ { 0, 0, 4, 0 }, /* beqi/jmp */
|
|
|
/* 14 */ { 127, -128, 0, 15 }, /* bnez */
|
/* 14 */ { 127, -128, 0, 15 }, /* bnez */
|
/* 15 */ { 65535, -65536, 2, 16 }, /* bnei */
|
/* 15 */ { 65535, -65536, 2, 16 }, /* bnei */
|
/* 16 */ { 0, 0, 4, 0 }, /* beqi/jmp */
|
/* 16 */ { 0, 0, 4, 0 }, /* beqi/jmp */
|
|
|
/* 17 */ { 65535, -65536, 0, 13 }, /* bgei */
|
/* 17 */ { 65535, -65536, 0, 13 }, /* bgei */
|
/* 18 */ { 0, 0, 4, 0 },
|
/* 18 */ { 0, 0, 4, 0 },
|
/* 19 */ { 65535, -65536, 0, 13 }, /* blti */
|
/* 19 */ { 65535, -65536, 0, 13 }, /* blti */
|
/* 20 */ { 0, 0, 4, 0 },
|
/* 20 */ { 0, 0, 4, 0 },
|
/* 19 */ { 65535, -65536, 0, 13 }, /* bcpeq */
|
/* 19 */ { 65535, -65536, 0, 13 }, /* bcpeq */
|
/* 20 */ { 0, 0, 4, 0 },
|
/* 20 */ { 0, 0, 4, 0 },
|
/* 19 */ { 65535, -65536, 0, 13 }, /* bcpne */
|
/* 19 */ { 65535, -65536, 0, 13 }, /* bcpne */
|
/* 20 */ { 0, 0, 4, 0 },
|
/* 20 */ { 0, 0, 4, 0 },
|
/* 19 */ { 65535, -65536, 0, 13 }, /* bcpat */
|
/* 19 */ { 65535, -65536, 0, 13 }, /* bcpat */
|
/* 20 */ { 0, 0, 4, 0 },
|
/* 20 */ { 0, 0, 4, 0 },
|
/* 19 */ { 65535, -65536, 0, 13 }, /* bcpaf */
|
/* 19 */ { 65535, -65536, 0, 13 }, /* bcpaf */
|
/* 20 */ { 0, 0, 4, 0 }
|
/* 20 */ { 0, 0, 4, 0 }
|
};
|
};
|
|
|
/* Pseudo-values for 64 bit "insns" which are combinations of two 32
|
/* Pseudo-values for 64 bit "insns" which are combinations of two 32
|
bit insns. */
|
bit insns. */
|
typedef enum {
|
typedef enum {
|
MEP_PSEUDO64_NONE,
|
MEP_PSEUDO64_NONE,
|
MEP_PSEUDO64_16BITCC,
|
MEP_PSEUDO64_16BITCC,
|
MEP_PSEUDO64_32BITCC,
|
MEP_PSEUDO64_32BITCC,
|
} MepPseudo64Values;
|
} MepPseudo64Values;
|
|
|
static struct {
|
static struct {
|
int insn;
|
int insn;
|
int growth;
|
int growth;
|
int insn_for_extern;
|
int insn_for_extern;
|
} subtype_mappings[] = {
|
} subtype_mappings[] = {
|
{ 0, 0, 0 },
|
{ 0, 0, 0 },
|
{ 0, 0, 0 },
|
{ 0, 0, 0 },
|
{ MEP_INSN_BSR12, 0, MEP_INSN_BSR24 },
|
{ MEP_INSN_BSR12, 0, MEP_INSN_BSR24 },
|
{ MEP_INSN_BSR24, 2, MEP_INSN_BSR24 },
|
{ MEP_INSN_BSR24, 2, MEP_INSN_BSR24 },
|
{ MEP_INSN_BRA, 0, MEP_INSN_BRA },
|
{ MEP_INSN_BRA, 0, MEP_INSN_BRA },
|
{ MEP_INSN_BEQ, 2, MEP_INSN_BEQ },
|
{ MEP_INSN_BEQ, 2, MEP_INSN_BEQ },
|
{ MEP_INSN_JMP, 2, MEP_INSN_JMP },
|
{ MEP_INSN_JMP, 2, MEP_INSN_JMP },
|
{ MEP_INSN_BEQI, 0, MEP_INSN_BEQI },
|
{ MEP_INSN_BEQI, 0, MEP_INSN_BEQI },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ MEP_INSN_BEQZ, 0, MEP_INSN_BEQZ },
|
{ MEP_INSN_BEQZ, 0, MEP_INSN_BEQZ },
|
{ MEP_INSN_BEQI, 2, MEP_INSN_BEQI },
|
{ MEP_INSN_BEQI, 2, MEP_INSN_BEQI },
|
{ -1, 4, MEP_PSEUDO64_16BITCC },
|
{ -1, 4, MEP_PSEUDO64_16BITCC },
|
{ MEP_INSN_BNEI, 0, MEP_INSN_BNEI },
|
{ MEP_INSN_BNEI, 0, MEP_INSN_BNEI },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ MEP_INSN_BNEZ, 0, MEP_INSN_BNEZ },
|
{ MEP_INSN_BNEZ, 0, MEP_INSN_BNEZ },
|
{ MEP_INSN_BNEI, 2, MEP_INSN_BNEI },
|
{ MEP_INSN_BNEI, 2, MEP_INSN_BNEI },
|
{ -1, 4, MEP_PSEUDO64_16BITCC },
|
{ -1, 4, MEP_PSEUDO64_16BITCC },
|
{ MEP_INSN_BGEI, 0, MEP_INSN_BGEI },
|
{ MEP_INSN_BGEI, 0, MEP_INSN_BGEI },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ MEP_INSN_BLTI, 0, MEP_INSN_BLTI },
|
{ MEP_INSN_BLTI, 0, MEP_INSN_BLTI },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ MEP_INSN_BCPEQ, 0, MEP_INSN_BCPEQ },
|
{ MEP_INSN_BCPEQ, 0, MEP_INSN_BCPEQ },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ MEP_INSN_BCPNE, 0, MEP_INSN_BCPNE },
|
{ MEP_INSN_BCPNE, 0, MEP_INSN_BCPNE },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ MEP_INSN_BCPAT, 0, MEP_INSN_BCPAT },
|
{ MEP_INSN_BCPAT, 0, MEP_INSN_BCPAT },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ -1, 4, MEP_PSEUDO64_32BITCC },
|
{ MEP_INSN_BCPAF, 0, MEP_INSN_BCPAF },
|
{ MEP_INSN_BCPAF, 0, MEP_INSN_BCPAF },
|
{ -1, 4, MEP_PSEUDO64_32BITCC }
|
{ -1, 4, MEP_PSEUDO64_32BITCC }
|
};
|
};
|
#define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
|
#define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
|
|
|
void
|
void
|
mep_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
|
mep_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
|
{
|
{
|
symbolS *symbolP = fragP->fr_symbol;
|
symbolS *symbolP = fragP->fr_symbol;
|
if (symbolP && !S_IS_DEFINED (symbolP))
|
if (symbolP && !S_IS_DEFINED (symbolP))
|
*aim = 0;
|
*aim = 0;
|
/* Adjust for MeP pcrel not being relative to the next opcode. */
|
/* Adjust for MeP pcrel not being relative to the next opcode. */
|
*aim += 2 + md_relax_table[this_state].rlx_length;
|
*aim += 2 + md_relax_table[this_state].rlx_length;
|
}
|
}
|
|
|
static int
|
static int
|
insn_to_subtype (int insn)
|
insn_to_subtype (int insn)
|
{
|
{
|
unsigned int i;
|
unsigned int i;
|
for (i=0; i<NUM_MAPPINGS; i++)
|
for (i=0; i<NUM_MAPPINGS; i++)
|
if (insn == subtype_mappings[i].insn)
|
if (insn == subtype_mappings[i].insn)
|
return i;
|
return i;
|
abort ();
|
abort ();
|
}
|
}
|
|
|
/* Return an initial guess of the length by which a fragment must grow
|
/* Return an initial guess of the length by which a fragment must grow
|
to hold a branch to reach its destination. Also updates fr_type
|
to hold a branch to reach its destination. Also updates fr_type
|
and fr_subtype as necessary.
|
and fr_subtype as necessary.
|
|
|
Called just before doing relaxation. Any symbol that is now
|
Called just before doing relaxation. Any symbol that is now
|
undefined will not become defined. The guess for fr_var is
|
undefined will not become defined. The guess for fr_var is
|
ACTUALLY the growth beyond fr_fix. Whatever we do to grow fr_fix
|
ACTUALLY the growth beyond fr_fix. Whatever we do to grow fr_fix
|
or fr_var contributes to our returned value. Although it may not
|
or fr_var contributes to our returned value. Although it may not
|
be explicit in the frag, pretend fr_var starts with a 0 value. */
|
be explicit in the frag, pretend fr_var starts with a 0 value. */
|
|
|
int
|
int
|
md_estimate_size_before_relax (fragS * fragP, segT segment)
|
md_estimate_size_before_relax (fragS * fragP, segT segment)
|
{
|
{
|
if (fragP->fr_subtype == 1)
|
if (fragP->fr_subtype == 1)
|
fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
|
fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
|
|
|
if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
|
if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
|
{
|
{
|
int new_insn;
|
int new_insn;
|
|
|
new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
|
new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
|
fragP->fr_subtype = insn_to_subtype (new_insn);
|
fragP->fr_subtype = insn_to_subtype (new_insn);
|
}
|
}
|
|
|
if (MEP_VLIW && ! MEP_VLIW64
|
if (MEP_VLIW && ! MEP_VLIW64
|
&& (bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW))
|
&& (bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW))
|
{
|
{
|
/* Use 32 bit branches for vliw32 so the vliw word is not split. */
|
/* Use 32 bit branches for vliw32 so the vliw word is not split. */
|
switch (fragP->fr_cgen.insn->base->num)
|
switch (fragP->fr_cgen.insn->base->num)
|
{
|
{
|
case MEP_INSN_BSR12:
|
case MEP_INSN_BSR12:
|
fragP->fr_subtype = insn_to_subtype
|
fragP->fr_subtype = insn_to_subtype
|
(subtype_mappings[fragP->fr_subtype].insn_for_extern);
|
(subtype_mappings[fragP->fr_subtype].insn_for_extern);
|
break;
|
break;
|
case MEP_INSN_BEQZ:
|
case MEP_INSN_BEQZ:
|
fragP->fr_subtype ++;
|
fragP->fr_subtype ++;
|
break;
|
break;
|
case MEP_INSN_BNEZ:
|
case MEP_INSN_BNEZ:
|
fragP->fr_subtype ++;
|
fragP->fr_subtype ++;
|
break;
|
break;
|
}
|
}
|
}
|
}
|
|
|
if (fragP->fr_cgen.insn->base
|
if (fragP->fr_cgen.insn->base
|
&& fragP->fr_cgen.insn->base->num
|
&& fragP->fr_cgen.insn->base->num
|
!= subtype_mappings[fragP->fr_subtype].insn)
|
!= subtype_mappings[fragP->fr_subtype].insn)
|
{
|
{
|
int new_insn= subtype_mappings[fragP->fr_subtype].insn;
|
int new_insn= subtype_mappings[fragP->fr_subtype].insn;
|
if (new_insn != -1)
|
if (new_insn != -1)
|
{
|
{
|
fragP->fr_cgen.insn = (fragP->fr_cgen.insn
|
fragP->fr_cgen.insn = (fragP->fr_cgen.insn
|
- fragP->fr_cgen.insn->base->num
|
- fragP->fr_cgen.insn->base->num
|
+ new_insn);
|
+ new_insn);
|
}
|
}
|
}
|
}
|
|
|
return subtype_mappings[fragP->fr_subtype].growth;
|
return subtype_mappings[fragP->fr_subtype].growth;
|
}
|
}
|
|
|
/* *fragP has been relaxed to its final size, and now needs to have
|
/* *fragP has been relaxed to its final size, and now needs to have
|
the bytes inside it modified to conform to the new size.
|
the bytes inside it modified to conform to the new size.
|
|
|
Called after relaxation is finished.
|
Called after relaxation is finished.
|
fragP->fr_type == rs_machine_dependent.
|
fragP->fr_type == rs_machine_dependent.
|
fragP->fr_subtype is the subtype of what the address relaxed to. */
|
fragP->fr_subtype is the subtype of what the address relaxed to. */
|
|
|
static int
|
static int
|
target_address_for (fragS *frag)
|
target_address_for (fragS *frag)
|
{
|
{
|
int rv = frag->fr_offset;
|
int rv = frag->fr_offset;
|
symbolS *sym = frag->fr_symbol;
|
symbolS *sym = frag->fr_symbol;
|
|
|
if (sym)
|
if (sym)
|
rv += S_GET_VALUE (sym);
|
rv += S_GET_VALUE (sym);
|
|
|
return rv;
|
return rv;
|
}
|
}
|
|
|
void
|
void
|
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
|
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
|
segT sec ATTRIBUTE_UNUSED,
|
segT sec ATTRIBUTE_UNUSED,
|
fragS *fragP)
|
fragS *fragP)
|
{
|
{
|
int addend, rn, bit = 0;
|
int addend, rn, bit = 0;
|
int operand;
|
int operand;
|
int where = fragP->fr_opcode - fragP->fr_literal;
|
int where = fragP->fr_opcode - fragP->fr_literal;
|
int e = target_big_endian ? 0 : 1;
|
int e = target_big_endian ? 0 : 1;
|
|
|
addend = target_address_for (fragP) - (fragP->fr_address + where);
|
addend = target_address_for (fragP) - (fragP->fr_address + where);
|
|
|
if (subtype_mappings[fragP->fr_subtype].insn == -1)
|
if (subtype_mappings[fragP->fr_subtype].insn == -1)
|
{
|
{
|
fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
|
fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
|
switch (subtype_mappings[fragP->fr_subtype].insn_for_extern)
|
switch (subtype_mappings[fragP->fr_subtype].insn_for_extern)
|
{
|
{
|
case MEP_PSEUDO64_16BITCC:
|
case MEP_PSEUDO64_16BITCC:
|
fragP->fr_opcode[1^e] = ((fragP->fr_opcode[1^e] & 1) ^ 1) | 0x06;
|
fragP->fr_opcode[1^e] = ((fragP->fr_opcode[1^e] & 1) ^ 1) | 0x06;
|
fragP->fr_opcode[2^e] = 0xd8;
|
fragP->fr_opcode[2^e] = 0xd8;
|
fragP->fr_opcode[3^e] = 0x08;
|
fragP->fr_opcode[3^e] = 0x08;
|
fragP->fr_opcode[4^e] = 0;
|
fragP->fr_opcode[4^e] = 0;
|
fragP->fr_opcode[5^e] = 0;
|
fragP->fr_opcode[5^e] = 0;
|
where += 2;
|
where += 2;
|
break;
|
break;
|
case MEP_PSEUDO64_32BITCC:
|
case MEP_PSEUDO64_32BITCC:
|
if (fragP->fr_opcode[0^e] & 0x10)
|
if (fragP->fr_opcode[0^e] & 0x10)
|
fragP->fr_opcode[1^e] ^= 0x01;
|
fragP->fr_opcode[1^e] ^= 0x01;
|
else
|
else
|
fragP->fr_opcode[1^e] ^= 0x04;
|
fragP->fr_opcode[1^e] ^= 0x04;
|
fragP->fr_opcode[2^e] = 0;
|
fragP->fr_opcode[2^e] = 0;
|
fragP->fr_opcode[3^e] = 4;
|
fragP->fr_opcode[3^e] = 4;
|
fragP->fr_opcode[4^e] = 0xd8;
|
fragP->fr_opcode[4^e] = 0xd8;
|
fragP->fr_opcode[5^e] = 0x08;
|
fragP->fr_opcode[5^e] = 0x08;
|
fragP->fr_opcode[6^e] = 0;
|
fragP->fr_opcode[6^e] = 0;
|
fragP->fr_opcode[7^e] = 0;
|
fragP->fr_opcode[7^e] = 0;
|
where += 4;
|
where += 4;
|
break;
|
break;
|
default:
|
default:
|
abort ();
|
abort ();
|
}
|
}
|
fragP->fr_cgen.insn = (fragP->fr_cgen.insn
|
fragP->fr_cgen.insn = (fragP->fr_cgen.insn
|
- fragP->fr_cgen.insn->base->num
|
- fragP->fr_cgen.insn->base->num
|
+ MEP_INSN_JMP);
|
+ MEP_INSN_JMP);
|
operand = MEP_OPERAND_PCABS24A2;
|
operand = MEP_OPERAND_PCABS24A2;
|
}
|
}
|
else
|
else
|
switch (fragP->fr_cgen.insn->base->num)
|
switch (fragP->fr_cgen.insn->base->num)
|
{
|
{
|
case MEP_INSN_BSR12:
|
case MEP_INSN_BSR12:
|
fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
|
fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
|
fragP->fr_opcode[1^e] = 0x01 | (addend & 0xfe);
|
fragP->fr_opcode[1^e] = 0x01 | (addend & 0xfe);
|
operand = MEP_OPERAND_PCREL12A2;
|
operand = MEP_OPERAND_PCREL12A2;
|
break;
|
break;
|
|
|
case MEP_INSN_BSR24:
|
case MEP_INSN_BSR24:
|
fragP->fr_fix += 2;
|
fragP->fr_fix += 2;
|
fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
|
fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
|
fragP->fr_opcode[1^e] = 0x09 | ((addend << 3) & 0xf0);
|
fragP->fr_opcode[1^e] = 0x09 | ((addend << 3) & 0xf0);
|
fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
|
fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
|
fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
|
fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
|
operand = MEP_OPERAND_PCREL24A2;
|
operand = MEP_OPERAND_PCREL24A2;
|
break;
|
break;
|
|
|
case MEP_INSN_BRA:
|
case MEP_INSN_BRA:
|
fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
|
fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
|
fragP->fr_opcode[1^e] = 0x00 | (addend & 0xfe);
|
fragP->fr_opcode[1^e] = 0x00 | (addend & 0xfe);
|
operand = MEP_OPERAND_PCREL12A2;
|
operand = MEP_OPERAND_PCREL12A2;
|
break;
|
break;
|
|
|
case MEP_INSN_BEQ:
|
case MEP_INSN_BEQ:
|
/* The default relax_frag doesn't change the state if there is no
|
/* The default relax_frag doesn't change the state if there is no
|
growth, so we must manually handle converting out-of-range BEQ
|
growth, so we must manually handle converting out-of-range BEQ
|
instructions to JMP. */
|
instructions to JMP. */
|
if (addend <= 65535 && addend >= -65536)
|
if (addend <= 65535 && addend >= -65536)
|
{
|
{
|
fragP->fr_fix += 2;
|
fragP->fr_fix += 2;
|
fragP->fr_opcode[0^e] = 0xe0;
|
fragP->fr_opcode[0^e] = 0xe0;
|
fragP->fr_opcode[1^e] = 0x01;
|
fragP->fr_opcode[1^e] = 0x01;
|
fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
|
fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
|
fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
|
fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
|
operand = MEP_OPERAND_PCREL17A2;
|
operand = MEP_OPERAND_PCREL17A2;
|
break;
|
break;
|
}
|
}
|
/* ...FALLTHROUGH... */
|
/* ...FALLTHROUGH... */
|
|
|
case MEP_INSN_JMP:
|
case MEP_INSN_JMP:
|
addend = target_address_for (fragP);
|
addend = target_address_for (fragP);
|
fragP->fr_fix += 2;
|
fragP->fr_fix += 2;
|
fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
|
fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
|
fragP->fr_opcode[1^e] = 0x08 | ((addend << 3) & 0xf0);
|
fragP->fr_opcode[1^e] = 0x08 | ((addend << 3) & 0xf0);
|
fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
|
fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
|
fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
|
fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
|
operand = MEP_OPERAND_PCABS24A2;
|
operand = MEP_OPERAND_PCABS24A2;
|
break;
|
break;
|
|
|
case MEP_INSN_BNEZ:
|
case MEP_INSN_BNEZ:
|
bit = 1;
|
bit = 1;
|
case MEP_INSN_BEQZ:
|
case MEP_INSN_BEQZ:
|
fragP->fr_opcode[1^e] = bit | (addend & 0xfe);
|
fragP->fr_opcode[1^e] = bit | (addend & 0xfe);
|
operand = MEP_OPERAND_PCREL8A2;
|
operand = MEP_OPERAND_PCREL8A2;
|
break;
|
break;
|
|
|
case MEP_INSN_BNEI:
|
case MEP_INSN_BNEI:
|
bit = 4;
|
bit = 4;
|
case MEP_INSN_BEQI:
|
case MEP_INSN_BEQI:
|
if (subtype_mappings[fragP->fr_subtype].growth)
|
if (subtype_mappings[fragP->fr_subtype].growth)
|
{
|
{
|
fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
|
fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
|
rn = fragP->fr_opcode[0^e] & 0x0f;
|
rn = fragP->fr_opcode[0^e] & 0x0f;
|
fragP->fr_opcode[0^e] = 0xe0 | rn;
|
fragP->fr_opcode[0^e] = 0xe0 | rn;
|
fragP->fr_opcode[1^e] = bit;
|
fragP->fr_opcode[1^e] = bit;
|
}
|
}
|
fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
|
fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
|
fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
|
fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
|
operand = MEP_OPERAND_PCREL17A2;
|
operand = MEP_OPERAND_PCREL17A2;
|
break;
|
break;
|
|
|
case MEP_INSN_BLTI:
|
case MEP_INSN_BLTI:
|
case MEP_INSN_BGEI:
|
case MEP_INSN_BGEI:
|
case MEP_INSN_BCPEQ:
|
case MEP_INSN_BCPEQ:
|
case MEP_INSN_BCPNE:
|
case MEP_INSN_BCPNE:
|
case MEP_INSN_BCPAT:
|
case MEP_INSN_BCPAT:
|
case MEP_INSN_BCPAF:
|
case MEP_INSN_BCPAF:
|
/* No opcode change needed, just operand. */
|
/* No opcode change needed, just operand. */
|
fragP->fr_opcode[2^e] = (addend >> 9) & 0xff;
|
fragP->fr_opcode[2^e] = (addend >> 9) & 0xff;
|
fragP->fr_opcode[3^e] = (addend >> 1) & 0xff;
|
fragP->fr_opcode[3^e] = (addend >> 1) & 0xff;
|
operand = MEP_OPERAND_PCREL17A2;
|
operand = MEP_OPERAND_PCREL17A2;
|
break;
|
break;
|
|
|
default:
|
default:
|
abort ();
|
abort ();
|
}
|
}
|
|
|
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|
|| operand == MEP_OPERAND_PCABS24A2)
|
|| operand == MEP_OPERAND_PCABS24A2)
|
{
|
{
|
assert (fragP->fr_cgen.insn != 0);
|
assert (fragP->fr_cgen.insn != 0);
|
gas_cgen_record_fixup (fragP,
|
gas_cgen_record_fixup (fragP,
|
where,
|
where,
|
fragP->fr_cgen.insn,
|
fragP->fr_cgen.insn,
|
(fragP->fr_fix - where) * 8,
|
(fragP->fr_fix - where) * 8,
|
cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
|
cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
|
operand),
|
operand),
|
fragP->fr_cgen.opinfo,
|
fragP->fr_cgen.opinfo,
|
fragP->fr_symbol, fragP->fr_offset);
|
fragP->fr_symbol, fragP->fr_offset);
|
}
|
}
|
}
|
}
|
|
|
|
|
/* Functions concerning relocs. */
|
/* Functions concerning relocs. */
|
|
|
void
|
void
|
mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
|
mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
|
{
|
{
|
/* If we already know the fixup value, adjust it in the same
|
/* If we already know the fixup value, adjust it in the same
|
way that the linker would have done. */
|
way that the linker would have done. */
|
if (fixP->fx_addsy == 0)
|
if (fixP->fx_addsy == 0)
|
switch (fixP->fx_cgen.opinfo)
|
switch (fixP->fx_cgen.opinfo)
|
{
|
{
|
case BFD_RELOC_MEP_LOW16:
|
case BFD_RELOC_MEP_LOW16:
|
*valP = ((long)(*valP & 0xffff)) << 16 >> 16;
|
*valP = ((long)(*valP & 0xffff)) << 16 >> 16;
|
break;
|
break;
|
case BFD_RELOC_MEP_HI16U:
|
case BFD_RELOC_MEP_HI16U:
|
*valP >>= 16;
|
*valP >>= 16;
|
break;
|
break;
|
case BFD_RELOC_MEP_HI16S:
|
case BFD_RELOC_MEP_HI16S:
|
*valP = (*valP + 0x8000) >> 16;
|
*valP = (*valP + 0x8000) >> 16;
|
break;
|
break;
|
}
|
}
|
|
|
/* Now call cgen's md_aply_fix. */
|
/* Now call cgen's md_aply_fix. */
|
gas_cgen_md_apply_fix (fixP, valP, seg);
|
gas_cgen_md_apply_fix (fixP, valP, seg);
|
}
|
}
|
|
|
long
|
long
|
md_pcrel_from_section (fixS *fixP, segT sec)
|
md_pcrel_from_section (fixS *fixP, segT sec)
|
{
|
{
|
if (fixP->fx_addsy != (symbolS *) NULL
|
if (fixP->fx_addsy != (symbolS *) NULL
|
&& (! S_IS_DEFINED (fixP->fx_addsy)
|
&& (! S_IS_DEFINED (fixP->fx_addsy)
|
|| S_GET_SEGMENT (fixP->fx_addsy) != sec))
|
|| S_GET_SEGMENT (fixP->fx_addsy) != sec))
|
/* The symbol is undefined (or is defined but not in this section).
|
/* The symbol is undefined (or is defined but not in this section).
|
Let the linker figure it out. */
|
Let the linker figure it out. */
|
return 0;
|
return 0;
|
|
|
/* Return the address of the opcode - cgen adjusts for opcode size
|
/* Return the address of the opcode - cgen adjusts for opcode size
|
itself, to be consistent with the disassembler, which must do
|
itself, to be consistent with the disassembler, which must do
|
so. */
|
so. */
|
return fixP->fx_where + fixP->fx_frag->fr_address;
|
return fixP->fx_where + fixP->fx_frag->fr_address;
|
}
|
}
|
|
|
/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
|
/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
|
Returns BFD_RELOC_NONE if no reloc type can be found.
|
Returns BFD_RELOC_NONE if no reloc type can be found.
|
*FIXP may be modified if desired. */
|
*FIXP may be modified if desired. */
|
|
|
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
|
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
|
#define MAP(n) case MEP_OPERAND_##n: return BFD_RELOC_MEP_##n;
|
#define MAP(n) case MEP_OPERAND_##n: return BFD_RELOC_MEP_##n;
|
#else
|
#else
|
#define MAP(n) case MEP_OPERAND_/**/n: return BFD_RELOC_MEP_/**/n;
|
#define MAP(n) case MEP_OPERAND_/**/n: return BFD_RELOC_MEP_/**/n;
|
#endif
|
#endif
|
|
|
bfd_reloc_code_real_type
|
bfd_reloc_code_real_type
|
md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
|
md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
|
const CGEN_OPERAND *operand,
|
const CGEN_OPERAND *operand,
|
fixS *fixP)
|
fixS *fixP)
|
{
|
{
|
enum bfd_reloc_code_real reloc = fixP->fx_cgen.opinfo;
|
enum bfd_reloc_code_real reloc = fixP->fx_cgen.opinfo;
|
static char printed[MEP_OPERAND_MAX] = { 0 };
|
static char printed[MEP_OPERAND_MAX] = { 0 };
|
|
|
/* If there's a reloc here, it's because the parser saw a %foo() and
|
/* If there's a reloc here, it's because the parser saw a %foo() and
|
is giving us the correct reloc to use, or because we converted to
|
is giving us the correct reloc to use, or because we converted to
|
a different size reloc below and want to avoid "converting" more
|
a different size reloc below and want to avoid "converting" more
|
than once. */
|
than once. */
|
if (reloc && reloc != BFD_RELOC_NONE)
|
if (reloc && reloc != BFD_RELOC_NONE)
|
return reloc;
|
return reloc;
|
|
|
switch (operand->type)
|
switch (operand->type)
|
{
|
{
|
MAP (PCREL8A2); /* beqz */
|
MAP (PCREL8A2); /* beqz */
|
MAP (PCREL12A2); /* bsr16 */
|
MAP (PCREL12A2); /* bsr16 */
|
MAP (PCREL17A2); /* beqi */
|
MAP (PCREL17A2); /* beqi */
|
MAP (PCREL24A2); /* bsr24 */
|
MAP (PCREL24A2); /* bsr24 */
|
MAP (PCABS24A2); /* jmp */
|
MAP (PCABS24A2); /* jmp */
|
MAP (UIMM24); /* mov */
|
MAP (UIMM24); /* mov */
|
MAP (ADDR24A4); /* sw/lw */
|
MAP (ADDR24A4); /* sw/lw */
|
|
|
/* The rest of the relocs should be generated by the parser,
|
/* The rest of the relocs should be generated by the parser,
|
for things such as %tprel(), etc. */
|
for things such as %tprel(), etc. */
|
case MEP_OPERAND_SIMM16:
|
case MEP_OPERAND_SIMM16:
|
#ifdef OBJ_COMPLEX_RELC
|
#ifdef OBJ_COMPLEX_RELC
|
/* coalescing this into RELOC_MEP_16 is actually a bug,
|
/* coalescing this into RELOC_MEP_16 is actually a bug,
|
since it's a signed operand. let the relc code handle it. */
|
since it's a signed operand. let the relc code handle it. */
|
return BFD_RELOC_RELC;
|
return BFD_RELOC_RELC;
|
#endif
|
#endif
|
|
|
case MEP_OPERAND_UIMM16:
|
case MEP_OPERAND_UIMM16:
|
case MEP_OPERAND_SDISP16:
|
case MEP_OPERAND_SDISP16:
|
case MEP_OPERAND_CODE16:
|
case MEP_OPERAND_CODE16:
|
fixP->fx_where += 2;
|
fixP->fx_where += 2;
|
/* to avoid doing the above add twice */
|
/* to avoid doing the above add twice */
|
fixP->fx_cgen.opinfo = BFD_RELOC_MEP_16;
|
fixP->fx_cgen.opinfo = BFD_RELOC_MEP_16;
|
return BFD_RELOC_MEP_16;
|
return BFD_RELOC_MEP_16;
|
|
|
default:
|
default:
|
#ifdef OBJ_COMPLEX_RELC
|
#ifdef OBJ_COMPLEX_RELC
|
/* this is not an error, yet.
|
/* this is not an error, yet.
|
pass it to the linker. */
|
pass it to the linker. */
|
return BFD_RELOC_RELC;
|
return BFD_RELOC_RELC;
|
#endif
|
#endif
|
if (printed[operand->type])
|
if (printed[operand->type])
|
return BFD_RELOC_NONE;
|
return BFD_RELOC_NONE;
|
printed[operand->type] = 1;
|
printed[operand->type] = 1;
|
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
_("Don't know how to relocate plain operands of type %s"),
|
_("Don't know how to relocate plain operands of type %s"),
|
operand->name);
|
operand->name);
|
|
|
/* Print some helpful hints for the user. */
|
/* Print some helpful hints for the user. */
|
switch (operand->type)
|
switch (operand->type)
|
{
|
{
|
case MEP_OPERAND_UDISP7:
|
case MEP_OPERAND_UDISP7:
|
case MEP_OPERAND_UDISP7A2:
|
case MEP_OPERAND_UDISP7A2:
|
case MEP_OPERAND_UDISP7A4:
|
case MEP_OPERAND_UDISP7A4:
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
_("Perhaps you are missing %%tpoff()?"));
|
_("Perhaps you are missing %%tpoff()?"));
|
break;
|
break;
|
default:
|
default:
|
break;
|
break;
|
}
|
}
|
return BFD_RELOC_NONE;
|
return BFD_RELOC_NONE;
|
}
|
}
|
}
|
}
|
|
|
/* Called while parsing an instruction to create a fixup.
|
/* Called while parsing an instruction to create a fixup.
|
We need to check for HI16 relocs and queue them up for later sorting. */
|
We need to check for HI16 relocs and queue them up for later sorting. */
|
|
|
fixS *
|
fixS *
|
mep_cgen_record_fixup_exp (fragS *frag,
|
mep_cgen_record_fixup_exp (fragS *frag,
|
int where,
|
int where,
|
const CGEN_INSN *insn,
|
const CGEN_INSN *insn,
|
int length,
|
int length,
|
const CGEN_OPERAND *operand,
|
const CGEN_OPERAND *operand,
|
int opinfo,
|
int opinfo,
|
expressionS *exp)
|
expressionS *exp)
|
{
|
{
|
fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
|
fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
|
operand, opinfo, exp);
|
operand, opinfo, exp);
|
return fixP;
|
return fixP;
|
}
|
}
|
|
|
/* Return BFD reloc type from opinfo field in a fixS.
|
/* Return BFD reloc type from opinfo field in a fixS.
|
It's tricky using fx_r_type in mep_frob_file because the values
|
It's tricky using fx_r_type in mep_frob_file because the values
|
are BFD_RELOC_UNUSED + operand number. */
|
are BFD_RELOC_UNUSED + operand number. */
|
#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
|
#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
|
|
|
/* Sort any unmatched HI16 relocs so that they immediately precede
|
/* Sort any unmatched HI16 relocs so that they immediately precede
|
the corresponding LO16 reloc. This is called before md_apply_fix and
|
the corresponding LO16 reloc. This is called before md_apply_fix and
|
tc_gen_reloc. */
|
tc_gen_reloc. */
|
|
|
void
|
void
|
mep_frob_file ()
|
mep_frob_file ()
|
{
|
{
|
struct mep_hi_fixup * l;
|
struct mep_hi_fixup * l;
|
|
|
for (l = mep_hi_fixup_list; l != NULL; l = l->next)
|
for (l = mep_hi_fixup_list; l != NULL; l = l->next)
|
{
|
{
|
segment_info_type * seginfo;
|
segment_info_type * seginfo;
|
int pass;
|
int pass;
|
|
|
assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_HI16
|
assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_HI16
|
|| FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_LO16);
|
|| FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_LO16);
|
|
|
/* Check quickly whether the next fixup happens to be a matching low. */
|
/* Check quickly whether the next fixup happens to be a matching low. */
|
if (l->fixp->fx_next != NULL
|
if (l->fixp->fx_next != NULL
|
&& FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_LO16
|
&& FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_LO16
|
&& l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
|
&& l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
|
&& l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
|
&& l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
|
continue;
|
continue;
|
|
|
/* Look through the fixups for this segment for a matching
|
/* Look through the fixups for this segment for a matching
|
`low'. When we find one, move the high just in front of it.
|
`low'. When we find one, move the high just in front of it.
|
We do this in two passes. In the first pass, we try to find
|
We do this in two passes. In the first pass, we try to find
|
a unique `low'. In the second pass, we permit multiple
|
a unique `low'. In the second pass, we permit multiple
|
high's relocs for a single `low'. */
|
high's relocs for a single `low'. */
|
seginfo = seg_info (l->seg);
|
seginfo = seg_info (l->seg);
|
for (pass = 0; pass < 2; pass++)
|
for (pass = 0; pass < 2; pass++)
|
{
|
{
|
fixS * f;
|
fixS * f;
|
fixS * prev;
|
fixS * prev;
|
|
|
prev = NULL;
|
prev = NULL;
|
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
{
|
{
|
/* Check whether this is a `low' fixup which matches l->fixp. */
|
/* Check whether this is a `low' fixup which matches l->fixp. */
|
if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_LO16
|
if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_LO16
|
&& f->fx_addsy == l->fixp->fx_addsy
|
&& f->fx_addsy == l->fixp->fx_addsy
|
&& f->fx_offset == l->fixp->fx_offset
|
&& f->fx_offset == l->fixp->fx_offset
|
&& (pass == 1
|
&& (pass == 1
|
|| prev == NULL
|
|| prev == NULL
|
|| (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_HI16)
|
|| (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_HI16)
|
|| prev->fx_addsy != f->fx_addsy
|
|| prev->fx_addsy != f->fx_addsy
|
|| prev->fx_offset != f->fx_offset))
|
|| prev->fx_offset != f->fx_offset))
|
{
|
{
|
fixS ** pf;
|
fixS ** pf;
|
|
|
/* Move l->fixp before f. */
|
/* Move l->fixp before f. */
|
for (pf = &seginfo->fix_root;
|
for (pf = &seginfo->fix_root;
|
* pf != l->fixp;
|
* pf != l->fixp;
|
pf = & (* pf)->fx_next)
|
pf = & (* pf)->fx_next)
|
assert (* pf != NULL);
|
assert (* pf != NULL);
|
|
|
* pf = l->fixp->fx_next;
|
* pf = l->fixp->fx_next;
|
|
|
l->fixp->fx_next = f;
|
l->fixp->fx_next = f;
|
if (prev == NULL)
|
if (prev == NULL)
|
seginfo->fix_root = l->fixp;
|
seginfo->fix_root = l->fixp;
|
else
|
else
|
prev->fx_next = l->fixp;
|
prev->fx_next = l->fixp;
|
|
|
break;
|
break;
|
}
|
}
|
|
|
prev = f;
|
prev = f;
|
}
|
}
|
|
|
if (f != NULL)
|
if (f != NULL)
|
break;
|
break;
|
|
|
if (pass == 1)
|
if (pass == 1)
|
as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
|
as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
|
_("Unmatched high relocation"));
|
_("Unmatched high relocation"));
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* See whether we need to force a relocation into the output file. */
|
/* See whether we need to force a relocation into the output file. */
|
|
|
int
|
int
|
mep_force_relocation (fixS *fixp)
|
mep_force_relocation (fixS *fixp)
|
{
|
{
|
if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
|
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
|
return 1;
|
return 1;
|
|
|
/* Allow branches to global symbols to be resolved at assembly time.
|
/* Allow branches to global symbols to be resolved at assembly time.
|
This is consistent with way relaxable branches are handled, since
|
This is consistent with way relaxable branches are handled, since
|
branches to both global and local symbols are relaxed. It also
|
branches to both global and local symbols are relaxed. It also
|
corresponds to the assumptions made in md_pcrel_from_section. */
|
corresponds to the assumptions made in md_pcrel_from_section. */
|
return S_FORCE_RELOC (fixp->fx_addsy, !fixp->fx_pcrel);
|
return S_FORCE_RELOC (fixp->fx_addsy, !fixp->fx_pcrel);
|
}
|
}
|
|
|
/* Write a value out to the object file, using the appropriate endianness. */
|
/* Write a value out to the object file, using the appropriate endianness. */
|
|
|
void
|
void
|
md_number_to_chars (char *buf, valueT val, int n)
|
md_number_to_chars (char *buf, valueT val, int n)
|
{
|
{
|
if (target_big_endian)
|
if (target_big_endian)
|
number_to_chars_bigendian (buf, val, n);
|
number_to_chars_bigendian (buf, val, n);
|
else
|
else
|
number_to_chars_littleendian (buf, val, n);
|
number_to_chars_littleendian (buf, val, n);
|
}
|
}
|
|
|
char *
|
char *
|
md_atof (int type, char *litP, int *sizeP)
|
md_atof (int type, char *litP, int *sizeP)
|
{
|
{
|
return ieee_md_atof (type, litP, sizeP, TRUE);
|
return ieee_md_atof (type, litP, sizeP, TRUE);
|
}
|
}
|
|
|
bfd_boolean
|
bfd_boolean
|
mep_fix_adjustable (fixS *fixP)
|
mep_fix_adjustable (fixS *fixP)
|
{
|
{
|
bfd_reloc_code_real_type reloc_type;
|
bfd_reloc_code_real_type reloc_type;
|
|
|
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
|
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
|
{
|
{
|
const CGEN_INSN *insn = NULL;
|
const CGEN_INSN *insn = NULL;
|
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
|
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
|
const CGEN_OPERAND *operand
|
const CGEN_OPERAND *operand
|
= cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
|
= cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
|
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
|
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
|
}
|
}
|
else
|
else
|
reloc_type = fixP->fx_r_type;
|
reloc_type = fixP->fx_r_type;
|
|
|
if (fixP->fx_addsy == NULL)
|
if (fixP->fx_addsy == NULL)
|
return 1;
|
return 1;
|
|
|
/* Prevent all adjustments to global symbols. */
|
/* Prevent all adjustments to global symbols. */
|
if (S_IS_EXTERNAL (fixP->fx_addsy))
|
if (S_IS_EXTERNAL (fixP->fx_addsy))
|
return 0;
|
return 0;
|
|
|
if (S_IS_WEAK (fixP->fx_addsy))
|
if (S_IS_WEAK (fixP->fx_addsy))
|
return 0;
|
return 0;
|
|
|
/* We need the symbol name for the VTABLE entries */
|
/* We need the symbol name for the VTABLE entries */
|
if (reloc_type == BFD_RELOC_VTABLE_INHERIT
|
if (reloc_type == BFD_RELOC_VTABLE_INHERIT
|
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
|
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
|
return 0;
|
return 0;
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
int
|
int
|
mep_elf_section_letter (int letter, char **ptrmsg)
|
mep_elf_section_letter (int letter, char **ptrmsg)
|
{
|
{
|
if (letter == 'v')
|
if (letter == 'v')
|
return SHF_MEP_VLIW;
|
return SHF_MEP_VLIW;
|
|
|
*ptrmsg = _("Bad .section directive: want a,v,w,x,M,S in string");
|
*ptrmsg = _("Bad .section directive: want a,v,w,x,M,S in string");
|
return 0;
|
return 0;
|
}
|
}
|
|
|
flagword
|
flagword
|
mep_elf_section_flags (flagword flags, int attr, int type ATTRIBUTE_UNUSED)
|
mep_elf_section_flags (flagword flags, int attr, int type ATTRIBUTE_UNUSED)
|
{
|
{
|
if (attr & SHF_MEP_VLIW)
|
if (attr & SHF_MEP_VLIW)
|
flags |= SEC_MEP_VLIW;
|
flags |= SEC_MEP_VLIW;
|
return flags;
|
return flags;
|
}
|
}
|
|
|
/* In vliw mode, the default section is .vtext. We have to be able
|
/* In vliw mode, the default section is .vtext. We have to be able
|
to switch into .vtext using only the .vtext directive. */
|
to switch into .vtext using only the .vtext directive. */
|
|
|
static segT
|
static segT
|
mep_vtext_section (void)
|
mep_vtext_section (void)
|
{
|
{
|
static segT vtext_section;
|
static segT vtext_section;
|
|
|
if (! vtext_section)
|
if (! vtext_section)
|
{
|
{
|
flagword applicable = bfd_applicable_section_flags (stdoutput);
|
flagword applicable = bfd_applicable_section_flags (stdoutput);
|
vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
|
vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
|
bfd_set_section_flags (stdoutput, vtext_section,
|
bfd_set_section_flags (stdoutput, vtext_section,
|
applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
|
applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
|
| SEC_CODE | SEC_READONLY
|
| SEC_CODE | SEC_READONLY
|
| SEC_MEP_VLIW));
|
| SEC_MEP_VLIW));
|
}
|
}
|
|
|
return vtext_section;
|
return vtext_section;
|
}
|
}
|
|
|
static void
|
static void
|
mep_s_vtext (int ignore ATTRIBUTE_UNUSED)
|
mep_s_vtext (int ignore ATTRIBUTE_UNUSED)
|
{
|
{
|
int temp;
|
int temp;
|
|
|
/* Record previous_section and previous_subsection. */
|
/* Record previous_section and previous_subsection. */
|
obj_elf_section_change_hook ();
|
obj_elf_section_change_hook ();
|
|
|
temp = get_absolute_expression ();
|
temp = get_absolute_expression ();
|
subseg_set (mep_vtext_section (), (subsegT) temp);
|
subseg_set (mep_vtext_section (), (subsegT) temp);
|
demand_empty_rest_of_line ();
|
demand_empty_rest_of_line ();
|
}
|
}
|
|
|
static void
|
static void
|
mep_switch_to_core_mode (int dummy ATTRIBUTE_UNUSED)
|
mep_switch_to_core_mode (int dummy ATTRIBUTE_UNUSED)
|
{
|
{
|
mep_process_saved_insns ();
|
mep_process_saved_insns ();
|
pluspresent = 0;
|
pluspresent = 0;
|
mode = CORE;
|
mode = CORE;
|
}
|
}
|
|
|
static void
|
static void
|
mep_switch_to_vliw_mode (int dummy ATTRIBUTE_UNUSED)
|
mep_switch_to_vliw_mode (int dummy ATTRIBUTE_UNUSED)
|
{
|
{
|
if (! MEP_VLIW)
|
if (! MEP_VLIW)
|
as_bad (_(".vliw unavailable when VLIW is disabled."));
|
as_bad (_(".vliw unavailable when VLIW is disabled."));
|
mode = VLIW;
|
mode = VLIW;
|
/* Switch into .vtext here too. */
|
/* Switch into .vtext here too. */
|
/* mep_s_vtext(); */
|
/* mep_s_vtext(); */
|
}
|
}
|
|
|
/* This is an undocumented pseudo-op used to disable gas's
|
/* This is an undocumented pseudo-op used to disable gas's
|
"disabled_registers" check. Used for code which checks for those
|
"disabled_registers" check. Used for code which checks for those
|
registers at runtime. */
|
registers at runtime. */
|
static void
|
static void
|
mep_noregerr (int i ATTRIBUTE_UNUSED)
|
mep_noregerr (int i ATTRIBUTE_UNUSED)
|
{
|
{
|
allow_disabled_registers = 1;
|
allow_disabled_registers = 1;
|
}
|
}
|
|
|
/* mep_unrecognized_line: This is called when a line that can't be parsed
|
/* mep_unrecognized_line: This is called when a line that can't be parsed
|
is encountered. We use it to check for a leading '+' sign which indicates
|
is encountered. We use it to check for a leading '+' sign which indicates
|
that the current instruction is a coprocessor instruction that is to be
|
that the current instruction is a coprocessor instruction that is to be
|
parallelized with a previous core insn. This function accepts the '+' and
|
parallelized with a previous core insn. This function accepts the '+' and
|
rejects all other characters that might indicate garbage at the beginning
|
rejects all other characters that might indicate garbage at the beginning
|
of the line. The '+' character gets lost as the calling loop continues,
|
of the line. The '+' character gets lost as the calling loop continues,
|
so we need to indicate that we saw it. */
|
so we need to indicate that we saw it. */
|
|
|
int
|
int
|
mep_unrecognized_line (int ch)
|
mep_unrecognized_line (int ch)
|
{
|
{
|
switch (ch)
|
switch (ch)
|
{
|
{
|
case '+':
|
case '+':
|
pluspresent = 1;
|
pluspresent = 1;
|
return 1; /* '+' indicates an instruction to be parallelized. */
|
return 1; /* '+' indicates an instruction to be parallelized. */
|
default:
|
default:
|
return 0; /* If it's not a '+', the line can't be parsed. */
|
return 0; /* If it's not a '+', the line can't be parsed. */
|
}
|
}
|
}
|
}
|
|
|
void
|
void
|
mep_cleanup (void)
|
mep_cleanup (void)
|
{
|
{
|
/* Take care of any insns left to be parallelized when the file ends.
|
/* Take care of any insns left to be parallelized when the file ends.
|
This is mainly here to handle the case where the file ends with an
|
This is mainly here to handle the case where the file ends with an
|
insn preceeded by a + or the file ends unexpectedly. */
|
insn preceeded by a + or the file ends unexpectedly. */
|
if (mode == VLIW)
|
if (mode == VLIW)
|
mep_process_saved_insns ();
|
mep_process_saved_insns ();
|
}
|
}
|
|
|
int
|
int
|
mep_flush_pending_output (void)
|
mep_flush_pending_output (void)
|
{
|
{
|
if (mode == VLIW)
|
if (mode == VLIW)
|
{
|
{
|
mep_process_saved_insns ();
|
mep_process_saved_insns ();
|
pluspresent = 0;
|
pluspresent = 0;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
