@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
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@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
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@c Free Software Foundation, Inc.
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@c Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@ifset GENERIC
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@page
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@page
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@node ARM-Dependent
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@node ARM-Dependent
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@chapter ARM Dependent Features
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@chapter ARM Dependent Features
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@end ifset
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@end ifset
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@ifclear GENERIC
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@ifclear GENERIC
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@node Machine Dependencies
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@node Machine Dependencies
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@chapter ARM Dependent Features
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@chapter ARM Dependent Features
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@end ifclear
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@end ifclear
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@cindex ARM support
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@cindex ARM support
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@cindex Thumb support
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@cindex Thumb support
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@menu
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@menu
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* ARM Options:: Options
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* ARM Options:: Options
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* ARM Syntax:: Syntax
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* ARM Syntax:: Syntax
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* ARM Floating Point:: Floating Point
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* ARM Floating Point:: Floating Point
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* ARM Directives:: ARM Machine Directives
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* ARM Directives:: ARM Machine Directives
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* ARM Opcodes:: Opcodes
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* ARM Opcodes:: Opcodes
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* ARM Mapping Symbols:: Mapping Symbols
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* ARM Mapping Symbols:: Mapping Symbols
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@end menu
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@end menu
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@node ARM Options
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@node ARM Options
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@section Options
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@section Options
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@cindex ARM options (none)
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@cindex ARM options (none)
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@cindex options for ARM (none)
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@cindex options for ARM (none)
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@table @code
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@table @code
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@cindex @code{-mcpu=} command line option, ARM
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@cindex @code{-mcpu=} command line option, ARM
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@item -mcpu=@var{processor}[+@var{extension}@dots{}]
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@item -mcpu=@var{processor}[+@var{extension}@dots{}]
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This option specifies the target processor. The assembler will issue an
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This option specifies the target processor. The assembler will issue an
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error message if an attempt is made to assemble an instruction which
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error message if an attempt is made to assemble an instruction which
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will not execute on the target processor. The following processor names are
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will not execute on the target processor. The following processor names are
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recognized:
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recognized:
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@code{arm1},
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@code{arm1},
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@code{arm2},
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@code{arm2},
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@code{arm250},
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@code{arm250},
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@code{arm3},
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@code{arm3},
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@code{arm6},
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@code{arm6},
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@code{arm60},
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@code{arm60},
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@code{arm600},
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@code{arm600},
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@code{arm610},
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@code{arm610},
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@code{arm620},
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@code{arm620},
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@code{arm7},
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@code{arm7},
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@code{arm7m},
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@code{arm7m},
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@code{arm7d},
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@code{arm7d},
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@code{arm7dm},
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@code{arm7dm},
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@code{arm7di},
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@code{arm7di},
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@code{arm7dmi},
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@code{arm7dmi},
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@code{arm70},
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@code{arm70},
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@code{arm700},
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@code{arm700},
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@code{arm700i},
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@code{arm700i},
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@code{arm710},
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@code{arm710},
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@code{arm710t},
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@code{arm710t},
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@code{arm720},
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@code{arm720},
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@code{arm720t},
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@code{arm720t},
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@code{arm740t},
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@code{arm740t},
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@code{arm710c},
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@code{arm710c},
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@code{arm7100},
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@code{arm7100},
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@code{arm7500},
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@code{arm7500},
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@code{arm7500fe},
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@code{arm7500fe},
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@code{arm7t},
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@code{arm7t},
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@code{arm7tdmi},
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@code{arm7tdmi},
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@code{arm7tdmi-s},
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@code{arm7tdmi-s},
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@code{arm8},
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@code{arm8},
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@code{arm810},
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@code{arm810},
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@code{strongarm},
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@code{strongarm},
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@code{strongarm1},
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@code{strongarm1},
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@code{strongarm110},
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@code{strongarm110},
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@code{strongarm1100},
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@code{strongarm1100},
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@code{strongarm1110},
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@code{strongarm1110},
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@code{arm9},
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@code{arm9},
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@code{arm920},
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@code{arm920},
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@code{arm920t},
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@code{arm920t},
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@code{arm922t},
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@code{arm922t},
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@code{arm940t},
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@code{arm940t},
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@code{arm9tdmi},
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@code{arm9tdmi},
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@code{arm9e},
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@code{arm9e},
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@code{arm926e},
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@code{arm926e},
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@code{arm926ej-s},
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@code{arm926ej-s},
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@code{arm946e-r0},
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@code{arm946e-r0},
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@code{arm946e},
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@code{arm946e},
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@code{arm946e-s},
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@code{arm946e-s},
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@code{arm966e-r0},
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@code{arm966e-r0},
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@code{arm966e},
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@code{arm966e},
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@code{arm966e-s},
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@code{arm966e-s},
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@code{arm968e-s},
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@code{arm968e-s},
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@code{arm10t},
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@code{arm10t},
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@code{arm10tdmi},
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@code{arm10tdmi},
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@code{arm10e},
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@code{arm10e},
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@code{arm1020},
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@code{arm1020},
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@code{arm1020t},
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@code{arm1020t},
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@code{arm1020e},
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@code{arm1020e},
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@code{arm1022e},
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@code{arm1022e},
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@code{arm1026ej-s},
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@code{arm1026ej-s},
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@code{arm1136j-s},
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@code{arm1136j-s},
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@code{arm1136jf-s},
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@code{arm1136jf-s},
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@code{arm1156t2-s},
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@code{arm1156t2-s},
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@code{arm1156t2f-s},
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@code{arm1156t2f-s},
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@code{arm1176jz-s},
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@code{arm1176jz-s},
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@code{arm1176jzf-s},
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@code{arm1176jzf-s},
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@code{mpcore},
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@code{mpcore},
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@code{mpcorenovfp},
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@code{mpcorenovfp},
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@code{cortex-a8},
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@code{cortex-a8},
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@code{cortex-a9},
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@code{cortex-a9},
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@code{cortex-r4},
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@code{cortex-r4},
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@code{cortex-m3},
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@code{cortex-m3},
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@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
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@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
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@code{i80200} (Intel XScale processor)
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@code{i80200} (Intel XScale processor)
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@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
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@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
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and
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and
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@code{xscale}.
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@code{xscale}.
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The special name @code{all} may be used to allow the
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The special name @code{all} may be used to allow the
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assembler to accept instructions valid for any ARM processor.
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assembler to accept instructions valid for any ARM processor.
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In addition to the basic instruction set, the assembler can be told to
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In addition to the basic instruction set, the assembler can be told to
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accept various extension mnemonics that extend the processor using the
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accept various extension mnemonics that extend the processor using the
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co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
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co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
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is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
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is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
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are currently supported:
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are currently supported:
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@code{+maverick}
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@code{+maverick}
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@code{+iwmmxt}
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@code{+iwmmxt}
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and
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and
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@code{+xscale}.
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@code{+xscale}.
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@cindex @code{-march=} command line option, ARM
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@cindex @code{-march=} command line option, ARM
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@item -march=@var{architecture}[+@var{extension}@dots{}]
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@item -march=@var{architecture}[+@var{extension}@dots{}]
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This option specifies the target architecture. The assembler will issue
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This option specifies the target architecture. The assembler will issue
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an error message if an attempt is made to assemble an instruction which
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an error message if an attempt is made to assemble an instruction which
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will not execute on the target architecture. The following architecture
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will not execute on the target architecture. The following architecture
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names are recognized:
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names are recognized:
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@code{armv1},
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@code{armv1},
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@code{armv2},
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@code{armv2},
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@code{armv2a},
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@code{armv2a},
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@code{armv2s},
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@code{armv2s},
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@code{armv3},
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@code{armv3},
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@code{armv3m},
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@code{armv3m},
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@code{armv4},
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@code{armv4},
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@code{armv4xm},
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@code{armv4xm},
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@code{armv4t},
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@code{armv4t},
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@code{armv4txm},
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@code{armv4txm},
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@code{armv5},
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@code{armv5},
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@code{armv5t},
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@code{armv5t},
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@code{armv5txm},
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@code{armv5txm},
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@code{armv5te},
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@code{armv5te},
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@code{armv5texp},
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@code{armv5texp},
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@code{armv6},
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@code{armv6},
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@code{armv6j},
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@code{armv6j},
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@code{armv6k},
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@code{armv6k},
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@code{armv6z},
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@code{armv6z},
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@code{armv6zk},
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@code{armv6zk},
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@code{armv7},
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@code{armv7},
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@code{armv7-a},
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@code{armv7-a},
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@code{armv7-r},
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@code{armv7-r},
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@code{armv7-m},
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@code{armv7-m},
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@code{iwmmxt}
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@code{iwmmxt}
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and
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and
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@code{xscale}.
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@code{xscale}.
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If both @code{-mcpu} and
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If both @code{-mcpu} and
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@code{-march} are specified, the assembler will use
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@code{-march} are specified, the assembler will use
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the setting for @code{-mcpu}.
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the setting for @code{-mcpu}.
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The architecture option can be extended with the same instruction set
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The architecture option can be extended with the same instruction set
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extension options as the @code{-mcpu} option.
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extension options as the @code{-mcpu} option.
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@cindex @code{-mfpu=} command line option, ARM
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@cindex @code{-mfpu=} command line option, ARM
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@item -mfpu=@var{floating-point-format}
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@item -mfpu=@var{floating-point-format}
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|
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This option specifies the floating point format to assemble for. The
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This option specifies the floating point format to assemble for. The
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assembler will issue an error message if an attempt is made to assemble
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assembler will issue an error message if an attempt is made to assemble
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an instruction which will not execute on the target floating point unit.
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an instruction which will not execute on the target floating point unit.
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The following format options are recognized:
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The following format options are recognized:
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@code{softfpa},
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@code{softfpa},
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@code{fpe},
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@code{fpe},
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@code{fpe2},
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@code{fpe2},
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@code{fpe3},
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@code{fpe3},
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@code{fpa},
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@code{fpa},
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@code{fpa10},
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@code{fpa10},
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@code{fpa11},
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@code{fpa11},
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@code{arm7500fe},
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@code{arm7500fe},
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@code{softvfp},
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@code{softvfp},
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@code{softvfp+vfp},
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@code{softvfp+vfp},
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@code{vfp},
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@code{vfp},
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@code{vfp10},
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@code{vfp10},
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@code{vfp10-r0},
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@code{vfp10-r0},
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@code{vfp9},
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@code{vfp9},
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@code{vfpxd},
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@code{vfpxd},
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@code{vfpv2}
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@code{vfpv2}
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@code{vfpv3}
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@code{vfpv3}
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@code{vfpv3-d16}
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@code{vfpv3-d16}
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@code{arm1020t},
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@code{arm1020t},
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@code{arm1020e},
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@code{arm1020e},
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@code{arm1136jf-s},
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@code{arm1136jf-s},
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@code{maverick}
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@code{maverick}
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and
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and
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@code{neon}.
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@code{neon}.
|
|
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In addition to determining which instructions are assembled, this option
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In addition to determining which instructions are assembled, this option
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also affects the way in which the @code{.double} assembler directive behaves
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also affects the way in which the @code{.double} assembler directive behaves
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when assembling little-endian code.
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when assembling little-endian code.
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|
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The default is dependent on the processor selected. For Architecture 5 or
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The default is dependent on the processor selected. For Architecture 5 or
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later, the default is to assembler for VFP instructions; for earlier
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later, the default is to assembler for VFP instructions; for earlier
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architectures the default is to assemble for FPA instructions.
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architectures the default is to assemble for FPA instructions.
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|
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@cindex @code{-mthumb} command line option, ARM
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@cindex @code{-mthumb} command line option, ARM
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@item -mthumb
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@item -mthumb
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This option specifies that the assembler should start assembling Thumb
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This option specifies that the assembler should start assembling Thumb
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instructions; that is, it should behave as though the file starts with a
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instructions; that is, it should behave as though the file starts with a
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@code{.code 16} directive.
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@code{.code 16} directive.
|
|
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@cindex @code{-mthumb-interwork} command line option, ARM
|
@cindex @code{-mthumb-interwork} command line option, ARM
|
@item -mthumb-interwork
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@item -mthumb-interwork
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This option specifies that the output generated by the assembler should
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This option specifies that the output generated by the assembler should
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be marked as supporting interworking.
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be marked as supporting interworking.
|
|
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@cindex @code{-mapcs} command line option, ARM
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@cindex @code{-mapcs} command line option, ARM
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@item -mapcs @code{[26|32]}
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@item -mapcs @code{[26|32]}
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This option specifies that the output generated by the assembler should
|
This option specifies that the output generated by the assembler should
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be marked as supporting the indicated version of the Arm Procedure.
|
be marked as supporting the indicated version of the Arm Procedure.
|
Calling Standard.
|
Calling Standard.
|
|
|
@cindex @code{-matpcs} command line option, ARM
|
@cindex @code{-matpcs} command line option, ARM
|
@item -matpcs
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@item -matpcs
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This option specifies that the output generated by the assembler should
|
This option specifies that the output generated by the assembler should
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be marked as supporting the Arm/Thumb Procedure Calling Standard. If
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be marked as supporting the Arm/Thumb Procedure Calling Standard. If
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enabled this option will cause the assembler to create an empty
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enabled this option will cause the assembler to create an empty
|
debugging section in the object file called .arm.atpcs. Debuggers can
|
debugging section in the object file called .arm.atpcs. Debuggers can
|
use this to determine the ABI being used by.
|
use this to determine the ABI being used by.
|
|
|
@cindex @code{-mapcs-float} command line option, ARM
|
@cindex @code{-mapcs-float} command line option, ARM
|
@item -mapcs-float
|
@item -mapcs-float
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This indicates the floating point variant of the APCS should be
|
This indicates the floating point variant of the APCS should be
|
used. In this variant floating point arguments are passed in FP
|
used. In this variant floating point arguments are passed in FP
|
registers rather than integer registers.
|
registers rather than integer registers.
|
|
|
@cindex @code{-mapcs-reentrant} command line option, ARM
|
@cindex @code{-mapcs-reentrant} command line option, ARM
|
@item -mapcs-reentrant
|
@item -mapcs-reentrant
|
This indicates that the reentrant variant of the APCS should be used.
|
This indicates that the reentrant variant of the APCS should be used.
|
This variant supports position independent code.
|
This variant supports position independent code.
|
|
|
@cindex @code{-mfloat-abi=} command line option, ARM
|
@cindex @code{-mfloat-abi=} command line option, ARM
|
@item -mfloat-abi=@var{abi}
|
@item -mfloat-abi=@var{abi}
|
This option specifies that the output generated by the assembler should be
|
This option specifies that the output generated by the assembler should be
|
marked as using specified floating point ABI.
|
marked as using specified floating point ABI.
|
The following values are recognized:
|
The following values are recognized:
|
@code{soft},
|
@code{soft},
|
@code{softfp}
|
@code{softfp}
|
and
|
and
|
@code{hard}.
|
@code{hard}.
|
|
|
@cindex @code{-eabi=} command line option, ARM
|
@cindex @code{-eabi=} command line option, ARM
|
@item -meabi=@var{ver}
|
@item -meabi=@var{ver}
|
This option specifies which EABI version the produced object files should
|
This option specifies which EABI version the produced object files should
|
conform to.
|
conform to.
|
The following values are recognized:
|
The following values are recognized:
|
@code{gnu},
|
@code{gnu},
|
@code{4}
|
@code{4}
|
and
|
and
|
@code{5}.
|
@code{5}.
|
|
|
@cindex @code{-EB} command line option, ARM
|
@cindex @code{-EB} command line option, ARM
|
@item -EB
|
@item -EB
|
This option specifies that the output generated by the assembler should
|
This option specifies that the output generated by the assembler should
|
be marked as being encoded for a big-endian processor.
|
be marked as being encoded for a big-endian processor.
|
|
|
@cindex @code{-EL} command line option, ARM
|
@cindex @code{-EL} command line option, ARM
|
@item -EL
|
@item -EL
|
This option specifies that the output generated by the assembler should
|
This option specifies that the output generated by the assembler should
|
be marked as being encoded for a little-endian processor.
|
be marked as being encoded for a little-endian processor.
|
|
|
@cindex @code{-k} command line option, ARM
|
@cindex @code{-k} command line option, ARM
|
@cindex PIC code generation for ARM
|
@cindex PIC code generation for ARM
|
@item -k
|
@item -k
|
This option specifies that the output of the assembler should be marked
|
This option specifies that the output of the assembler should be marked
|
as position-independent code (PIC).
|
as position-independent code (PIC).
|
|
|
@cindex @code{--fix-v4bx} command line option, ARM
|
@cindex @code{--fix-v4bx} command line option, ARM
|
@item --fix-v4bx
|
@item --fix-v4bx
|
Allow @code{BX} instructions in ARMv4 code. This is intended for use with
|
Allow @code{BX} instructions in ARMv4 code. This is intended for use with
|
the linker option of the same name.
|
the linker option of the same name.
|
|
|
@end table
|
@end table
|
|
|
|
|
@node ARM Syntax
|
@node ARM Syntax
|
@section Syntax
|
@section Syntax
|
@menu
|
@menu
|
* ARM-Chars:: Special Characters
|
* ARM-Chars:: Special Characters
|
* ARM-Regs:: Register Names
|
* ARM-Regs:: Register Names
|
* ARM-Relocations:: Relocations
|
* ARM-Relocations:: Relocations
|
@end menu
|
@end menu
|
|
|
@node ARM-Chars
|
@node ARM-Chars
|
@subsection Special Characters
|
@subsection Special Characters
|
|
|
@cindex line comment character, ARM
|
@cindex line comment character, ARM
|
@cindex ARM line comment character
|
@cindex ARM line comment character
|
The presence of a @samp{@@} on a line indicates the start of a comment
|
The presence of a @samp{@@} on a line indicates the start of a comment
|
that extends to the end of the current line. If a @samp{#} appears as
|
that extends to the end of the current line. If a @samp{#} appears as
|
the first character of a line, the whole line is treated as a comment.
|
the first character of a line, the whole line is treated as a comment.
|
|
|
@cindex line separator, ARM
|
@cindex line separator, ARM
|
@cindex statement separator, ARM
|
@cindex statement separator, ARM
|
@cindex ARM line separator
|
@cindex ARM line separator
|
The @samp{;} character can be used instead of a newline to separate
|
The @samp{;} character can be used instead of a newline to separate
|
statements.
|
statements.
|
|
|
@cindex immediate character, ARM
|
@cindex immediate character, ARM
|
@cindex ARM immediate character
|
@cindex ARM immediate character
|
Either @samp{#} or @samp{$} can be used to indicate immediate operands.
|
Either @samp{#} or @samp{$} can be used to indicate immediate operands.
|
|
|
@cindex identifiers, ARM
|
@cindex identifiers, ARM
|
@cindex ARM identifiers
|
@cindex ARM identifiers
|
*TODO* Explain about /data modifier on symbols.
|
*TODO* Explain about /data modifier on symbols.
|
|
|
@node ARM-Regs
|
@node ARM-Regs
|
@subsection Register Names
|
@subsection Register Names
|
|
|
@cindex ARM register names
|
@cindex ARM register names
|
@cindex register names, ARM
|
@cindex register names, ARM
|
*TODO* Explain about ARM register naming, and the predefined names.
|
*TODO* Explain about ARM register naming, and the predefined names.
|
|
|
@node ARM Floating Point
|
@node ARM Floating Point
|
@section Floating Point
|
@section Floating Point
|
|
|
@cindex floating point, ARM (@sc{ieee})
|
@cindex floating point, ARM (@sc{ieee})
|
@cindex ARM floating point (@sc{ieee})
|
@cindex ARM floating point (@sc{ieee})
|
The ARM family uses @sc{ieee} floating-point numbers.
|
The ARM family uses @sc{ieee} floating-point numbers.
|
|
|
@node ARM-Relocations
|
@node ARM-Relocations
|
@subsection ARM relocation generation
|
@subsection ARM relocation generation
|
|
|
@cindex data relocations, ARM
|
@cindex data relocations, ARM
|
@cindex ARM data relocations
|
@cindex ARM data relocations
|
Specific data relocations can be generated by putting the relocation name
|
Specific data relocations can be generated by putting the relocation name
|
in parentheses after the symbol name. For example:
|
in parentheses after the symbol name. For example:
|
|
|
@smallexample
|
@smallexample
|
.word foo(TARGET1)
|
.word foo(TARGET1)
|
@end smallexample
|
@end smallexample
|
|
|
This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
|
This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
|
@var{foo}.
|
@var{foo}.
|
The following relocations are supported:
|
The following relocations are supported:
|
@code{GOT},
|
@code{GOT},
|
@code{GOTOFF},
|
@code{GOTOFF},
|
@code{TARGET1},
|
@code{TARGET1},
|
@code{TARGET2},
|
@code{TARGET2},
|
@code{SBREL},
|
@code{SBREL},
|
@code{TLSGD},
|
@code{TLSGD},
|
@code{TLSLDM},
|
@code{TLSLDM},
|
@code{TLSLDO},
|
@code{TLSLDO},
|
@code{GOTTPOFF}
|
@code{GOTTPOFF}
|
and
|
and
|
@code{TPOFF}.
|
@code{TPOFF}.
|
|
|
For compatibility with older toolchains the assembler also accepts
|
For compatibility with older toolchains the assembler also accepts
|
@code{(PLT)} after branch targets. This will generate the deprecated
|
@code{(PLT)} after branch targets. This will generate the deprecated
|
@samp{R_ARM_PLT32} relocation.
|
@samp{R_ARM_PLT32} relocation.
|
|
|
@cindex MOVW and MOVT relocations, ARM
|
@cindex MOVW and MOVT relocations, ARM
|
Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
|
Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
|
by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
|
by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
|
respectively. For example to load the 32-bit address of foo into r0:
|
respectively. For example to load the 32-bit address of foo into r0:
|
|
|
@smallexample
|
@smallexample
|
MOVW r0, #:lower16:foo
|
MOVW r0, #:lower16:foo
|
MOVT r0, #:upper16:foo
|
MOVT r0, #:upper16:foo
|
@end smallexample
|
@end smallexample
|
|
|
@node ARM Directives
|
@node ARM Directives
|
@section ARM Machine Directives
|
@section ARM Machine Directives
|
|
|
@cindex machine directives, ARM
|
@cindex machine directives, ARM
|
@cindex ARM machine directives
|
@cindex ARM machine directives
|
@table @code
|
@table @code
|
|
|
@cindex @code{align} directive, ARM
|
@cindex @code{align} directive, ARM
|
@item .align @var{expression} [, @var{expression}]
|
@item .align @var{expression} [, @var{expression}]
|
This is the generic @var{.align} directive. For the ARM however if the
|
This is the generic @var{.align} directive. For the ARM however if the
|
first argument is zero (ie no alignment is needed) the assembler will
|
first argument is zero (ie no alignment is needed) the assembler will
|
behave as if the argument had been 2 (ie pad to the next four byte
|
behave as if the argument had been 2 (ie pad to the next four byte
|
boundary). This is for compatibility with ARM's own assembler.
|
boundary). This is for compatibility with ARM's own assembler.
|
|
|
@cindex @code{req} directive, ARM
|
@cindex @code{req} directive, ARM
|
@item @var{name} .req @var{register name}
|
@item @var{name} .req @var{register name}
|
This creates an alias for @var{register name} called @var{name}. For
|
This creates an alias for @var{register name} called @var{name}. For
|
example:
|
example:
|
|
|
@smallexample
|
@smallexample
|
foo .req r0
|
foo .req r0
|
@end smallexample
|
@end smallexample
|
|
|
@cindex @code{unreq} directive, ARM
|
@cindex @code{unreq} directive, ARM
|
@item .unreq @var{alias-name}
|
@item .unreq @var{alias-name}
|
This undefines a register alias which was previously defined using the
|
This undefines a register alias which was previously defined using the
|
@code{req}, @code{dn} or @code{qn} directives. For example:
|
@code{req}, @code{dn} or @code{qn} directives. For example:
|
|
|
@smallexample
|
@smallexample
|
foo .req r0
|
foo .req r0
|
.unreq foo
|
.unreq foo
|
@end smallexample
|
@end smallexample
|
|
|
An error occurs if the name is undefined. Note - this pseudo op can
|
An error occurs if the name is undefined. Note - this pseudo op can
|
be used to delete builtin in register name aliases (eg 'r0'). This
|
be used to delete builtin in register name aliases (eg 'r0'). This
|
should only be done if it is really necessary.
|
should only be done if it is really necessary.
|
|
|
@cindex @code{dn} and @code{qn} directives, ARM
|
@cindex @code{dn} and @code{qn} directives, ARM
|
@item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
|
@item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
|
@item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
|
@item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
|
|
|
The @code{dn} and @code{qn} directives are used to create typed
|
The @code{dn} and @code{qn} directives are used to create typed
|
and/or indexed register aliases for use in Advanced SIMD Extension
|
and/or indexed register aliases for use in Advanced SIMD Extension
|
(Neon) instructions. The former should be used to create aliases
|
(Neon) instructions. The former should be used to create aliases
|
of double-precision registers, and the latter to create aliases of
|
of double-precision registers, and the latter to create aliases of
|
quad-precision registers.
|
quad-precision registers.
|
|
|
If these directives are used to create typed aliases, those aliases can
|
If these directives are used to create typed aliases, those aliases can
|
be used in Neon instructions instead of writing types after the mnemonic
|
be used in Neon instructions instead of writing types after the mnemonic
|
or after each operand. For example:
|
or after each operand. For example:
|
|
|
@smallexample
|
@smallexample
|
x .dn d2.f32
|
x .dn d2.f32
|
y .dn d3.f32
|
y .dn d3.f32
|
z .dn d4.f32[1]
|
z .dn d4.f32[1]
|
vmul x,y,z
|
vmul x,y,z
|
@end smallexample
|
@end smallexample
|
|
|
This is equivalent to writing the following:
|
This is equivalent to writing the following:
|
|
|
@smallexample
|
@smallexample
|
vmul.f32 d2,d3,d4[1]
|
vmul.f32 d2,d3,d4[1]
|
@end smallexample
|
@end smallexample
|
|
|
Aliases created using @code{dn} or @code{qn} can be destroyed using
|
Aliases created using @code{dn} or @code{qn} can be destroyed using
|
@code{unreq}.
|
@code{unreq}.
|
|
|
@cindex @code{code} directive, ARM
|
@cindex @code{code} directive, ARM
|
@item .code @code{[16|32]}
|
@item .code @code{[16|32]}
|
This directive selects the instruction set being generated. The value 16
|
This directive selects the instruction set being generated. The value 16
|
selects Thumb, with the value 32 selecting ARM.
|
selects Thumb, with the value 32 selecting ARM.
|
|
|
@cindex @code{thumb} directive, ARM
|
@cindex @code{thumb} directive, ARM
|
@item .thumb
|
@item .thumb
|
This performs the same action as @var{.code 16}.
|
This performs the same action as @var{.code 16}.
|
|
|
@cindex @code{arm} directive, ARM
|
@cindex @code{arm} directive, ARM
|
@item .arm
|
@item .arm
|
This performs the same action as @var{.code 32}.
|
This performs the same action as @var{.code 32}.
|
|
|
@cindex @code{force_thumb} directive, ARM
|
@cindex @code{force_thumb} directive, ARM
|
@item .force_thumb
|
@item .force_thumb
|
This directive forces the selection of Thumb instructions, even if the
|
This directive forces the selection of Thumb instructions, even if the
|
target processor does not support those instructions
|
target processor does not support those instructions
|
|
|
@cindex @code{thumb_func} directive, ARM
|
@cindex @code{thumb_func} directive, ARM
|
@item .thumb_func
|
@item .thumb_func
|
This directive specifies that the following symbol is the name of a
|
This directive specifies that the following symbol is the name of a
|
Thumb encoded function. This information is necessary in order to allow
|
Thumb encoded function. This information is necessary in order to allow
|
the assembler and linker to generate correct code for interworking
|
the assembler and linker to generate correct code for interworking
|
between Arm and Thumb instructions and should be used even if
|
between Arm and Thumb instructions and should be used even if
|
interworking is not going to be performed. The presence of this
|
interworking is not going to be performed. The presence of this
|
directive also implies @code{.thumb}
|
directive also implies @code{.thumb}
|
|
|
This directive is not neccessary when generating EABI objects. On these
|
This directive is not neccessary when generating EABI objects. On these
|
targets the encoding is implicit when generating Thumb code.
|
targets the encoding is implicit when generating Thumb code.
|
|
|
@cindex @code{thumb_set} directive, ARM
|
@cindex @code{thumb_set} directive, ARM
|
@item .thumb_set
|
@item .thumb_set
|
This performs the equivalent of a @code{.set} directive in that it
|
This performs the equivalent of a @code{.set} directive in that it
|
creates a symbol which is an alias for another symbol (possibly not yet
|
creates a symbol which is an alias for another symbol (possibly not yet
|
defined). This directive also has the added property in that it marks
|
defined). This directive also has the added property in that it marks
|
the aliased symbol as being a thumb function entry point, in the same
|
the aliased symbol as being a thumb function entry point, in the same
|
way that the @code{.thumb_func} directive does.
|
way that the @code{.thumb_func} directive does.
|
|
|
@cindex @code{.ltorg} directive, ARM
|
@cindex @code{.ltorg} directive, ARM
|
@item .ltorg
|
@item .ltorg
|
This directive causes the current contents of the literal pool to be
|
This directive causes the current contents of the literal pool to be
|
dumped into the current section (which is assumed to be the .text
|
dumped into the current section (which is assumed to be the .text
|
section) at the current location (aligned to a word boundary).
|
section) at the current location (aligned to a word boundary).
|
@code{GAS} maintains a separate literal pool for each section and each
|
@code{GAS} maintains a separate literal pool for each section and each
|
sub-section. The @code{.ltorg} directive will only affect the literal
|
sub-section. The @code{.ltorg} directive will only affect the literal
|
pool of the current section and sub-section. At the end of assembly
|
pool of the current section and sub-section. At the end of assembly
|
all remaining, un-empty literal pools will automatically be dumped.
|
all remaining, un-empty literal pools will automatically be dumped.
|
|
|
Note - older versions of @code{GAS} would dump the current literal
|
Note - older versions of @code{GAS} would dump the current literal
|
pool any time a section change occurred. This is no longer done, since
|
pool any time a section change occurred. This is no longer done, since
|
it prevents accurate control of the placement of literal pools.
|
it prevents accurate control of the placement of literal pools.
|
|
|
@cindex @code{.pool} directive, ARM
|
@cindex @code{.pool} directive, ARM
|
@item .pool
|
@item .pool
|
This is a synonym for .ltorg.
|
This is a synonym for .ltorg.
|
|
|
@cindex @code{.fnstart} directive, ARM
|
@cindex @code{.fnstart} directive, ARM
|
@item .fnstart
|
@item .fnstart
|
Marks the start of a function with an unwind table entry.
|
Marks the start of a function with an unwind table entry.
|
|
|
@cindex @code{.fnend} directive, ARM
|
@cindex @code{.fnend} directive, ARM
|
@item .fnend
|
@item .fnend
|
Marks the end of a function with an unwind table entry. The unwind index
|
Marks the end of a function with an unwind table entry. The unwind index
|
table entry is created when this directive is processed.
|
table entry is created when this directive is processed.
|
|
|
If no personality routine has been specified then standard personality
|
If no personality routine has been specified then standard personality
|
routine 0 or 1 will be used, depending on the number of unwind opcodes
|
routine 0 or 1 will be used, depending on the number of unwind opcodes
|
required.
|
required.
|
|
|
@cindex @code{.cantunwind} directive, ARM
|
@cindex @code{.cantunwind} directive, ARM
|
@item .cantunwind
|
@item .cantunwind
|
Prevents unwinding through the current function. No personality routine
|
Prevents unwinding through the current function. No personality routine
|
or exception table data is required or permitted.
|
or exception table data is required or permitted.
|
|
|
@cindex @code{.personality} directive, ARM
|
@cindex @code{.personality} directive, ARM
|
@item .personality @var{name}
|
@item .personality @var{name}
|
Sets the personality routine for the current function to @var{name}.
|
Sets the personality routine for the current function to @var{name}.
|
|
|
@cindex @code{.personalityindex} directive, ARM
|
@cindex @code{.personalityindex} directive, ARM
|
@item .personalityindex @var{index}
|
@item .personalityindex @var{index}
|
Sets the personality routine for the current function to the EABI standard
|
Sets the personality routine for the current function to the EABI standard
|
routine number @var{index}
|
routine number @var{index}
|
|
|
@cindex @code{.handlerdata} directive, ARM
|
@cindex @code{.handlerdata} directive, ARM
|
@item .handlerdata
|
@item .handlerdata
|
Marks the end of the current function, and the start of the exception table
|
Marks the end of the current function, and the start of the exception table
|
entry for that function. Anything between this directive and the
|
entry for that function. Anything between this directive and the
|
@code{.fnend} directive will be added to the exception table entry.
|
@code{.fnend} directive will be added to the exception table entry.
|
|
|
Must be preceded by a @code{.personality} or @code{.personalityindex}
|
Must be preceded by a @code{.personality} or @code{.personalityindex}
|
directive.
|
directive.
|
|
|
@cindex @code{.save} directive, ARM
|
@cindex @code{.save} directive, ARM
|
@item .save @var{reglist}
|
@item .save @var{reglist}
|
Generate unwinder annotations to restore the registers in @var{reglist}.
|
Generate unwinder annotations to restore the registers in @var{reglist}.
|
The format of @var{reglist} is the same as the corresponding store-multiple
|
The format of @var{reglist} is the same as the corresponding store-multiple
|
instruction.
|
instruction.
|
|
|
@smallexample
|
@smallexample
|
@exdent @emph{core registers}
|
@exdent @emph{core registers}
|
.save @{r4, r5, r6, lr@}
|
.save @{r4, r5, r6, lr@}
|
stmfd sp!, @{r4, r5, r6, lr@}
|
stmfd sp!, @{r4, r5, r6, lr@}
|
@exdent @emph{FPA registers}
|
@exdent @emph{FPA registers}
|
.save f4, 2
|
.save f4, 2
|
sfmfd f4, 2, [sp]!
|
sfmfd f4, 2, [sp]!
|
@exdent @emph{VFP registers}
|
@exdent @emph{VFP registers}
|
.save @{d8, d9, d10@}
|
.save @{d8, d9, d10@}
|
fstmdx sp!, @{d8, d9, d10@}
|
fstmdx sp!, @{d8, d9, d10@}
|
@exdent @emph{iWMMXt registers}
|
@exdent @emph{iWMMXt registers}
|
.save @{wr10, wr11@}
|
.save @{wr10, wr11@}
|
wstrd wr11, [sp, #-8]!
|
wstrd wr11, [sp, #-8]!
|
wstrd wr10, [sp, #-8]!
|
wstrd wr10, [sp, #-8]!
|
or
|
or
|
.save wr11
|
.save wr11
|
wstrd wr11, [sp, #-8]!
|
wstrd wr11, [sp, #-8]!
|
.save wr10
|
.save wr10
|
wstrd wr10, [sp, #-8]!
|
wstrd wr10, [sp, #-8]!
|
@end smallexample
|
@end smallexample
|
|
|
@cindex @code{.vsave} directive, ARM
|
@cindex @code{.vsave} directive, ARM
|
@item .vsave @var{vfp-reglist}
|
@item .vsave @var{vfp-reglist}
|
Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
|
Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
|
using FLDMD. Also works for VFPv3 registers
|
using FLDMD. Also works for VFPv3 registers
|
that are to be restored using VLDM.
|
that are to be restored using VLDM.
|
The format of @var{vfp-reglist} is the same as the corresponding store-multiple
|
The format of @var{vfp-reglist} is the same as the corresponding store-multiple
|
instruction.
|
instruction.
|
|
|
@smallexample
|
@smallexample
|
@exdent @emph{VFP registers}
|
@exdent @emph{VFP registers}
|
.vsave @{d8, d9, d10@}
|
.vsave @{d8, d9, d10@}
|
fstmdd sp!, @{d8, d9, d10@}
|
fstmdd sp!, @{d8, d9, d10@}
|
@exdent @emph{VFPv3 registers}
|
@exdent @emph{VFPv3 registers}
|
.vsave @{d15, d16, d17@}
|
.vsave @{d15, d16, d17@}
|
vstm sp!, @{d15, d16, d17@}
|
vstm sp!, @{d15, d16, d17@}
|
@end smallexample
|
@end smallexample
|
|
|
Since FLDMX and FSTMX are now deprecated, this directive should be
|
Since FLDMX and FSTMX are now deprecated, this directive should be
|
used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
|
used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
|
|
|
@cindex @code{.pad} directive, ARM
|
@cindex @code{.pad} directive, ARM
|
@item .pad #@var{count}
|
@item .pad #@var{count}
|
Generate unwinder annotations for a stack adjustment of @var{count} bytes.
|
Generate unwinder annotations for a stack adjustment of @var{count} bytes.
|
A positive value indicates the function prologue allocated stack space by
|
A positive value indicates the function prologue allocated stack space by
|
decrementing the stack pointer.
|
decrementing the stack pointer.
|
|
|
@cindex @code{.movsp} directive, ARM
|
@cindex @code{.movsp} directive, ARM
|
@item .movsp @var{reg} [, #@var{offset}]
|
@item .movsp @var{reg} [, #@var{offset}]
|
Tell the unwinder that @var{reg} contains an offset from the current
|
Tell the unwinder that @var{reg} contains an offset from the current
|
stack pointer. If @var{offset} is not specified then it is assumed to be
|
stack pointer. If @var{offset} is not specified then it is assumed to be
|
zero.
|
zero.
|
|
|
@cindex @code{.setfp} directive, ARM
|
@cindex @code{.setfp} directive, ARM
|
@item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
|
@item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
|
Make all unwinder annotations relaive to a frame pointer. Without this
|
Make all unwinder annotations relaive to a frame pointer. Without this
|
the unwinder will use offsets from the stack pointer.
|
the unwinder will use offsets from the stack pointer.
|
|
|
The syntax of this directive is the same as the @code{sub} or @code{mov}
|
The syntax of this directive is the same as the @code{sub} or @code{mov}
|
instruction used to set the frame pointer. @var{spreg} must be either
|
instruction used to set the frame pointer. @var{spreg} must be either
|
@code{sp} or mentioned in a previous @code{.movsp} directive.
|
@code{sp} or mentioned in a previous @code{.movsp} directive.
|
|
|
@smallexample
|
@smallexample
|
.movsp ip
|
.movsp ip
|
mov ip, sp
|
mov ip, sp
|
@dots{}
|
@dots{}
|
.setfp fp, ip, #4
|
.setfp fp, ip, #4
|
sub fp, ip, #4
|
sub fp, ip, #4
|
@end smallexample
|
@end smallexample
|
|
|
@cindex @code{.unwind_raw} directive, ARM
|
@cindex @code{.unwind_raw} directive, ARM
|
@item .raw @var{offset}, @var{byte1}, @dots{}
|
@item .raw @var{offset}, @var{byte1}, @dots{}
|
Insert one of more arbitary unwind opcode bytes, which are known to adjust
|
Insert one of more arbitary unwind opcode bytes, which are known to adjust
|
the stack pointer by @var{offset} bytes.
|
the stack pointer by @var{offset} bytes.
|
|
|
For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
|
For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
|
@code{.save @{r0@}}
|
@code{.save @{r0@}}
|
|
|
@cindex @code{.cpu} directive, ARM
|
@cindex @code{.cpu} directive, ARM
|
@item .cpu @var{name}
|
@item .cpu @var{name}
|
Select the target processor. Valid values for @var{name} are the same as
|
Select the target processor. Valid values for @var{name} are the same as
|
for the @option{-mcpu} commandline option.
|
for the @option{-mcpu} commandline option.
|
|
|
@cindex @code{.arch} directive, ARM
|
@cindex @code{.arch} directive, ARM
|
@item .arch @var{name}
|
@item .arch @var{name}
|
Select the target architecture. Valid values for @var{name} are the same as
|
Select the target architecture. Valid values for @var{name} are the same as
|
for the @option{-march} commandline option.
|
for the @option{-march} commandline option.
|
|
|
@cindex @code{.object_arch} directive, ARM
|
@cindex @code{.object_arch} directive, ARM
|
@item .object_arch @var{name}
|
@item .object_arch @var{name}
|
Override the architecture recorded in the EABI object attribute section.
|
Override the architecture recorded in the EABI object attribute section.
|
Valid values for @var{name} are the same as for the @code{.arch} directive.
|
Valid values for @var{name} are the same as for the @code{.arch} directive.
|
Typically this is useful when code uses runtime detection of CPU features.
|
Typically this is useful when code uses runtime detection of CPU features.
|
|
|
@cindex @code{.fpu} directive, ARM
|
@cindex @code{.fpu} directive, ARM
|
@item .fpu @var{name}
|
@item .fpu @var{name}
|
Select the floating point unit to assemble for. Valid values for @var{name}
|
Select the floating point unit to assemble for. Valid values for @var{name}
|
are the same as for the @option{-mfpu} commandline option.
|
are the same as for the @option{-mfpu} commandline option.
|
|
|
@cindex @code{.eabi_attribute} directive, ARM
|
@cindex @code{.eabi_attribute} directive, ARM
|
@item .eabi_attribute @var{tag}, @var{value}
|
@item .eabi_attribute @var{tag}, @var{value}
|
Set the EABI object attribute number @var{tag} to @var{value}. The value
|
Set the EABI object attribute number @var{tag} to @var{value}. The value
|
is either a @code{number}, @code{"string"}, or @code{number, "string"}
|
is either a @code{number}, @code{"string"}, or @code{number, "string"}
|
depending on the tag.
|
depending on the tag.
|
|
|
@end table
|
@end table
|
|
|
@node ARM Opcodes
|
@node ARM Opcodes
|
@section Opcodes
|
@section Opcodes
|
|
|
@cindex ARM opcodes
|
@cindex ARM opcodes
|
@cindex opcodes for ARM
|
@cindex opcodes for ARM
|
@code{@value{AS}} implements all the standard ARM opcodes. It also
|
@code{@value{AS}} implements all the standard ARM opcodes. It also
|
implements several pseudo opcodes, including several synthetic load
|
implements several pseudo opcodes, including several synthetic load
|
instructions.
|
instructions.
|
|
|
@table @code
|
@table @code
|
|
|
@cindex @code{NOP} pseudo op, ARM
|
@cindex @code{NOP} pseudo op, ARM
|
@item NOP
|
@item NOP
|
@smallexample
|
@smallexample
|
nop
|
nop
|
@end smallexample
|
@end smallexample
|
|
|
This pseudo op will always evaluate to a legal ARM instruction that does
|
This pseudo op will always evaluate to a legal ARM instruction that does
|
nothing. Currently it will evaluate to MOV r0, r0.
|
nothing. Currently it will evaluate to MOV r0, r0.
|
|
|
@cindex @code{LDR reg,=<label>} pseudo op, ARM
|
@cindex @code{LDR reg,=<label>} pseudo op, ARM
|
@item LDR
|
@item LDR
|
@smallexample
|
@smallexample
|
ldr <register> , = <expression>
|
ldr <register> , = <expression>
|
@end smallexample
|
@end smallexample
|
|
|
If expression evaluates to a numeric constant then a MOV or MVN
|
If expression evaluates to a numeric constant then a MOV or MVN
|
instruction will be used in place of the LDR instruction, if the
|
instruction will be used in place of the LDR instruction, if the
|
constant can be generated by either of these instructions. Otherwise
|
constant can be generated by either of these instructions. Otherwise
|
the constant will be placed into the nearest literal pool (if it not
|
the constant will be placed into the nearest literal pool (if it not
|
already there) and a PC relative LDR instruction will be generated.
|
already there) and a PC relative LDR instruction will be generated.
|
|
|
@cindex @code{ADR reg,<label>} pseudo op, ARM
|
@cindex @code{ADR reg,<label>} pseudo op, ARM
|
@item ADR
|
@item ADR
|
@smallexample
|
@smallexample
|
adr <register> <label>
|
adr <register> <label>
|
@end smallexample
|
@end smallexample
|
|
|
This instruction will load the address of @var{label} into the indicated
|
This instruction will load the address of @var{label} into the indicated
|
register. The instruction will evaluate to a PC relative ADD or SUB
|
register. The instruction will evaluate to a PC relative ADD or SUB
|
instruction depending upon where the label is located. If the label is
|
instruction depending upon where the label is located. If the label is
|
out of range, or if it is not defined in the same file (and section) as
|
out of range, or if it is not defined in the same file (and section) as
|
the ADR instruction, then an error will be generated. This instruction
|
the ADR instruction, then an error will be generated. This instruction
|
will not make use of the literal pool.
|
will not make use of the literal pool.
|
|
|
@cindex @code{ADRL reg,<label>} pseudo op, ARM
|
@cindex @code{ADRL reg,<label>} pseudo op, ARM
|
@item ADRL
|
@item ADRL
|
@smallexample
|
@smallexample
|
adrl <register> <label>
|
adrl <register> <label>
|
@end smallexample
|
@end smallexample
|
|
|
This instruction will load the address of @var{label} into the indicated
|
This instruction will load the address of @var{label} into the indicated
|
register. The instruction will evaluate to one or two PC relative ADD
|
register. The instruction will evaluate to one or two PC relative ADD
|
or SUB instructions depending upon where the label is located. If a
|
or SUB instructions depending upon where the label is located. If a
|
second instruction is not needed a NOP instruction will be generated in
|
second instruction is not needed a NOP instruction will be generated in
|
its place, so that this instruction is always 8 bytes long.
|
its place, so that this instruction is always 8 bytes long.
|
|
|
If the label is out of range, or if it is not defined in the same file
|
If the label is out of range, or if it is not defined in the same file
|
(and section) as the ADRL instruction, then an error will be generated.
|
(and section) as the ADRL instruction, then an error will be generated.
|
This instruction will not make use of the literal pool.
|
This instruction will not make use of the literal pool.
|
|
|
@end table
|
@end table
|
|
|
For information on the ARM or Thumb instruction sets, see @cite{ARM
|
For information on the ARM or Thumb instruction sets, see @cite{ARM
|
Software Development Toolkit Reference Manual}, Advanced RISC Machines
|
Software Development Toolkit Reference Manual}, Advanced RISC Machines
|
Ltd.
|
Ltd.
|
|
|
@node ARM Mapping Symbols
|
@node ARM Mapping Symbols
|
@section Mapping Symbols
|
@section Mapping Symbols
|
|
|
The ARM ELF specification requires that special symbols be inserted
|
The ARM ELF specification requires that special symbols be inserted
|
into object files to mark certain features:
|
into object files to mark certain features:
|
|
|
@table @code
|
@table @code
|
|
|
@cindex @code{$a}
|
@cindex @code{$a}
|
@item $a
|
@item $a
|
At the start of a region of code containing ARM instructions.
|
At the start of a region of code containing ARM instructions.
|
|
|
@cindex @code{$t}
|
@cindex @code{$t}
|
@item $t
|
@item $t
|
At the start of a region of code containing THUMB instructions.
|
At the start of a region of code containing THUMB instructions.
|
|
|
@cindex @code{$d}
|
@cindex @code{$d}
|
@item $d
|
@item $d
|
At the start of a region of data.
|
At the start of a region of data.
|
|
|
@end table
|
@end table
|
|
|
The assembler will automatically insert these symbols for you - there
|
The assembler will automatically insert these symbols for you - there
|
is no need to code them yourself. Support for tagging symbols ($b,
|
is no need to code them yourself. Support for tagging symbols ($b,
|
$f, $p and $m) which is also mentioned in the current ARM ELF
|
$f, $p and $m) which is also mentioned in the current ARM ELF
|
specification is not implemented. This is because they have been
|
specification is not implemented. This is because they have been
|
dropped from the new EABI and so tools cannot rely upon their
|
dropped from the new EABI and so tools cannot rely upon their
|
presence.
|
presence.
|
|
|
|
|
