@c Copyright 1996, 2000, 2002 Free Software Foundation, Inc.
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@c Copyright 1996, 2000, 2002 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@ifset GENERIC
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@page
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@page
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@node D10V-Dependent
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@node D10V-Dependent
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@chapter D10V Dependent Features
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@chapter D10V Dependent Features
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@end ifset
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@end ifset
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@ifclear GENERIC
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@ifclear GENERIC
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@node Machine Dependencies
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@node Machine Dependencies
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@chapter D10V Dependent Features
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@chapter D10V Dependent Features
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@end ifclear
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@end ifclear
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@cindex D10V support
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@cindex D10V support
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@menu
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@menu
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* D10V-Opts:: D10V Options
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* D10V-Opts:: D10V Options
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* D10V-Syntax:: Syntax
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* D10V-Syntax:: Syntax
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* D10V-Float:: Floating Point
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* D10V-Float:: Floating Point
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* D10V-Opcodes:: Opcodes
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* D10V-Opcodes:: Opcodes
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@end menu
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@end menu
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@node D10V-Opts
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@node D10V-Opts
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@section D10V Options
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@section D10V Options
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@cindex options, D10V
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@cindex options, D10V
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@cindex D10V options
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@cindex D10V options
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The Mitsubishi D10V version of @code{@value{AS}} has a few machine
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The Mitsubishi D10V version of @code{@value{AS}} has a few machine
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dependent options.
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dependent options.
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@table @samp
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@table @samp
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@item -O
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@item -O
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The D10V can often execute two sub-instructions in parallel. When this option
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The D10V can often execute two sub-instructions in parallel. When this option
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is used, @code{@value{AS}} will attempt to optimize its output by detecting when
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is used, @code{@value{AS}} will attempt to optimize its output by detecting when
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instructions can be executed in parallel.
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instructions can be executed in parallel.
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@item --nowarnswap
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@item --nowarnswap
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To optimize execution performance, @code{@value{AS}} will sometimes swap the
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To optimize execution performance, @code{@value{AS}} will sometimes swap the
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order of instructions. Normally this generates a warning. When this option
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order of instructions. Normally this generates a warning. When this option
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is used, no warning will be generated when instructions are swapped.
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is used, no warning will be generated when instructions are swapped.
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@item --gstabs-packing
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@item --gstabs-packing
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@item --no-gstabs-packing
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@item --no-gstabs-packing
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@code{@value{AS}} packs adjacent short instructions into a single packed
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@code{@value{AS}} packs adjacent short instructions into a single packed
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instruction. @samp{--no-gstabs-packing} turns instruction packing off if
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instruction. @samp{--no-gstabs-packing} turns instruction packing off if
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@samp{--gstabs} is specified as well; @samp{--gstabs-packing} (the
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@samp{--gstabs} is specified as well; @samp{--gstabs-packing} (the
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default) turns instruction packing on even when @samp{--gstabs} is
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default) turns instruction packing on even when @samp{--gstabs} is
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specified.
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specified.
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@end table
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@end table
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@node D10V-Syntax
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@node D10V-Syntax
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@section Syntax
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@section Syntax
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@cindex D10V syntax
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@cindex D10V syntax
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@cindex syntax, D10V
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@cindex syntax, D10V
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The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual.
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The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual.
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The differences are detailed below.
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The differences are detailed below.
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@menu
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@menu
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* D10V-Size:: Size Modifiers
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* D10V-Size:: Size Modifiers
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* D10V-Subs:: Sub-Instructions
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* D10V-Subs:: Sub-Instructions
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* D10V-Chars:: Special Characters
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* D10V-Chars:: Special Characters
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* D10V-Regs:: Register Names
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* D10V-Regs:: Register Names
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* D10V-Addressing:: Addressing Modes
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* D10V-Addressing:: Addressing Modes
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* D10V-Word:: @@WORD Modifier
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* D10V-Word:: @@WORD Modifier
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@end menu
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@end menu
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@node D10V-Size
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@node D10V-Size
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@subsection Size Modifiers
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@subsection Size Modifiers
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@cindex D10V size modifiers
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@cindex D10V size modifiers
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@cindex size modifiers, D10V
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@cindex size modifiers, D10V
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The D10V version of @code{@value{AS}} uses the instruction names in the D10V
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The D10V version of @code{@value{AS}} uses the instruction names in the D10V
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Architecture Manual. However, the names in the manual are sometimes ambiguous.
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Architecture Manual. However, the names in the manual are sometimes ambiguous.
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There are instruction names that can assemble to a short or long form opcode.
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There are instruction names that can assemble to a short or long form opcode.
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How does the assembler pick the correct form? @code{@value{AS}} will always pick the
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How does the assembler pick the correct form? @code{@value{AS}} will always pick the
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smallest form if it can. When dealing with a symbol that is not defined yet when a
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smallest form if it can. When dealing with a symbol that is not defined yet when a
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line is being assembled, it will always use the long form. If you need to force the
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line is being assembled, it will always use the long form. If you need to force the
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assembler to use either the short or long form of the instruction, you can append
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assembler to use either the short or long form of the instruction, you can append
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either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
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either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
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an assembly program and you want to do a branch to a symbol that is defined later
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an assembly program and you want to do a branch to a symbol that is defined later
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in your program, you can write @samp{bra.s foo}.
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in your program, you can write @samp{bra.s foo}.
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Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
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Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
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have both short and long forms.
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have both short and long forms.
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@node D10V-Subs
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@node D10V-Subs
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@subsection Sub-Instructions
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@subsection Sub-Instructions
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@cindex D10V sub-instructions
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@cindex D10V sub-instructions
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@cindex sub-instructions, D10V
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@cindex sub-instructions, D10V
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The D10V assembler takes as input a series of instructions, either one-per-line,
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The D10V assembler takes as input a series of instructions, either one-per-line,
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or in the special two-per-line format described in the next section. Some of these
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or in the special two-per-line format described in the next section. Some of these
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instructions will be short-form or sub-instructions. These sub-instructions can be packed
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instructions will be short-form or sub-instructions. These sub-instructions can be packed
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into a single instruction. The assembler will do this automatically. It will also detect
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into a single instruction. The assembler will do this automatically. It will also detect
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when it should not pack instructions. For example, when a label is defined, the next
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when it should not pack instructions. For example, when a label is defined, the next
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instruction will never be packaged with the previous one. Whenever a branch and link
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instruction will never be packaged with the previous one. Whenever a branch and link
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instruction is called, it will not be packaged with the next instruction so the return
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instruction is called, it will not be packaged with the next instruction so the return
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address will be valid. Nops are automatically inserted when necessary.
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address will be valid. Nops are automatically inserted when necessary.
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If you do not want the assembler automatically making these decisions, you can control
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If you do not want the assembler automatically making these decisions, you can control
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the packaging and execution type (parallel or sequential) with the special execution
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the packaging and execution type (parallel or sequential) with the special execution
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symbols described in the next section.
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symbols described in the next section.
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@node D10V-Chars
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@node D10V-Chars
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@subsection Special Characters
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@subsection Special Characters
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@cindex line comment character, D10V
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@cindex line comment character, D10V
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@cindex D10V line comment character
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@cindex D10V line comment character
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@samp{;} and @samp{#} are the line comment characters.
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@samp{;} and @samp{#} are the line comment characters.
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@cindex sub-instruction ordering, D10V
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@cindex sub-instruction ordering, D10V
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@cindex D10V sub-instruction ordering
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@cindex D10V sub-instruction ordering
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Sub-instructions may be executed in order, in reverse-order, or in parallel.
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Sub-instructions may be executed in order, in reverse-order, or in parallel.
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Instructions listed in the standard one-per-line format will be executed sequentially.
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Instructions listed in the standard one-per-line format will be executed sequentially.
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To specify the executing order, use the following symbols:
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To specify the executing order, use the following symbols:
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@table @samp
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@table @samp
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@item ->
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@item ->
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Sequential with instruction on the left first.
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Sequential with instruction on the left first.
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@item <-
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@item <-
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Sequential with instruction on the right first.
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Sequential with instruction on the right first.
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@item ||
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@item ||
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Parallel
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Parallel
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@end table
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@end table
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The D10V syntax allows either one instruction per line, one instruction per line with
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The D10V syntax allows either one instruction per line, one instruction per line with
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the execution symbol, or two instructions per line. For example
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the execution symbol, or two instructions per line. For example
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@table @code
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@table @code
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@item abs a1 -> abs r0
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@item abs a1 -> abs r0
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Execute these sequentially. The instruction on the right is in the right
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Execute these sequentially. The instruction on the right is in the right
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container and is executed second.
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container and is executed second.
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@item abs r0 <- abs a1
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@item abs r0 <- abs a1
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Execute these reverse-sequentially. The instruction on the right is in the right
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Execute these reverse-sequentially. The instruction on the right is in the right
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container, and is executed first.
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container, and is executed first.
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@item ld2w r2,@@r8+ || mac a0,r0,r7
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@item ld2w r2,@@r8+ || mac a0,r0,r7
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Execute these in parallel.
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Execute these in parallel.
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@item ld2w r2,@@r8+ ||
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@item ld2w r2,@@r8+ ||
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@itemx mac a0,r0,r7
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@itemx mac a0,r0,r7
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Two-line format. Execute these in parallel.
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Two-line format. Execute these in parallel.
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@item ld2w r2,@@r8+
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@item ld2w r2,@@r8+
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@itemx mac a0,r0,r7
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@itemx mac a0,r0,r7
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Two-line format. Execute these sequentially. Assembler will
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Two-line format. Execute these sequentially. Assembler will
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put them in the proper containers.
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put them in the proper containers.
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@item ld2w r2,@@r8+ ->
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@item ld2w r2,@@r8+ ->
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@itemx mac a0,r0,r7
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@itemx mac a0,r0,r7
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Two-line format. Execute these sequentially. Same as above but
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Two-line format. Execute these sequentially. Same as above but
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second instruction will always go into right container.
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second instruction will always go into right container.
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@end table
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@end table
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@cindex symbol names, @samp{$} in
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@cindex symbol names, @samp{$} in
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@cindex @code{$} in symbol names
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@cindex @code{$} in symbol names
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Since @samp{$} has no special meaning, you may use it in symbol names.
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Since @samp{$} has no special meaning, you may use it in symbol names.
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@node D10V-Regs
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@node D10V-Regs
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@subsection Register Names
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@subsection Register Names
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@cindex D10V registers
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@cindex D10V registers
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@cindex registers, D10V
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@cindex registers, D10V
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You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V
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You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V
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registers. You can also use @samp{sp} as an alias for @samp{r15}. The accumulators
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registers. You can also use @samp{sp} as an alias for @samp{r15}. The accumulators
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are @samp{a0} and @samp{a1}. There are special register-pair names that may
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are @samp{a0} and @samp{a1}. There are special register-pair names that may
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optionally be used in opcodes that require even-numbered registers. Register names are
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optionally be used in opcodes that require even-numbered registers. Register names are
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not case sensitive.
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not case sensitive.
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Register Pairs
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Register Pairs
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@table @code
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@table @code
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@item r0-r1
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@item r0-r1
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@item r2-r3
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@item r2-r3
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@item r4-r5
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@item r4-r5
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@item r6-r7
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@item r6-r7
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@item r8-r9
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@item r8-r9
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@item r10-r11
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@item r10-r11
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@item r12-r13
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@item r12-r13
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@item r14-r15
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@item r14-r15
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@end table
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@end table
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The D10V also has predefined symbols for these control registers and status bits:
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The D10V also has predefined symbols for these control registers and status bits:
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@table @code
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@table @code
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@item psw
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@item psw
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Processor Status Word
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Processor Status Word
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@item bpsw
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@item bpsw
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Backup Processor Status Word
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Backup Processor Status Word
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@item pc
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@item pc
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Program Counter
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Program Counter
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@item bpc
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@item bpc
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Backup Program Counter
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Backup Program Counter
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@item rpt_c
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@item rpt_c
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Repeat Count
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Repeat Count
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@item rpt_s
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@item rpt_s
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Repeat Start address
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Repeat Start address
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@item rpt_e
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@item rpt_e
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Repeat End address
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Repeat End address
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@item mod_s
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@item mod_s
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Modulo Start address
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Modulo Start address
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@item mod_e
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@item mod_e
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Modulo End address
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Modulo End address
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@item iba
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@item iba
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Instruction Break Address
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Instruction Break Address
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@item f0
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@item f0
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Flag 0
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Flag 0
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@item f1
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@item f1
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Flag 1
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Flag 1
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@item c
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@item c
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Carry flag
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Carry flag
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@end table
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@end table
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@node D10V-Addressing
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@node D10V-Addressing
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@subsection Addressing Modes
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@subsection Addressing Modes
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@cindex addressing modes, D10V
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@cindex addressing modes, D10V
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@cindex D10V addressing modes
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@cindex D10V addressing modes
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@code{@value{AS}} understands the following addressing modes for the D10V.
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@code{@value{AS}} understands the following addressing modes for the D10V.
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@code{R@var{n}} in the following refers to any of the numbered
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@code{R@var{n}} in the following refers to any of the numbered
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registers, but @emph{not} the control registers.
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registers, but @emph{not} the control registers.
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@table @code
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@table @code
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@item R@var{n}
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@item R@var{n}
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Register direct
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Register direct
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@item @@R@var{n}
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@item @@R@var{n}
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Register indirect
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Register indirect
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@item @@R@var{n}+
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@item @@R@var{n}+
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Register indirect with post-increment
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Register indirect with post-increment
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@item @@R@var{n}-
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@item @@R@var{n}-
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Register indirect with post-decrement
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Register indirect with post-decrement
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@item @@-SP
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@item @@-SP
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Register indirect with pre-decrement
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Register indirect with pre-decrement
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@item @@(@var{disp}, R@var{n})
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@item @@(@var{disp}, R@var{n})
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Register indirect with displacement
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Register indirect with displacement
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@item @var{addr}
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@item @var{addr}
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PC relative address (for branch or rep).
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PC relative address (for branch or rep).
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@item #@var{imm}
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@item #@var{imm}
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Immediate data (the @samp{#} is optional and ignored)
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Immediate data (the @samp{#} is optional and ignored)
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@end table
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@end table
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@node D10V-Word
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@node D10V-Word
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@subsection @@WORD Modifier
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@subsection @@WORD Modifier
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@cindex D10V @@word modifier
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@cindex D10V @@word modifier
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@cindex @@word modifier, D10V
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@cindex @@word modifier, D10V
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Any symbol followed by @code{@@word} will be replaced by the symbol's value
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Any symbol followed by @code{@@word} will be replaced by the symbol's value
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shifted right by 2. This is used in situations such as loading a register
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shifted right by 2. This is used in situations such as loading a register
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with the address of a function (or any other code fragment). For example, if
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with the address of a function (or any other code fragment). For example, if
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you want to load a register with the location of the function @code{main} then
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you want to load a register with the location of the function @code{main} then
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jump to that function, you could do it as follows:
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jump to that function, you could do it as follows:
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@smallexample
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@smallexample
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@group
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@group
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ldi r2, main@@word
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ldi r2, main@@word
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jmp r2
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jmp r2
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@end group
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@end group
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@end smallexample
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@end smallexample
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@node D10V-Float
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@node D10V-Float
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@section Floating Point
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@section Floating Point
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@cindex floating point, D10V
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@cindex floating point, D10V
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@cindex D10V floating point
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@cindex D10V floating point
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The D10V has no hardware floating point, but the @code{.float} and @code{.double}
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The D10V has no hardware floating point, but the @code{.float} and @code{.double}
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directives generates @sc{ieee} floating-point numbers for compatibility
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directives generates @sc{ieee} floating-point numbers for compatibility
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with other development tools.
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with other development tools.
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@node D10V-Opcodes
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@node D10V-Opcodes
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@section Opcodes
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@section Opcodes
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@cindex D10V opcode summary
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@cindex D10V opcode summary
|
@cindex opcode summary, D10V
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@cindex opcode summary, D10V
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@cindex mnemonics, D10V
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@cindex mnemonics, D10V
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@cindex instruction summary, D10V
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@cindex instruction summary, D10V
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For detailed information on the D10V machine instruction set, see
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For detailed information on the D10V machine instruction set, see
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@cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications}
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@cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications}
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(Mitsubishi Electric Corp.).
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(Mitsubishi Electric Corp.).
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@code{@value{AS}} implements all the standard D10V opcodes. The only changes are those
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@code{@value{AS}} implements all the standard D10V opcodes. The only changes are those
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described in the section on size modifiers
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described in the section on size modifiers
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