@c Copyright 2000, 2003 Free Software Foundation, Inc.
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@c Copyright 2000, 2003 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@ifset GENERIC
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@page
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@page
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@node i860-Dependent
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@node i860-Dependent
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@chapter Intel i860 Dependent Features
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@chapter Intel i860 Dependent Features
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@end ifset
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@end ifset
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@ifclear GENERIC
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@ifclear GENERIC
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@node Machine Dependencies
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@node Machine Dependencies
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@chapter Intel i860 Dependent Features
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@chapter Intel i860 Dependent Features
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@end ifclear
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@end ifclear
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@ignore
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@ignore
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@c FIXME: This is basically a stub for i860. There is tons more information
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@c FIXME: This is basically a stub for i860. There is tons more information
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that I will add later (jle@cygnus.com).
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that I will add later (jle@cygnus.com).
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@end ignore
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@end ignore
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@cindex i860 support
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@cindex i860 support
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@menu
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@menu
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* Notes-i860:: i860 Notes
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* Notes-i860:: i860 Notes
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* Options-i860:: i860 Command-line Options
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* Options-i860:: i860 Command-line Options
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* Directives-i860:: i860 Machine Directives
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* Directives-i860:: i860 Machine Directives
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* Opcodes for i860:: i860 Opcodes
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* Opcodes for i860:: i860 Opcodes
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@end menu
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@end menu
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@node Notes-i860
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@node Notes-i860
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@section i860 Notes
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@section i860 Notes
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This is a fairly complete i860 assembler which is compatible with the
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This is a fairly complete i860 assembler which is compatible with the
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UNIX System V/860 Release 4 assembler. However, it does not currently
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UNIX System V/860 Release 4 assembler. However, it does not currently
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support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}).
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support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}).
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Like the SVR4/860 assembler, the output object format is ELF32. Currently,
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Like the SVR4/860 assembler, the output object format is ELF32. Currently,
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this is the only supported object format. If there is sufficient interest,
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this is the only supported object format. If there is sufficient interest,
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other formats such as COFF may be implemented.
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other formats such as COFF may be implemented.
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Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
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Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
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being the default. One difference is that AT&T syntax requires the '%'
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being the default. One difference is that AT&T syntax requires the '%'
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prefix on register names while Intel syntax does not. Another difference
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prefix on register names while Intel syntax does not. Another difference
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is in the specification of relocatable expressions. The Intel syntax
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is in the specification of relocatable expressions. The Intel syntax
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is @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha}
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is @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha}
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(and similarly for the "l" and "h" selectors).
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(and similarly for the "l" and "h" selectors).
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@node Options-i860
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@node Options-i860
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@section i860 Command-line Options
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@section i860 Command-line Options
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@subsection SVR4 compatibility options
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@subsection SVR4 compatibility options
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@table @code
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@table @code
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@item -V
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@item -V
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Print assembler version.
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Print assembler version.
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@item -Qy
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@item -Qy
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Ignored.
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Ignored.
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@item -Qn
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@item -Qn
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Ignored.
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Ignored.
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@end table
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@end table
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@subsection Other options
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@subsection Other options
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@table @code
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@table @code
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@item -EL
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@item -EL
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Select little endian output (this is the default).
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Select little endian output (this is the default).
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@item -EB
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@item -EB
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Select big endian output. Note that the i860 always reads instructions
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Select big endian output. Note that the i860 always reads instructions
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as little endian data, so this option only effects data and not
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as little endian data, so this option only effects data and not
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instructions.
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instructions.
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@item -mwarn-expand
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@item -mwarn-expand
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Emit a warning message if any pseudo-instruction expansions occurred.
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Emit a warning message if any pseudo-instruction expansions occurred.
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For example, a @code{or} instruction with an immediate larger than 16-bits
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For example, a @code{or} instruction with an immediate larger than 16-bits
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will be expanded into two instructions. This is a very undesirable feature to
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will be expanded into two instructions. This is a very undesirable feature to
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rely on, so this flag can help detect any code where it happens. One
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rely on, so this flag can help detect any code where it happens. One
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use of it, for instance, has been to find and eliminate any place
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use of it, for instance, has been to find and eliminate any place
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where @code{gcc} may emit these pseudo-instructions.
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where @code{gcc} may emit these pseudo-instructions.
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@item -mxp
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@item -mxp
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Enable support for the i860XP instructions and control registers. By default,
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Enable support for the i860XP instructions and control registers. By default,
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this option is disabled so that only the base instruction set (i.e., i860XR)
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this option is disabled so that only the base instruction set (i.e., i860XR)
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is supported.
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is supported.
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@item -mintel-syntax
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@item -mintel-syntax
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The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the
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The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the
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Intel syntax.
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Intel syntax.
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@end table
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@end table
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@node Directives-i860
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@node Directives-i860
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@section i860 Machine Directives
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@section i860 Machine Directives
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@cindex machine directives, i860
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@cindex machine directives, i860
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@cindex i860 machine directives
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@cindex i860 machine directives
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@table @code
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@table @code
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@cindex @code{dual} directive, i860
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@cindex @code{dual} directive, i860
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@item .dual
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@item .dual
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Enter dual instruction mode. While this directive is supported, the
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Enter dual instruction mode. While this directive is supported, the
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preferred way to use dual instruction mode is to explicitly code
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preferred way to use dual instruction mode is to explicitly code
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the dual bit with the @code{d.} prefix.
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the dual bit with the @code{d.} prefix.
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@end table
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@end table
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@table @code
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@table @code
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@cindex @code{enddual} directive, i860
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@cindex @code{enddual} directive, i860
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@item .enddual
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@item .enddual
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Exit dual instruction mode. While this directive is supported, the
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Exit dual instruction mode. While this directive is supported, the
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preferred way to use dual instruction mode is to explicitly code
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preferred way to use dual instruction mode is to explicitly code
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the dual bit with the @code{d.} prefix.
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the dual bit with the @code{d.} prefix.
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@end table
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@end table
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@table @code
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@table @code
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@cindex @code{atmp} directive, i860
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@cindex @code{atmp} directive, i860
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@item .atmp
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@item .atmp
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Change the temporary register used when expanding pseudo operations. The
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Change the temporary register used when expanding pseudo operations. The
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default register is @code{r31}.
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default register is @code{r31}.
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@end table
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@end table
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The @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode.
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The @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode.
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Both syntaxes allow for the standard @code{.align} directive. However,
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Both syntaxes allow for the standard @code{.align} directive. However,
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the Intel syntax additionally allows keywords for the alignment
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the Intel syntax additionally allows keywords for the alignment
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parameter: "@code{.align type}", where `type' is one of @code{.short}, @code{.long},
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parameter: "@code{.align type}", where `type' is one of @code{.short}, @code{.long},
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@code{.quad}, @code{.single}, @code{.double} representing alignments of 2, 4,
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@code{.quad}, @code{.single}, @code{.double} representing alignments of 2, 4,
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16, 4, and 8, respectively.
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16, 4, and 8, respectively.
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@node Opcodes for i860
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@node Opcodes for i860
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@section i860 Opcodes
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@section i860 Opcodes
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@cindex opcodes, i860
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@cindex opcodes, i860
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@cindex i860 opcodes
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@cindex i860 opcodes
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All of the Intel i860XR and i860XP machine instructions are supported. Please see
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All of the Intel i860XR and i860XP machine instructions are supported. Please see
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either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information.
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either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information.
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@subsection Other instruction support (pseudo-instructions)
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@subsection Other instruction support (pseudo-instructions)
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For compatibility with some other i860 assemblers, a number of
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For compatibility with some other i860 assemblers, a number of
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pseudo-instructions are supported. While these are supported, they are
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pseudo-instructions are supported. While these are supported, they are
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a very undesirable feature that should be avoided -- in particular, when
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a very undesirable feature that should be avoided -- in particular, when
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they result in an expansion to multiple actual i860 instructions. Below
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they result in an expansion to multiple actual i860 instructions. Below
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are the pseudo-instructions that result in expansions.
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are the pseudo-instructions that result in expansions.
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@itemize @bullet
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@itemize @bullet
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@item Load large immediate into general register:
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@item Load large immediate into general register:
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The pseudo-instruction @code{mov imm,%rn} (where the immediate does
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The pseudo-instruction @code{mov imm,%rn} (where the immediate does
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not fit within a signed 16-bit field) will be expanded into:
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not fit within a signed 16-bit field) will be expanded into:
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@smallexample
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@smallexample
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orh large_imm@@h,%r0,%rn
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orh large_imm@@h,%r0,%rn
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or large_imm@@l,%rn,%rn
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or large_imm@@l,%rn,%rn
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@end smallexample
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@end smallexample
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@item Load/store with relocatable address expression:
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@item Load/store with relocatable address expression:
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For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn}
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For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn}
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will be expanded into:
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will be expanded into:
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@smallexample
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@smallexample
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orh addr_exp@@ha,%rx,%r31
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orh addr_exp@@ha,%rx,%r31
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ld.l addr_exp@@l(%r31),%rn
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ld.l addr_exp@@l(%r31),%rn
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@end smallexample
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@end smallexample
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The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well.
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The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well.
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@item Signed large immediate with add/subtract:
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@item Signed large immediate with add/subtract:
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If any of the arithmetic operations @code{adds, addu, subs, subu} are used
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If any of the arithmetic operations @code{adds, addu, subs, subu} are used
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with an immediate larger than 16-bits (signed), then they will be expanded.
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with an immediate larger than 16-bits (signed), then they will be expanded.
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For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
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For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
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@smallexample
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@smallexample
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orh large_imm@@h,%r0,%r31
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orh large_imm@@h,%r0,%r31
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or large_imm@@l,%r31,%r31
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or large_imm@@l,%r31,%r31
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adds %r31,%rx,%rn
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adds %r31,%rx,%rn
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@end smallexample
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@end smallexample
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@item Unsigned large immediate with logical operations:
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@item Unsigned large immediate with logical operations:
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Logical operations (@code{or, andnot, or, xor}) also result in expansions.
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Logical operations (@code{or, andnot, or, xor}) also result in expansions.
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The pseudo-instruction @code{or large_imm,%rx,%rn} results in:
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The pseudo-instruction @code{or large_imm,%rx,%rn} results in:
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@smallexample
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@smallexample
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orh large_imm@@h,%rx,%r31
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orh large_imm@@h,%rx,%r31
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or large_imm@@l,%r31,%rn
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or large_imm@@l,%r31,%rn
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@end smallexample
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@end smallexample
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Similarly for the others, except for @code{and} which expands to:
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Similarly for the others, except for @code{and} which expands to:
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@smallexample
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@smallexample
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andnot (-1 - large_imm)@@h,%rx,%r31
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andnot (-1 - large_imm)@@h,%rx,%r31
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andnot (-1 - large_imm)@@l,%r31,%rn
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andnot (-1 - large_imm)@@l,%r31,%rn
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@end smallexample
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@end smallexample
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@end itemize
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@end itemize
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