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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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| Rev 156 |
Rev 816 |
#as:
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#as:
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#objdump: -dr
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#objdump: -dr
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#name: shift_insn
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#name: shift_insn
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.*: +file format .*
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.*: +file format .*
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Disassembly of section .text:
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Disassembly of section .text:
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00000000 :
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00000000 :
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0: 71 fc sllb \$0x7, r1
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0: 71 fc sllb \$0x7, r1
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2: 23 4d sllb r2, r3
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2: 23 4d sllb r2, r3
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00000004 :
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00000004 :
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4: d4 fc srlb \$0x5, r4
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4: d4 fc srlb \$0x5, r4
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6: 56 4e srlb r5, r6
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6: 56 4e srlb r5, r6
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00000008 :
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00000008 :
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8: 47 fd srab \$0x4, r7
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8: 47 fd srab \$0x4, r7
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a: 89 4f srab r8, r9
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a: 89 4f srab r8, r9
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0000000c :
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0000000c :
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c: fa b6 sllw \$0xf, r10
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c: fa b6 sllw \$0xf, r10
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e: bc 5d sllw r11, r12
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e: bc 5d sllw r11, r12
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00000010 :
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00000010 :
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10: ed b7 srlw \$0xe, r13
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10: ed b7 srlw \$0xe, r13
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12: ef 5e srlw r14, r15
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12: ef 5e srlw r14, r15
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00000014 :
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00000014 :
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14: de b8 sraw \$0xd, r14
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14: de b8 sraw \$0xd, r14
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16: f1 5f sraw r15, r1
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16: f1 5f sraw r15, r1
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00000018 :
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00000018 :
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18: f2 f1 slld \$0x1f, r2
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18: f2 f1 slld \$0x1f, r2
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1a: 34 6d slld r3, r4
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1a: 34 6d slld r3, r4
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0000001c :
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0000001c :
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1c: f5 f3 srld \$0x1f, r5
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1c: f5 f3 srld \$0x1f, r5
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1e: 67 6e srld r6, r7
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1e: 67 6e srld r6, r7
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00000020 :
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00000020 :
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20: 28 f5 srad \$0x12, r8
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20: 28 f5 srad \$0x12, r8
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22: 9a 6f srad r9, r10
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22: 9a 6f srad r9, r10
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