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| Rev 156 |
Rev 816 |
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#
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#
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# Try to verify all operand modes for 68HC12
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# Try to verify all operand modes for 68HC12
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#
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#
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sect .text
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sect .text
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globl start
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globl start
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start:
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start:
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anda [12,x] ; Indexed indirect
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anda [12,x] ; Indexed indirect
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ldaa #10
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ldaa #10
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ldx L1
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ldx L1
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L1: ldy ,x
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L1: ldy ,x
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addd 1,y ; Offset from register
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addd 1,y ; Offset from register
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subd -1,y
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subd -1,y
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eora 15,y
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eora 15,y
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eora -16,y
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eora -16,y
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eorb 16,y
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eorb 16,y
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eorb -17,y
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eorb -17,y
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oraa 128,sp
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oraa 128,sp
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orab -128,sp
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orab -128,sp
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orab 255,x
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orab 255,x
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orab -256,x
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orab -256,x
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anda 256,x
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anda 256,x
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andb -257,x
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andb -257,x
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anda [12,x] ; Indexed indirect (16-bit offset)
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anda [12,x] ; Indexed indirect (16-bit offset)
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ldaa [257,y]
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ldaa [257,y]
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ldab [32767,sp]
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ldab [32767,sp]
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ldd [32768,pc]
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ldd [32768,pc]
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ldd L1,pc
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ldd L1,pc
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std a,x ; Two-reg index
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std a,x ; Two-reg index
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ldx b,x
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ldx b,x
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stx d,y
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stx d,y
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addd 1,+x ; Pre-Auto inc
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addd 1,+x ; Pre-Auto inc
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addd 2,+x
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addd 2,+x
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addd 8,+x
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addd 8,+x
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addd 1,sp+ ; Post-Auto inc
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addd 1,sp+ ; Post-Auto inc
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addd 2,sp+
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addd 2,sp+
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addd 8,sp+
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addd 8,sp+
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subd 1,-y ; Pre-Auto dec
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subd 1,-y ; Pre-Auto dec
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subd 2,-y
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subd 2,-y
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subd 8,-y
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subd 8,-y
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addd 1,y- ; Post-Auto dec
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addd 1,y- ; Post-Auto dec
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addd 2,y-
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addd 2,y-
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addd 8,y-
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addd 8,y-
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std [d,x] ; Indexed indirect with two reg index
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std [d,x] ; Indexed indirect with two reg index
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std [d,y]
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std [d,y]
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std [d,sp]
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std [d,sp]
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std [d,pc]
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std [d,pc]
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beq L1
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beq L1
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lbeq start
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lbeq start
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lbcc L2
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lbcc L2
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;;
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;;
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;; Move insn with various operands
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;; Move insn with various operands
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;;
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;;
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movb start, 1,x
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movb start, 1,x
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movw 1,x, start
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movw 1,x, start
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movb start, 1,+x
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movb start, 1,+x
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movb start, 1,-x
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movb start, 1,-x
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movb #23, 1,-sp
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movb #23, 1,-sp
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movb L1, L2
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movb L1, L2
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movb L1, a,x
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movb L1, a,x
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movw L1, b,x
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movw L1, b,x
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movw L1, d,x
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movw L1, d,x
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movw d,x, a,x
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movw d,x, a,x
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movw b,sp, d,pc
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movw b,sp, d,pc
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movw b,sp, L1
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movw b,sp, L1
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movw b,sp, 1,x
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movw b,sp, 1,x
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movw d,x, a,y
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movw d,x, a,y
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trap #0x30
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trap #0x30
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trap #0x39
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trap #0x39
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trap #0x40
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trap #0x40
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trap #0x80
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trap #0x80
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trap #255
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trap #255
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L2:
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L2:
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movw 1,x,2,x
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movw 1,x,2,x
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movw -1,-1
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movw -1,-1
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movw -1,1,x
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movw -1,1,x
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movw #-1,1,x
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movw #-1,1,x
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movw 3,8
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movw 3,8
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movw #3,3
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movw #3,3
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movw #3,1,x
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movw #3,1,x
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movw 3,1,x
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movw 3,1,x
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movw 3,+2,x
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movw 3,+2,x
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movw 4,-2,x
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movw 4,-2,x
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rts
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rts
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;;
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;;
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;; Post-index byte with relocation
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;; Post-index byte with relocation
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;;
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;;
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post_indexed_pb:
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post_indexed_pb:
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t1:
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t1:
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leas abort,x
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leas abort,x
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t2:
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t2:
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leax t2-t1,y
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leax t2-t1,y
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leax toto,x
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leax toto,x
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leas toto+titi,sp
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leas toto+titi,sp
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leay titi,x
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leay titi,x
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leas bb,y
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leas bb,y
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leas min5b,pc
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leas min5b,pc
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leas max5b,pc
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leas max5b,pc
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leas min9b,pc
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leas min9b,pc
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leas max9b,pc
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leas max9b,pc
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;;
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;;
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;; Disassembler bug with movb
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;; Disassembler bug with movb
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;;
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;;
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movb #23,0x2345
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movb #23,0x2345
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movb #40,12,sp
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movb #40,12,sp
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movb #39,3,+sp
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movb #39,3,+sp
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movb #20,14,sp
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movb #20,14,sp
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movw #0x3210,0x3456
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movw #0x3210,0x3456
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movw #0x4040,12,sp
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movw #0x4040,12,sp
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movw #0x3900,3,+sp
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movw #0x3900,3,+sp
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movw #0x2000,14,sp
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movw #0x2000,14,sp
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# movb #111,start
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# movb #111,start
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titi = 10
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titi = 10
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toto = 100
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toto = 100
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min5b= -16
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min5b= -16
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max5b= 15
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max5b= 15
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min9b= -256
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min9b= -256
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max9b= 255
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max9b= 255
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bb = 10240
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bb = 10240
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