# Source file to test assembly of SB-1 MDMX subset instructions and extensions.
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# Source file to test assembly of SB-1 MDMX subset instructions and extensions.
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#
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#
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# SB-1 implements only the .ob MDMX instructions, and adds three additional
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# SB-1 implements only the .ob MDMX instructions, and adds three additional
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# MDMX-ish instructions (pabsdiff, pabsdiffc, pavg).
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# MDMX-ish instructions (pabsdiff, pabsdiffc, pavg).
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.set noreorder
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.set noreorder
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.set noat
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.set noat
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.globl text_label .text
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.globl text_label .text
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text_label:
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text_label:
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# The normal MDMX instructions:
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# The normal MDMX instructions:
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movf.l $v1, $v12, $fcc5
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movf.l $v1, $v12, $fcc5
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movn.l $v1, $v12, $18
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movn.l $v1, $v12, $18
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movt.l $v1, $v12, $fcc5
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movt.l $v1, $v12, $fcc5
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movz.l $v1, $v12, $18
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movz.l $v1, $v12, $18
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add.ob $v1, $v12, 18
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add.ob $v1, $v12, 18
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add.ob $v1, $v12, $v18
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add.ob $v1, $v12, $v18
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add.ob $v1, $v12, $v18[6]
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add.ob $v1, $v12, $v18[6]
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adda.ob $v12, 18
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adda.ob $v12, 18
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adda.ob $v12, $v18
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adda.ob $v12, $v18
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adda.ob $v12, $v18[6]
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adda.ob $v12, $v18[6]
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addl.ob $v12, 18
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addl.ob $v12, 18
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addl.ob $v12, $v18
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addl.ob $v12, $v18
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addl.ob $v12, $v18[6]
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addl.ob $v12, $v18[6]
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alni.ob $v1, $v12, $v18, 6
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alni.ob $v1, $v12, $v18, 6
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alnv.ob $v1, $v12, $v18, $21
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alnv.ob $v1, $v12, $v18, $21
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and.ob $v1, $v12, 18
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and.ob $v1, $v12, 18
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and.ob $v1, $v12, $v18
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and.ob $v1, $v12, $v18
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and.ob $v1, $v12, $v18[6]
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and.ob $v1, $v12, $v18[6]
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c.eq.ob $v12, 18
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c.eq.ob $v12, 18
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c.eq.ob $v12, $v18
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c.eq.ob $v12, $v18
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c.eq.ob $v12, $v18[6]
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c.eq.ob $v12, $v18[6]
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c.le.ob $v12, 18
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c.le.ob $v12, 18
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c.le.ob $v12, $v18
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c.le.ob $v12, $v18
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c.le.ob $v12, $v18[6]
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c.le.ob $v12, $v18[6]
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c.lt.ob $v12, 18
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c.lt.ob $v12, 18
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c.lt.ob $v12, $v18
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c.lt.ob $v12, $v18
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c.lt.ob $v12, $v18[6]
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c.lt.ob $v12, $v18[6]
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max.ob $v1, $v12, 18
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max.ob $v1, $v12, 18
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max.ob $v1, $v12, $v18
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max.ob $v1, $v12, $v18
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max.ob $v1, $v12, $v18[6]
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max.ob $v1, $v12, $v18[6]
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min.ob $v1, $v12, 18
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min.ob $v1, $v12, 18
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min.ob $v1, $v12, $v18
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min.ob $v1, $v12, $v18
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min.ob $v1, $v12, $v18[6]
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min.ob $v1, $v12, $v18[6]
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mul.ob $v1, $v12, 18
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mul.ob $v1, $v12, 18
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mul.ob $v1, $v12, $v18
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mul.ob $v1, $v12, $v18
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mul.ob $v1, $v12, $v18[6]
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mul.ob $v1, $v12, $v18[6]
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mula.ob $v12, 18
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mula.ob $v12, 18
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mula.ob $v12, $v18
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mula.ob $v12, $v18
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mula.ob $v12, $v18[6]
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mula.ob $v12, $v18[6]
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mull.ob $v12, 18
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mull.ob $v12, 18
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mull.ob $v12, $v18
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mull.ob $v12, $v18
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mull.ob $v12, $v18[6]
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mull.ob $v12, $v18[6]
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muls.ob $v12, 18
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muls.ob $v12, 18
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muls.ob $v12, $v18
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muls.ob $v12, $v18
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muls.ob $v12, $v18[6]
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muls.ob $v12, $v18[6]
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mulsl.ob $v12, 18
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mulsl.ob $v12, 18
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mulsl.ob $v12, $v18
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mulsl.ob $v12, $v18
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mulsl.ob $v12, $v18[6]
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mulsl.ob $v12, $v18[6]
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nor.ob $v1, $v12, 18
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nor.ob $v1, $v12, 18
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nor.ob $v1, $v12, $v18
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nor.ob $v1, $v12, $v18
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nor.ob $v1, $v12, $v18[6]
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nor.ob $v1, $v12, $v18[6]
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or.ob $v1, $v12, 18
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or.ob $v1, $v12, 18
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or.ob $v1, $v12, $v18
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or.ob $v1, $v12, $v18
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or.ob $v1, $v12, $v18[6]
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or.ob $v1, $v12, $v18[6]
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pickf.ob $v1, $v12, 18
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pickf.ob $v1, $v12, 18
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pickf.ob $v1, $v12, $v18
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pickf.ob $v1, $v12, $v18
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pickf.ob $v1, $v12, $v18[6]
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pickf.ob $v1, $v12, $v18[6]
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pickt.ob $v1, $v12, 18
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pickt.ob $v1, $v12, 18
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pickt.ob $v1, $v12, $v18
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pickt.ob $v1, $v12, $v18
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pickt.ob $v1, $v12, $v18[6]
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pickt.ob $v1, $v12, $v18[6]
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rach.ob $v1
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rach.ob $v1
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racl.ob $v1
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racl.ob $v1
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racm.ob $v1
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racm.ob $v1
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rnau.ob $v1, 18
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rnau.ob $v1, 18
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rnau.ob $v1, $v18
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rnau.ob $v1, $v18
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rnau.ob $v1, $v18[6]
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rnau.ob $v1, $v18[6]
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rneu.ob $v1, 18
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rneu.ob $v1, 18
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rneu.ob $v1, $v18
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rneu.ob $v1, $v18
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rneu.ob $v1, $v18[6]
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rneu.ob $v1, $v18[6]
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rzu.ob $v1, 18
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rzu.ob $v1, 18
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rzu.ob $v1, $v18
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rzu.ob $v1, $v18
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rzu.ob $v1, $v18[6]
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rzu.ob $v1, $v18[6]
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shfl.mixh.ob $v1, $v12, $v18
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shfl.mixh.ob $v1, $v12, $v18
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shfl.mixl.ob $v1, $v12, $v18
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shfl.mixl.ob $v1, $v12, $v18
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shfl.pach.ob $v1, $v12, $v18
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shfl.pach.ob $v1, $v12, $v18
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shfl.upsl.ob $v1, $v12, $v18
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shfl.upsl.ob $v1, $v12, $v18
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sll.ob $v1, $v12, 18
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sll.ob $v1, $v12, 18
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sll.ob $v1, $v12, $v18
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sll.ob $v1, $v12, $v18
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sll.ob $v1, $v12, $v18[6]
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sll.ob $v1, $v12, $v18[6]
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srl.ob $v1, $v12, 18
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srl.ob $v1, $v12, 18
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srl.ob $v1, $v12, $v18
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srl.ob $v1, $v12, $v18
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srl.ob $v1, $v12, $v18[6]
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srl.ob $v1, $v12, $v18[6]
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sub.ob $v1, $v12, 18
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sub.ob $v1, $v12, 18
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sub.ob $v1, $v12, $v18
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sub.ob $v1, $v12, $v18
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sub.ob $v1, $v12, $v18[6]
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sub.ob $v1, $v12, $v18[6]
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suba.ob $v12, 18
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suba.ob $v12, 18
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suba.ob $v12, $v18
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suba.ob $v12, $v18
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suba.ob $v12, $v18[6]
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suba.ob $v12, $v18[6]
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subl.ob $v12, 18
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subl.ob $v12, 18
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subl.ob $v12, $v18
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subl.ob $v12, $v18
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subl.ob $v12, $v18[6]
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subl.ob $v12, $v18[6]
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wach.ob $v12
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wach.ob $v12
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wacl.ob $v12, $v18
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wacl.ob $v12, $v18
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xor.ob $v1, $v12, 18
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xor.ob $v1, $v12, 18
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xor.ob $v1, $v12, $v18
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xor.ob $v1, $v12, $v18
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xor.ob $v1, $v12, $v18[6]
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xor.ob $v1, $v12, $v18[6]
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# The extensions:
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# The extensions:
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pabsdiff.ob $v1, $v12, 18
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pabsdiff.ob $v1, $v12, 18
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pabsdiff.ob $v1, $v12, $v18
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pabsdiff.ob $v1, $v12, $v18
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pabsdiff.ob $v1, $v12, $v18[6]
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pabsdiff.ob $v1, $v12, $v18[6]
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pabsdiffc.ob $v12, 18
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pabsdiffc.ob $v12, 18
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pabsdiffc.ob $v12, $v18
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pabsdiffc.ob $v12, $v18
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pabsdiffc.ob $v12, $v18[6]
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pabsdiffc.ob $v12, $v18[6]
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pavg.ob $v1, $v12, 18
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pavg.ob $v1, $v12, 18
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pavg.ob $v1, $v12, $v18
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pavg.ob $v1, $v12, $v18
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pavg.ob $v1, $v12, $v18[6]
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pavg.ob $v1, $v12, $v18[6]
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.space 8
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.space 8
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