/* SPU opcode list
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/* SPU opcode list
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Copyright 2006, 2007 Free Software Foundation, Inc.
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Copyright 2006, 2007 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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MA 02110-1301, USA. */
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#include "opcode/spu.h"
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#include "opcode/spu.h"
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/* This file holds the Spu opcode table */
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/* This file holds the Spu opcode table */
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/*
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/*
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Example contents of spu-insn.h
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Example contents of spu-insn.h
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id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
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id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
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QUAD WORD (0,RC,RB,RA,RT) latency
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QUAD WORD (0,RC,RB,RA,RT) latency
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APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form
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APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form
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*/
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*/
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const struct spu_opcode spu_opcodes[] = {
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const struct spu_opcode spu_opcodes[] = {
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#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
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#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
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{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
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{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
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#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
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#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
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{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
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{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
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#include "opcode/spu-insns.h"
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#include "opcode/spu-insns.h"
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#undef APUOP
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#undef APUOP
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#undef APUOPFB
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#undef APUOPFB
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};
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};
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const int spu_num_opcodes =
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const int spu_num_opcodes =
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sizeof (spu_opcodes) / sizeof (spu_opcodes[0]);
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sizeof (spu_opcodes) / sizeof (spu_opcodes[0]);
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