/* libgcc routines for the Texas Instruments TMS320C[34]x
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/* libgcc routines for the Texas Instruments TMS320C[34]x
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Copyright (C) 1997,98, 1999 Free Software Foundation, Inc.
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Copyright (C) 1997,98, 1999 Free Software Foundation, Inc.
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Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
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Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
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and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
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and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
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This file is part of GCC.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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later version.
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In addition to the permissions in the GNU General Public License, the
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In addition to the permissions in the GNU General Public License, the
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Free Software Foundation gives you unlimited permission to link the
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Free Software Foundation gives you unlimited permission to link the
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compiled version of this file into combinations with other programs,
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compiled version of this file into combinations with other programs,
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and to distribute those combinations without any restriction coming
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and to distribute those combinations without any restriction coming
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from the use of this file. (The General Public License restrictions
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from the use of this file. (The General Public License restrictions
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do apply in other respects; for example, they cover modification of
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do apply in other respects; for example, they cover modification of
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the file, and distribution when not linked into a combine
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the file, and distribution when not linked into a combine
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executable.)
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executable.)
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This file is distributed in the hope that it will be useful, but
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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Boston, MA 02110-1301, USA. */
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; These routines are called using the standard TI register argument
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; These routines are called using the standard TI register argument
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; passing model.
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; passing model.
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; The following registers do not have to be saved:
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; The following registers do not have to be saved:
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; r0, r1, r2, r3, ar0, ar1, ar2, ir0, ir1, bk, rs, rc, re, (r9, r10, r11)
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; r0, r1, r2, r3, ar0, ar1, ar2, ir0, ir1, bk, rs, rc, re, (r9, r10, r11)
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;
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;
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; Perform floating point divqf3
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; Perform floating point divqf3
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;
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;
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; This routine performs a reciprocal of the divisor using the method
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; This routine performs a reciprocal of the divisor using the method
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; described in the C30/C40 user manuals. It then multiplies that
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; described in the C30/C40 user manuals. It then multiplies that
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; result by the dividend.
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; result by the dividend.
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;
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;
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; Let r be the reciprocal of the divisor v and let the ith estimate
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; Let r be the reciprocal of the divisor v and let the ith estimate
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; of r be denoted by r[i]. An iterative approach can be used to
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; of r be denoted by r[i]. An iterative approach can be used to
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; improve the estimate of r, given an initial estimate r[0], where
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; improve the estimate of r, given an initial estimate r[0], where
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;
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;
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; r[i + 1] = r[i] * (2.0 - v * r[i])
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; r[i + 1] = r[i] * (2.0 - v * r[i])
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;
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;
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; The normalized error e[i] at the ith iteration is
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; The normalized error e[i] at the ith iteration is
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;
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;
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; e[i] = (r - r[i]) / r = (1 / v - r[i]) * v = (1 - v * r[i])
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; e[i] = (r - r[i]) / r = (1 / v - r[i]) * v = (1 - v * r[i])
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;
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;
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; Note that
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; Note that
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;
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;
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; e[i + 1] = (1 - v * r[i + 1]) = 1 - 2 * v * r[i] + v^2 + (r[i])^2
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; e[i + 1] = (1 - v * r[i + 1]) = 1 - 2 * v * r[i] + v^2 + (r[i])^2
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; = (1 - v * r[i])^2 = (e[i])^2
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; = (1 - v * r[i])^2 = (e[i])^2
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; r2 dividend, r3 divisor, r0 quotient
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; r2 dividend, r3 divisor, r0 quotient
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; clobbers r1, ar1
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; clobbers r1, ar1
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#ifdef L_divsf3
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#ifdef L_divsf3
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.text
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.text
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.global ___divqf3
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.global ___divqf3
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___divqf3:
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___divqf3:
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#ifdef _TMS320C4x
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#ifdef _TMS320C4x
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.if .REGPARM == 0
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.if .REGPARM == 0
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lda sp,ar0
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lda sp,ar0
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ldf *-ar0(2), r3
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ldf *-ar0(2), r3
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.endif
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.endif
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pop ar1 ; Pop return address
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pop ar1 ; Pop return address
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; r0 = estimate of r, r1 = tmp, r2 = dividend, r3 = divisor
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; r0 = estimate of r, r1 = tmp, r2 = dividend, r3 = divisor
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rcpf r3, r0 ; Compute initial estimate r[0]
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rcpf r3, r0 ; Compute initial estimate r[0]
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mpyf3 r0, r3, r1 ; r1 = r[0] * v
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mpyf3 r0, r3, r1 ; r1 = r[0] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[0] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[0] * v
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mpyf r1, r0 ; r0 = r[0] * (2.0 - r[0] * v) = r[1]
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mpyf r1, r0 ; r0 = r[0] * (2.0 - r[0] * v) = r[1]
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; End of 1st iteration (16 bits accuracy)
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; End of 1st iteration (16 bits accuracy)
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mpyf3 r0, r3, r1 ; r1 = r[1] * v
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mpyf3 r0, r3, r1 ; r1 = r[1] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[1] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[1] * v
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bud ar1 ; Delayed branch
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bud ar1 ; Delayed branch
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mpyf r1, r0 ; r0 = r[1] * (2.0 - r[1] * v) = r[2]
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mpyf r1, r0 ; r0 = r[1] * (2.0 - r[1] * v) = r[2]
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; End of 2nd iteration (32 bits accuracy)
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; End of 2nd iteration (32 bits accuracy)
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.if .REGPARM == 0
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.if .REGPARM == 0
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mpyf *-ar0(1), r0 ; Multiply by the dividend
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mpyf *-ar0(1), r0 ; Multiply by the dividend
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.else
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.else
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mpyf r2, r0 ; Multiply by the dividend
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mpyf r2, r0 ; Multiply by the dividend
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.endif
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.endif
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rnd r0
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rnd r0
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; Branch occurs here
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; Branch occurs here
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#else
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#else
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.if .REGPARM == 0
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.if .REGPARM == 0
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ldiu sp,ar0
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ldiu sp,ar0
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ldf *-ar0(2), r3
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ldf *-ar0(2), r3
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.endif
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.endif
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pop ar1 ; Pop return address
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pop ar1 ; Pop return address
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; Initial estimate r[0] = 1.0 * 2^(-e - 1)
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; Initial estimate r[0] = 1.0 * 2^(-e - 1)
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; where v = m * 2^e
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; where v = m * 2^e
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; r0 = estimate of r, r1 = tmp, r2 = dividend, r3 = divisor
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; r0 = estimate of r, r1 = tmp, r2 = dividend, r3 = divisor
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; Calculate initial estimate r[0]
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; Calculate initial estimate r[0]
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pushf r3
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pushf r3
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pop r0
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pop r0
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not r0 ; r0 = -e
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not r0 ; r0 = -e
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; complement exponent = -e -1
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; complement exponent = -e -1
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; complement sign (side effect)
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; complement sign (side effect)
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; complement mantissa (almost 3 bit accurate)
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; complement mantissa (almost 3 bit accurate)
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push r0
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push r0
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popf r0 ; r0 = 1.0 * e^(-e - 1) + inverted mantissa
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popf r0 ; r0 = 1.0 * e^(-e - 1) + inverted mantissa
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ldf -1.0, r1 ; undo complement sign bit
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ldf -1.0, r1 ; undo complement sign bit
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xor r1, r0
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xor r1, r0
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mpyf3 r0, r3, r1 ; r1 = r[0] * v
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mpyf3 r0, r3, r1 ; r1 = r[0] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[0] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[0] * v
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mpyf r1, r0 ; r0 = r[0] * (2.0 - r[0] * v) = r[1]
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mpyf r1, r0 ; r0 = r[0] * (2.0 - r[0] * v) = r[1]
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; End of 1st iteration
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; End of 1st iteration
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mpyf3 r0, r3, r1 ; r1 = r[1] * v
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mpyf3 r0, r3, r1 ; r1 = r[1] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[1] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[1] * v
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mpyf r1, r0 ; r0 = r[1] * (2.0 - r[1] * v) = r[2]
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mpyf r1, r0 ; r0 = r[1] * (2.0 - r[1] * v) = r[2]
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; End of 2nd iteration
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; End of 2nd iteration
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mpyf3 r0, r3, r1 ; r1 = r[2] * v
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mpyf3 r0, r3, r1 ; r1 = r[2] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[2] * v
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subrf 2.0, r1 ; r1 = 2.0 - r[2] * v
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mpyf r1, r0 ; r0 = r[2] * (2.0 - r[2] * v) = r[3]
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mpyf r1, r0 ; r0 = r[2] * (2.0 - r[2] * v) = r[3]
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; End of 3rd iteration
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; End of 3rd iteration
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rnd r0 ; Minimize error in x[3]'s LSBs
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rnd r0 ; Minimize error in x[3]'s LSBs
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; Use modified last iteration
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; Use modified last iteration
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; r[4] = (r[3] * (1.0 - (v * r[3]))) + r[3]
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; r[4] = (r[3] * (1.0 - (v * r[3]))) + r[3]
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mpyf3 r0, r3, r1 ; r1 = r[3] * v
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mpyf3 r0, r3, r1 ; r1 = r[3] * v
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subrf 1.0, r1 ; r1 = 1.0 - r[3] * v
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subrf 1.0, r1 ; r1 = 1.0 - r[3] * v
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mpyf r0, r1 ; r1 = r[3] * (1.0 - r[3] * v)
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mpyf r0, r1 ; r1 = r[3] * (1.0 - r[3] * v)
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addf r1, r0 ; r0 = r[3] * (1.0 - r[3] * v) + r[3] = r[4]
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addf r1, r0 ; r0 = r[3] * (1.0 - r[3] * v) + r[3] = r[4]
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rnd r0 ; Minimize error in x[4]'s LSBs
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rnd r0 ; Minimize error in x[4]'s LSBs
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bud ar1 ; Delayed branch
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bud ar1 ; Delayed branch
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.if .REGPARM == 0
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.if .REGPARM == 0
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ldfu *-ar0(1), r2 ; Dividend in mem has only 24 bits significance
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ldfu *-ar0(1), r2 ; Dividend in mem has only 24 bits significance
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.else
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.else
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rnd r2 ; Minimize error in reg dividend's LSBs
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rnd r2 ; Minimize error in reg dividend's LSBs
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; since this may have 32 bit significance
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; since this may have 32 bit significance
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.endif
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.endif
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mpyf r2, r0 ; Multiply by the dividend
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mpyf r2, r0 ; Multiply by the dividend
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rnd r0 ; Round result to 32 bits
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rnd r0 ; Round result to 32 bits
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; Branch occurs here
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; Branch occurs here
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#endif
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#endif
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#endif
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#endif
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;
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;
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; Integer signed division
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; Integer signed division
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;
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;
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; ar2 dividend, r2 divisor, r0 quotient
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; ar2 dividend, r2 divisor, r0 quotient
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; clobbers r1, r3, ar0, ar1, ir0, ir1, rc, rs, re
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; clobbers r1, r3, ar0, ar1, ir0, ir1, rc, rs, re
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#ifdef L_divsi3
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#ifdef L_divsi3
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.text
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.text
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.global ___divqi3
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.global ___divqi3
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.ref udivqi3n
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.ref udivqi3n
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___divqi3:
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___divqi3:
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.if .REGPARM == 0
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.if .REGPARM == 0
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#ifdef _TMS320C4x
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#ifdef _TMS320C4x
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lda sp,ar0
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lda sp,ar0
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#else
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#else
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ldiu sp,ar0
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ldiu sp,ar0
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#endif
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#endif
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ldi *-ar0(1), ar2
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ldi *-ar0(1), ar2
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ldi *-ar0(2), r2
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ldi *-ar0(2), r2
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.endif
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.endif
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xor3 ar2, r2, r3 ; Get the sign
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xor3 ar2, r2, r3 ; Get the sign
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absi ar2, r0
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absi ar2, r0
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bvd divq32
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bvd divq32
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ldi r0, ar2
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ldi r0, ar2
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absi r2, r2
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absi r2, r2
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cmpi ar2, r2 ; Divisor > dividend?
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cmpi ar2, r2 ; Divisor > dividend?
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pop ir1
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pop ir1
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bhid zero ; If so, return 0
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bhid zero ; If so, return 0
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;
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;
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; Normalize oeprands. Use difference exponents as shift count
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; Normalize oeprands. Use difference exponents as shift count
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; for divisor, and as repeat count for "subc"
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; for divisor, and as repeat count for "subc"
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;
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;
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float ar2, r1 ; Normalize dividend
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float ar2, r1 ; Normalize dividend
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pushf r1 ; Get as integer
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pushf r1 ; Get as integer
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pop ar0
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pop ar0
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lsh -24, ar0 ; Get exponent
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lsh -24, ar0 ; Get exponent
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float r2, r1 ; Normalize divisor
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float r2, r1 ; Normalize divisor
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pushf r1 ; Get as integer
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pushf r1 ; Get as integer
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pop ir0
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pop ir0
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lsh -24, ir0 ; Get exponent
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lsh -24, ir0 ; Get exponent
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subi ir0, ar0 ; Get difference of exponents
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subi ir0, ar0 ; Get difference of exponents
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lsh ar0, r2 ; Align divisor with dividend
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lsh ar0, r2 ; Align divisor with dividend
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;
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;
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; Do count + 1 subtracts and shifts
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; Do count + 1 subtracts and shifts
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;
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;
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rpts ar0
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rpts ar0
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subc r2, ar2
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subc r2, ar2
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;
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;
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; Mask off the lower count+1 bits of ar2
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; Mask off the lower count+1 bits of ar2
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;
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;
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subri 31, ar0 ; Shift count is (32 - (ar0 + 1))
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subri 31, ar0 ; Shift count is (32 - (ar0 + 1))
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lsh ar0, ar2 ; Shift left
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lsh ar0, ar2 ; Shift left
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negi ar0, ar0
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negi ar0, ar0
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lsh3 ar0, ar2, r0 ; Shift right and put result in r0
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lsh3 ar0, ar2, r0 ; Shift right and put result in r0
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;
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;
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; Check sign and negate result if necessary
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; Check sign and negate result if necessary
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;
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;
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bud ir1 ; Delayed return
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bud ir1 ; Delayed return
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negi r0, r1 ; Negate result
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negi r0, r1 ; Negate result
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ash -31, r3 ; Check sign
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ash -31, r3 ; Check sign
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ldinz r1, r0 ; If set, use negative result
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ldinz r1, r0 ; If set, use negative result
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; Branch occurs here
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; Branch occurs here
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zero: bud ir1 ; Delayed branch
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zero: bud ir1 ; Delayed branch
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ldi 0, r0
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ldi 0, r0
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nop
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nop
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nop
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nop
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; Branch occurs here
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; Branch occurs here
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;
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;
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; special case where ar2 = abs(ar2) = 0x80000000. We handle this by
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; special case where ar2 = abs(ar2) = 0x80000000. We handle this by
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; calling unsigned divide and negating the result if necessary.
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; calling unsigned divide and negating the result if necessary.
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;
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;
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divq32:
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divq32:
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push r3 ; Save sign
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push r3 ; Save sign
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call udivqi3n
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call udivqi3n
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pop r3
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pop r3
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pop ir1
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pop ir1
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bd ir1
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bd ir1
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negi r0, r1 ; Negate result
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negi r0, r1 ; Negate result
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ash -31, r3 ; Check sign
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ash -31, r3 ; Check sign
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ldinz r1, r0 ; If set, use negative result
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ldinz r1, r0 ; If set, use negative result
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; Branch occurs here
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; Branch occurs here
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#endif
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#endif
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;
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;
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;
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;
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; ar2 dividend, r2 divisor, r0 quotient,
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; ar2 dividend, r2 divisor, r0 quotient,
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; clobbers r1, r3, ar0, ar1, ir0, ir1, rc, rs, re
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; clobbers r1, r3, ar0, ar1, ir0, ir1, rc, rs, re
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#ifdef L_udivsi3
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#ifdef L_udivsi3
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.text
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.text
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.global ___udivqi3
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.global ___udivqi3
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.global udivqi3n
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.global udivqi3n
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___udivqi3:
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___udivqi3:
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.if .REGPARM == 0
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.if .REGPARM == 0
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#ifdef _TMS320C4x
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#ifdef _TMS320C4x
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lda sp,ar0
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lda sp,ar0
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#else
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#else
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ldiu sp,ar0
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ldiu sp,ar0
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#endif
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#endif
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ldi *-ar0(1), ar2
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ldi *-ar0(1), ar2
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ldi *-ar0(2), r2
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ldi *-ar0(2), r2
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.endif
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.endif
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udivqi3n:
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udivqi3n:
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pop ir1
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pop ir1
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cmpi ar2, r2 ; If divisor > dividend
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cmpi ar2, r2 ; If divisor > dividend
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bhi qzero ; return zero
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bhi qzero ; return zero
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ldi r2, ar1 ; Store divisor in ar1
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ldi r2, ar1 ; Store divisor in ar1
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|
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tstb ar2, ar2 ; Check top bit, jump if set to special handler
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tstb ar2, ar2 ; Check top bit, jump if set to special handler
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bld div_32 ; Delayed branch
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bld div_32 ; Delayed branch
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;
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;
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; Get divisor exponent
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; Get divisor exponent
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;
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;
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float ar1, r1 ; Normalize the divisor
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float ar1, r1 ; Normalize the divisor
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pushf r1 ; Get into int register
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pushf r1 ; Get into int register
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pop rc
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pop rc
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; branch occurs here
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; branch occurs here
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bzd qzero ; if (float) divisor zero, return zero
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bzd qzero ; if (float) divisor zero, return zero
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float ar2, r1 ; Normalize the dividend
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float ar2, r1 ; Normalize the dividend
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pushf r1 ; Get into int register
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pushf r1 ; Get into int register
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pop ar0
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pop ar0
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lsh -24, ar0 ; Get both the exponents
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lsh -24, ar0 ; Get both the exponents
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lsh -24, rc
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lsh -24, rc
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subi rc, ar0 ; Get the difference between the exponents
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subi rc, ar0 ; Get the difference between the exponents
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lsh ar0, ar1 ; Normalize the divisor with the dividend
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lsh ar0, ar1 ; Normalize the divisor with the dividend
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|
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;
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;
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; Do count_1 subtracts and shifts
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; Do count_1 subtracts and shifts
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;
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;
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rpts ar0
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rpts ar0
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subc ar1, ar2
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subc ar1, ar2
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;
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;
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; mask off the lower count+1 bits
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; mask off the lower count+1 bits
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;
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;
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subri 31, ar0 ; Shift count (31 - (ar0+1))
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subri 31, ar0 ; Shift count (31 - (ar0+1))
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bud ir1 ; Delayed return
|
bud ir1 ; Delayed return
|
lsh3 ar0, ar2, r0
|
lsh3 ar0, ar2, r0
|
negi ar0, ar0
|
negi ar0, ar0
|
lsh ar0, r0
|
lsh ar0, r0
|
; Branch occurs here
|
; Branch occurs here
|
|
|
;
|
;
|
; Handle a full 32-bit dividend
|
; Handle a full 32-bit dividend
|
;
|
;
|
div_32: tstb ar1, ar1
|
div_32: tstb ar1, ar1
|
bld qone ; if divisor high bit is one, the result is one
|
bld qone ; if divisor high bit is one, the result is one
|
lsh -24, rc
|
lsh -24, rc
|
subri 31, rc
|
subri 31, rc
|
lsh rc, ar1 ; Line up the divisor
|
lsh rc, ar1 ; Line up the divisor
|
|
|
;
|
;
|
; Now divisor and dividend are aligned. Do first SUBC by hand, save
|
; Now divisor and dividend are aligned. Do first SUBC by hand, save
|
; of the forst quotient digit. Then, shift divisor right rather
|
; of the forst quotient digit. Then, shift divisor right rather
|
; than shifting dividend left. This leaves a zero in the top bit of
|
; than shifting dividend left. This leaves a zero in the top bit of
|
; the divident
|
; the divident
|
;
|
;
|
ldi 1, ar0 ; Initizialize MSB of quotient
|
ldi 1, ar0 ; Initizialize MSB of quotient
|
lsh rc, ar0 ; create a mask for MSBs
|
lsh rc, ar0 ; create a mask for MSBs
|
subi 1, ar0 ; mask is (2 << count) - 1
|
subi 1, ar0 ; mask is (2 << count) - 1
|
|
|
subi3 ar1, ar2, r1
|
subi3 ar1, ar2, r1
|
ldihs r1, ar2
|
ldihs r1, ar2
|
ldihs 1, r1
|
ldihs 1, r1
|
ldilo 0, r1
|
ldilo 0, r1
|
lsh rc, r1
|
lsh rc, r1
|
|
|
lsh -1, ar1
|
lsh -1, ar1
|
subi 1, rc
|
subi 1, rc
|
;
|
;
|
; do the rest of the shifts and subtracts
|
; do the rest of the shifts and subtracts
|
;
|
;
|
rpts rc
|
rpts rc
|
subc ar1, ar2
|
subc ar1, ar2
|
|
|
bud ir1
|
bud ir1
|
and ar0, ar2
|
and ar0, ar2
|
or3 r1, ar2, r0
|
or3 r1, ar2, r0
|
nop
|
nop
|
|
|
qone:
|
qone:
|
bud ir1
|
bud ir1
|
ldi 1, r0
|
ldi 1, r0
|
nop
|
nop
|
nop
|
nop
|
|
|
qzero:
|
qzero:
|
bud ir1
|
bud ir1
|
ldi 0, r0
|
ldi 0, r0
|
nop
|
nop
|
nop
|
nop
|
#endif
|
#endif
|
|
|
#ifdef L_umodsi3
|
#ifdef L_umodsi3
|
.text
|
.text
|
.global ___umodqi3
|
.global ___umodqi3
|
.global umodqi3n
|
.global umodqi3n
|
___umodqi3:
|
___umodqi3:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldi *-ar0(1), ar2
|
ldi *-ar0(1), ar2
|
ldi *-ar0(2), r2
|
ldi *-ar0(2), r2
|
.endif
|
.endif
|
|
|
umodqi3n:
|
umodqi3n:
|
pop ir1 ; return address
|
pop ir1 ; return address
|
cmpi ar2, r2 ; divisor > dividend ?
|
cmpi ar2, r2 ; divisor > dividend ?
|
bhi uzero ; if so, return dividend
|
bhi uzero ; if so, return dividend
|
ldi r2, ar1 ; load divisor
|
ldi r2, ar1 ; load divisor
|
;
|
;
|
; If top bit of dividend is set, handle specially.
|
; If top bit of dividend is set, handle specially.
|
;
|
;
|
tstb ar2, ar2 ; check top bit
|
tstb ar2, ar2 ; check top bit
|
bld umod_32 ; get divisor exponent, then jump.
|
bld umod_32 ; get divisor exponent, then jump.
|
;
|
;
|
; Get divisor exponent by converting to float.
|
; Get divisor exponent by converting to float.
|
;
|
;
|
float ar1, r1 ; normalize divisor
|
float ar1, r1 ; normalize divisor
|
pushf r1 ; push as float
|
pushf r1 ; push as float
|
pop rc ; pop as int to get exponent
|
pop rc ; pop as int to get exponent
|
bzd uzero ; if (float)divisor was zero, return
|
bzd uzero ; if (float)divisor was zero, return
|
;
|
;
|
; 31 or less bits in dividend. Get dividend exponent.
|
; 31 or less bits in dividend. Get dividend exponent.
|
;
|
;
|
float ar2, r1 ; normalize dividend
|
float ar2, r1 ; normalize dividend
|
pushf r1 ; push as float
|
pushf r1 ; push as float
|
pop ar0 ; pop as int to get exponent
|
pop ar0 ; pop as int to get exponent
|
;
|
;
|
; Use difference in exponents as shift count to line up MSBs.
|
; Use difference in exponents as shift count to line up MSBs.
|
;
|
;
|
lsh -24, rc ; divisor exponent
|
lsh -24, rc ; divisor exponent
|
lsh -24, ar0 ; dividend exponent
|
lsh -24, ar0 ; dividend exponent
|
subi rc, ar0 ; difference
|
subi rc, ar0 ; difference
|
lsh ar0, ar1 ; shift divisor up
|
lsh ar0, ar1 ; shift divisor up
|
;
|
;
|
; Do COUNT+1 subtract & shifts.
|
; Do COUNT+1 subtract & shifts.
|
;
|
;
|
rpts ar0
|
rpts ar0
|
subc ar1, ar2
|
subc ar1, ar2
|
;
|
;
|
; Remainder is in upper 31-COUNT bits.
|
; Remainder is in upper 31-COUNT bits.
|
;
|
;
|
bud ir1 ; delayed branch to return
|
bud ir1 ; delayed branch to return
|
addi 1, ar0 ; shift count is COUNT+1
|
addi 1, ar0 ; shift count is COUNT+1
|
negi ar0, ar0 ; negate for right shift
|
negi ar0, ar0 ; negate for right shift
|
lsh3 ar0, ar2, r0 ; shift to get result
|
lsh3 ar0, ar2, r0 ; shift to get result
|
; Return occurs here
|
; Return occurs here
|
|
|
;
|
;
|
; The following code handles cases of a full 32-bit dividend. Before
|
; The following code handles cases of a full 32-bit dividend. Before
|
; SUBC can be used, the top bit must be cleared (otherwise SUBC can
|
; SUBC can be used, the top bit must be cleared (otherwise SUBC can
|
; possibly shift a significant 1 out the top of the dividend). This
|
; possibly shift a significant 1 out the top of the dividend). This
|
; is accomplished by first doing a normal subtraction, then proceeding
|
; is accomplished by first doing a normal subtraction, then proceeding
|
; with SUBCs.
|
; with SUBCs.
|
;
|
;
|
umod_32:
|
umod_32:
|
;
|
;
|
; If the top bit of the divisor is set too, the remainder is simply
|
; If the top bit of the divisor is set too, the remainder is simply
|
; the difference between the dividend and divisor. Otherwise, shift
|
; the difference between the dividend and divisor. Otherwise, shift
|
; the divisor up to line up the MSBs.
|
; the divisor up to line up the MSBs.
|
;
|
;
|
tstb ar1, ar1 ; check divisor
|
tstb ar1, ar1 ; check divisor
|
bld uone ; if negative, remainder is diff
|
bld uone ; if negative, remainder is diff
|
|
|
lsh -24, rc ; divisor exponent
|
lsh -24, rc ; divisor exponent
|
subri 31, rc ; shift count = 31 - exp
|
subri 31, rc ; shift count = 31 - exp
|
negi rc, ar0 ; used later as shift count
|
negi rc, ar0 ; used later as shift count
|
lsh rc, ar1 ; shift up to line up MSBs
|
lsh rc, ar1 ; shift up to line up MSBs
|
;
|
;
|
; Now MSBs are aligned. Do first SUBC by hand using a plain subtraction.
|
; Now MSBs are aligned. Do first SUBC by hand using a plain subtraction.
|
; Then, shift divisor right rather than shifting dividend left. This leaves
|
; Then, shift divisor right rather than shifting dividend left. This leaves
|
; a 0 in the top bit of the dividend.
|
; a 0 in the top bit of the dividend.
|
;
|
;
|
subi3 ar1, ar2, r1 ; subtract
|
subi3 ar1, ar2, r1 ; subtract
|
ldihs r1, ar2 ; if positive, replace dividend
|
ldihs r1, ar2 ; if positive, replace dividend
|
subi 1, rc ; first iteration is done
|
subi 1, rc ; first iteration is done
|
lsh -1, ar1 ; shift divisor down
|
lsh -1, ar1 ; shift divisor down
|
;
|
;
|
; Do EXP subtract & shifts.
|
; Do EXP subtract & shifts.
|
;
|
;
|
rpts rc
|
rpts rc
|
subc ar1, ar2
|
subc ar1, ar2
|
;
|
;
|
; Quotient is in EXP+1 LSBs; shift remainder (in MSBs) down.
|
; Quotient is in EXP+1 LSBs; shift remainder (in MSBs) down.
|
;
|
;
|
bud ir1
|
bud ir1
|
lsh3 ar0, ar2, r0 ; COUNT contains -(EXP+1)
|
lsh3 ar0, ar2, r0 ; COUNT contains -(EXP+1)
|
nop
|
nop
|
nop
|
nop
|
;
|
;
|
; Return (dividend - divisor).
|
; Return (dividend - divisor).
|
;
|
;
|
uone: bud ir1
|
uone: bud ir1
|
subi3 r2, ar2, r0
|
subi3 r2, ar2, r0
|
nop
|
nop
|
nop
|
nop
|
;
|
;
|
; Return dividend.
|
; Return dividend.
|
;
|
;
|
uzero: bud ir1
|
uzero: bud ir1
|
ldi ar2, r0 ; set status from result
|
ldi ar2, r0 ; set status from result
|
nop
|
nop
|
nop
|
nop
|
#endif
|
#endif
|
|
|
#ifdef L_modsi3
|
#ifdef L_modsi3
|
.text
|
.text
|
.global ___modqi3
|
.global ___modqi3
|
.ref umodqi3n
|
.ref umodqi3n
|
___modqi3:
|
___modqi3:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldi *-ar0(1), ar2
|
ldi *-ar0(1), ar2
|
ldi *-ar0(2), r2
|
ldi *-ar0(2), r2
|
.endif
|
.endif
|
|
|
;
|
;
|
; Determine sign of result. Get absolute value of operands.
|
; Determine sign of result. Get absolute value of operands.
|
;
|
;
|
ldi ar2, ar0 ; sign of result same as dividend
|
ldi ar2, ar0 ; sign of result same as dividend
|
absi ar2, r0 ; make dividend positive
|
absi ar2, r0 ; make dividend positive
|
bvd mod_32 ; if still negative, escape
|
bvd mod_32 ; if still negative, escape
|
absi r2, r1 ; make divisor positive
|
absi r2, r1 ; make divisor positive
|
ldi r1, ar1 ; save in ar1
|
ldi r1, ar1 ; save in ar1
|
cmpi r0, ar1 ; divisor > dividend ?
|
cmpi r0, ar1 ; divisor > dividend ?
|
|
|
pop ir1 ; return address
|
pop ir1 ; return address
|
bhid return ; if so, return dividend
|
bhid return ; if so, return dividend
|
;
|
;
|
; Normalize operands. Use difference in exponents as shift count
|
; Normalize operands. Use difference in exponents as shift count
|
; for divisor, and as repeat count for SUBC.
|
; for divisor, and as repeat count for SUBC.
|
;
|
;
|
float r1, r1 ; normalize divisor
|
float r1, r1 ; normalize divisor
|
pushf r1 ; push as float
|
pushf r1 ; push as float
|
pop rc ; pop as int
|
pop rc ; pop as int
|
bzd return ; if (float)divisor was zero, return
|
bzd return ; if (float)divisor was zero, return
|
|
|
float r0, r1 ; normalize dividend
|
float r0, r1 ; normalize dividend
|
pushf r1 ; push as float
|
pushf r1 ; push as float
|
pop r1 ; pop as int
|
pop r1 ; pop as int
|
|
|
lsh -24, rc ; get divisor exponent
|
lsh -24, rc ; get divisor exponent
|
lsh -24, r1 ; get dividend exponent
|
lsh -24, r1 ; get dividend exponent
|
subi rc, r1 ; get difference in exponents
|
subi rc, r1 ; get difference in exponents
|
lsh r1, ar1 ; align divisor with dividend
|
lsh r1, ar1 ; align divisor with dividend
|
;
|
;
|
; Do COUNT+1 subtract & shifts.
|
; Do COUNT+1 subtract & shifts.
|
;
|
;
|
rpts r1
|
rpts r1
|
subc ar1, r0
|
subc ar1, r0
|
;
|
;
|
; Remainder is in upper bits of R0
|
; Remainder is in upper bits of R0
|
;
|
;
|
addi 1, r1 ; shift count is -(r1+1)
|
addi 1, r1 ; shift count is -(r1+1)
|
negi r1, r1
|
negi r1, r1
|
lsh r1, r0 ; shift right
|
lsh r1, r0 ; shift right
|
;
|
;
|
; Check sign and negate result if necessary.
|
; Check sign and negate result if necessary.
|
;
|
;
|
return:
|
return:
|
bud ir1 ; delayed branch to return
|
bud ir1 ; delayed branch to return
|
negi r0, r1 ; negate result
|
negi r0, r1 ; negate result
|
cmpi 0, ar0 ; check sign
|
cmpi 0, ar0 ; check sign
|
ldin r1, r0 ; if set, use negative result
|
ldin r1, r0 ; if set, use negative result
|
; Return occurs here
|
; Return occurs here
|
;
|
;
|
; The following code handles cases of a full 32-bit dividend. This occurs
|
; The following code handles cases of a full 32-bit dividend. This occurs
|
; when R0 = abs(R0) = 080000000h. Handle this by calling the unsigned mod
|
; when R0 = abs(R0) = 080000000h. Handle this by calling the unsigned mod
|
; function, then negating the result if necessary.
|
; function, then negating the result if necessary.
|
;
|
;
|
mod_32:
|
mod_32:
|
push ar0 ; remember sign
|
push ar0 ; remember sign
|
call umodqi3n ; do divide
|
call umodqi3n ; do divide
|
|
|
brd return ; return
|
brd return ; return
|
pop ar0 ; restore sign
|
pop ar0 ; restore sign
|
pop ir1 ; return address
|
pop ir1 ; return address
|
nop
|
nop
|
#endif
|
#endif
|
|
|
#ifdef L_unsfltconst
|
#ifdef L_unsfltconst
|
.section .const
|
.section .const
|
.global ___unsfltconst
|
.global ___unsfltconst
|
___unsfltconst: .float 4294967296.0
|
___unsfltconst: .float 4294967296.0
|
#endif
|
#endif
|
|
|
#ifdef L_unsfltcompare
|
#ifdef L_unsfltcompare
|
.section .const
|
.section .const
|
.global ___unsfltcompare
|
.global ___unsfltcompare
|
___unsfltcompare: .float 2147483648.0
|
___unsfltcompare: .float 2147483648.0
|
#endif
|
#endif
|
|
|
; Integer 32-bit signed multiplication
|
; Integer 32-bit signed multiplication
|
;
|
;
|
; The TMS320C3x MPYI instruction takes two 24-bit signed integers
|
; The TMS320C3x MPYI instruction takes two 24-bit signed integers
|
; and produces a 48-bit signed result which is truncated to 32-bits.
|
; and produces a 48-bit signed result which is truncated to 32-bits.
|
;
|
;
|
; A 32-bit by 32-bit multiplication thus requires a number of steps.
|
; A 32-bit by 32-bit multiplication thus requires a number of steps.
|
;
|
;
|
; Consider the product of two 32-bit signed integers,
|
; Consider the product of two 32-bit signed integers,
|
;
|
;
|
; z = x * y
|
; z = x * y
|
;
|
;
|
; where x = (b << 16) + a, y = (d << 16) + c
|
; where x = (b << 16) + a, y = (d << 16) + c
|
;
|
;
|
; This can be expressed as
|
; This can be expressed as
|
;
|
;
|
; z = ((b << 16) + a) * ((d << 16) + c)
|
; z = ((b << 16) + a) * ((d << 16) + c)
|
;
|
;
|
; = ((b * d) << 32) + ((b * c + a * d) << 16) + a * c
|
; = ((b * d) << 32) + ((b * c + a * d) << 16) + a * c
|
;
|
;
|
; Let z = (f << 16) + e where f < (1 << 16).
|
; Let z = (f << 16) + e where f < (1 << 16).
|
;
|
;
|
; Since we are only interested in a 32-bit result, we can ignore the
|
; Since we are only interested in a 32-bit result, we can ignore the
|
; (b * d) << 32 term, and thus
|
; (b * d) << 32 term, and thus
|
;
|
;
|
; f = b * c + a * d, e = a * c
|
; f = b * c + a * d, e = a * c
|
;
|
;
|
; We can simplify things if we have some a priori knowledge of the
|
; We can simplify things if we have some a priori knowledge of the
|
; operands, for example, if -32768 <= y <= 32767, then y = c and d = 0 and thus
|
; operands, for example, if -32768 <= y <= 32767, then y = c and d = 0 and thus
|
;
|
;
|
; f = b * c, e = a * c
|
; f = b * c, e = a * c
|
;
|
;
|
; ar2 multiplier, r2 multiplicand, r0 product
|
; ar2 multiplier, r2 multiplicand, r0 product
|
; clobbers r1, r2, r3
|
; clobbers r1, r2, r3
|
#ifdef L_mulsi3
|
#ifdef L_mulsi3
|
.text
|
.text
|
.global ___mulqi3
|
.global ___mulqi3
|
___mulqi3:
|
___mulqi3:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldi *-ar0(1), ar2
|
ldi *-ar0(1), ar2
|
ldi *-ar0(2), r2
|
ldi *-ar0(2), r2
|
.endif
|
.endif
|
|
|
pop ir1 ; return address
|
pop ir1 ; return address
|
ldi ar2, r0 ;
|
ldi ar2, r0 ;
|
and 0ffffh, r0 ; a
|
and 0ffffh, r0 ; a
|
lsh -16, ar2 ; b
|
lsh -16, ar2 ; b
|
ldi r2, r3 ;
|
ldi r2, r3 ;
|
and 0ffffh, r3 ; c
|
and 0ffffh, r3 ; c
|
mpyi r3, ar2 ; c * b
|
mpyi r3, ar2 ; c * b
|
lsh -16, r2 ; d
|
lsh -16, r2 ; d
|
mpyi r0, r2 ; a * d
|
mpyi r0, r2 ; a * d
|
addi ar2, r2 ; c * b + a * d
|
addi ar2, r2 ; c * b + a * d
|
bd ir1 ; delayed branch to return
|
bd ir1 ; delayed branch to return
|
lsh 16, r2 ; (c * b + a * d) << 16
|
lsh 16, r2 ; (c * b + a * d) << 16
|
mpyi r3, r0 ; a * c
|
mpyi r3, r0 ; a * c
|
addi r2, r0 ; a * c + (c * b + a * d) << 16
|
addi r2, r0 ; a * c + (c * b + a * d) << 16
|
; branch occurs here
|
; branch occurs here
|
|
|
#endif
|
#endif
|
|
|
;
|
;
|
; Integer 64 by 64 multiply
|
; Integer 64 by 64 multiply
|
; long1 and long2 on stack
|
; long1 and long2 on stack
|
; result in r0,r1
|
; result in r0,r1
|
;
|
;
|
#ifdef L_muldi3
|
#ifdef L_muldi3
|
.text
|
.text
|
.global ___mulhi3
|
.global ___mulhi3
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
___mulhi3:
|
___mulhi3:
|
pop ar0
|
pop ar0
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi *-ar2(1),r2
|
ldi *-ar2(1),r2
|
ldi *-ar2(3),r3
|
ldi *-ar2(3),r3
|
mpyi3 r2,r3,r0
|
mpyi3 r2,r3,r0
|
mpyuhi3 r2,r3,r1
|
mpyuhi3 r2,r3,r1
|
mpyi *-ar2(2),r2
|
mpyi *-ar2(2),r2
|
bd ar0
|
bd ar0
|
mpyi *-ar2(0),r3
|
mpyi *-ar2(0),r3
|
addi r2,r1
|
addi r2,r1
|
addi r3,r1
|
addi r3,r1
|
#else
|
#else
|
___mulhi3:
|
___mulhi3:
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi -16,rs
|
ldi -16,rs
|
ldi *-ar2(2),ar0
|
ldi *-ar2(2),ar0
|
ldi *-ar2(4),ar1
|
ldi *-ar2(4),ar1
|
ldi ar0,r2
|
ldi ar0,r2
|
and 0ffffh,r2
|
and 0ffffh,r2
|
ldi ar1,r3
|
ldi ar1,r3
|
and 0ffffh,r3
|
and 0ffffh,r3
|
lsh rs,ar0
|
lsh rs,ar0
|
lsh rs,ar1
|
lsh rs,ar1
|
|
|
mpyi r2,r3,r0
|
mpyi r2,r3,r0
|
mpyi ar0,ar1,r1
|
mpyi ar0,ar1,r1
|
mpyi r2,ar1,rc
|
mpyi r2,ar1,rc
|
lsh rs,rc,re
|
lsh rs,rc,re
|
addi re,r1
|
addi re,r1
|
lsh 16,rc
|
lsh 16,rc
|
addi rc,r0
|
addi rc,r0
|
addc 0,r1
|
addc 0,r1
|
mpyi r3,ar0,rc
|
mpyi r3,ar0,rc
|
lsh rs,rc,re
|
lsh rs,rc,re
|
addi re,r1
|
addi re,r1
|
lsh 16,rc
|
lsh 16,rc
|
addi rc,r0
|
addi rc,r0
|
addc 0,r1
|
addc 0,r1
|
|
|
ldi *-ar2(1),ar0
|
ldi *-ar2(1),ar0
|
ldi ar0,r2
|
ldi ar0,r2
|
and 0ffffh,r2
|
and 0ffffh,r2
|
lsh rs,ar0
|
lsh rs,ar0
|
mpyi r2,r3,rc
|
mpyi r2,r3,rc
|
addi rc,r1
|
addi rc,r1
|
mpyi r2,ar1,rc
|
mpyi r2,ar1,rc
|
mpyi r3,ar0,re
|
mpyi r3,ar0,re
|
addi re,rc
|
addi re,rc
|
lsh 16,rc
|
lsh 16,rc
|
addi rc,r1
|
addi rc,r1
|
|
|
ldi *-ar2(2),ar0
|
ldi *-ar2(2),ar0
|
ldi *-ar2(3),ar1
|
ldi *-ar2(3),ar1
|
ldi ar0,r2
|
ldi ar0,r2
|
and 0ffffh,r2
|
and 0ffffh,r2
|
ldi ar1,r3
|
ldi ar1,r3
|
and 0ffffh,r3
|
and 0ffffh,r3
|
lsh rs,ar0
|
lsh rs,ar0
|
lsh rs,ar1
|
lsh rs,ar1
|
mpyi r2,r3,rc
|
mpyi r2,r3,rc
|
addi rc,r1
|
addi rc,r1
|
mpyi r2,ar1,rc
|
mpyi r2,ar1,rc
|
mpyi r3,ar0,re
|
mpyi r3,ar0,re
|
pop ar0
|
pop ar0
|
bd ar0
|
bd ar0
|
addi re,rc
|
addi re,rc
|
lsh 16,rc
|
lsh 16,rc
|
addi rc,r1
|
addi rc,r1
|
#endif
|
#endif
|
#endif
|
#endif
|
|
|
;
|
;
|
; Integer 32 by 32 multiply highpart unsigned
|
; Integer 32 by 32 multiply highpart unsigned
|
; src1 in ar2
|
; src1 in ar2
|
; src2 in r2
|
; src2 in r2
|
; result in r0
|
; result in r0
|
;
|
;
|
#ifdef L_umuldi3_high
|
#ifdef L_umuldi3_high
|
.text
|
.text
|
.global ___umulhi3_high
|
.global ___umulhi3_high
|
___umulhi3_high:
|
___umulhi3_high:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldi *-ar0(1), ar2
|
ldi *-ar0(1), ar2
|
ldi *-ar0(2), r2
|
ldi *-ar0(2), r2
|
.endif
|
.endif
|
|
|
ldi -16,rs
|
ldi -16,rs
|
ldi r2,r3
|
ldi r2,r3
|
and 0ffffh,r2
|
and 0ffffh,r2
|
ldi ar2,ar1
|
ldi ar2,ar1
|
and 0ffffh,ar2
|
and 0ffffh,ar2
|
lsh rs,r3
|
lsh rs,r3
|
lsh rs,ar1
|
lsh rs,ar1
|
|
|
mpyi ar2,r2,r1
|
mpyi ar2,r2,r1
|
mpyi ar1,r3,r0
|
mpyi ar1,r3,r0
|
mpyi ar2,r3,rc
|
mpyi ar2,r3,rc
|
lsh rs,rc,re
|
lsh rs,rc,re
|
addi re,r0
|
addi re,r0
|
lsh 16,rc
|
lsh 16,rc
|
addi rc,r1
|
addi rc,r1
|
addc 0,r0
|
addc 0,r0
|
mpyi r2,ar1,rc
|
mpyi r2,ar1,rc
|
lsh rs,rc,re
|
lsh rs,rc,re
|
addi re,r0
|
addi re,r0
|
pop ar0
|
pop ar0
|
bd ar0
|
bd ar0
|
lsh 16,rc
|
lsh 16,rc
|
addi rc,r1
|
addi rc,r1
|
addc 0,r0
|
addc 0,r0
|
#endif
|
#endif
|
|
|
;
|
;
|
; Integer 32 by 32 multiply highpart signed
|
; Integer 32 by 32 multiply highpart signed
|
; src1 in ar2
|
; src1 in ar2
|
; src2 in r2
|
; src2 in r2
|
; result in r0
|
; result in r0
|
;
|
;
|
#ifdef L_smuldi3_high
|
#ifdef L_smuldi3_high
|
.text
|
.text
|
.global ___smulhi3_high
|
.global ___smulhi3_high
|
___smulhi3_high:
|
___smulhi3_high:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldi *-ar0(1), ar2
|
ldi *-ar0(1), ar2
|
ldi *-ar0(2), r2
|
ldi *-ar0(2), r2
|
.endif
|
.endif
|
|
|
ldi -16,rs
|
ldi -16,rs
|
ldi 0,rc
|
ldi 0,rc
|
subi3 ar2,rc,r0
|
subi3 ar2,rc,r0
|
ldi r2,r3
|
ldi r2,r3
|
ldilt r0,rc
|
ldilt r0,rc
|
subi3 r2,rc,r0
|
subi3 r2,rc,r0
|
ldi ar2,ar1
|
ldi ar2,ar1
|
tstb ar1,ar1
|
tstb ar1,ar1
|
ldilt r0,rc
|
ldilt r0,rc
|
and 0ffffh,r2
|
and 0ffffh,r2
|
and 0ffffh,ar2
|
and 0ffffh,ar2
|
lsh rs,r3
|
lsh rs,r3
|
lsh rs,ar1
|
lsh rs,ar1
|
|
|
mpyi ar2,r2,r1
|
mpyi ar2,r2,r1
|
mpyi ar1,r3,r0
|
mpyi ar1,r3,r0
|
addi rc,r0
|
addi rc,r0
|
mpyi ar2,r3,rc
|
mpyi ar2,r3,rc
|
lsh rs,rc,re
|
lsh rs,rc,re
|
addi re,r0
|
addi re,r0
|
lsh 16,rc
|
lsh 16,rc
|
addi rc,r1
|
addi rc,r1
|
addc 0,r0
|
addc 0,r0
|
mpyi r2,ar1,rc
|
mpyi r2,ar1,rc
|
lsh rs,rc,re
|
lsh rs,rc,re
|
addi re,r0
|
addi re,r0
|
pop ar0
|
pop ar0
|
bd ar0
|
bd ar0
|
lsh 16,rc
|
lsh 16,rc
|
addi rc,r1
|
addi rc,r1
|
addc 0,r0
|
addc 0,r0
|
#endif
|
#endif
|
|
|
;
|
;
|
; Integer 64 by 64 unsigned divide
|
; Integer 64 by 64 unsigned divide
|
; long1 and long2 on stack
|
; long1 and long2 on stack
|
; divide in r0,r1
|
; divide in r0,r1
|
; modulo in r2,r3
|
; modulo in r2,r3
|
; routine takes a maximum of 64*8+23=535 cycles = 21.4 us @ 50Mhz
|
; routine takes a maximum of 64*8+23=535 cycles = 21.4 us @ 50Mhz
|
;
|
;
|
#ifdef L_udivdi3
|
#ifdef L_udivdi3
|
.text
|
.text
|
.global ___udivhi3
|
.global ___udivhi3
|
.global ___udivide
|
.global ___udivide
|
.global ___umodulo
|
.global ___umodulo
|
.ref udivqi3n
|
.ref udivqi3n
|
.ref umodqi3n
|
.ref umodqi3n
|
___udivhi3:
|
___udivhi3:
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi *-ar2(4),ar0
|
ldi *-ar2(4),ar0
|
ldi *-ar2(3),ar1
|
ldi *-ar2(3),ar1
|
ldi *-ar2(2),r0
|
ldi *-ar2(2),r0
|
ldi *-ar2(1),r1
|
ldi *-ar2(1),r1
|
|
|
___udivide:
|
___udivide:
|
or r1,ar1,r2
|
or r1,ar1,r2
|
bne udiv0
|
bne udiv0
|
ldi ar0,r2
|
ldi ar0,r2
|
ldi r0,ar2
|
ldi r0,ar2
|
call udivqi3n
|
call udivqi3n
|
ldiu 0,r1
|
ldiu 0,r1
|
rets
|
rets
|
|
|
___umodulo:
|
___umodulo:
|
or r1,ar1,r2
|
or r1,ar1,r2
|
bne udiv0
|
bne udiv0
|
ldi ar0,r2
|
ldi ar0,r2
|
ldi r0,ar2
|
ldi r0,ar2
|
call umodqi3n
|
call umodqi3n
|
ldi r0,r2
|
ldi r0,r2
|
ldiu 0,r3
|
ldiu 0,r3
|
rets
|
rets
|
|
|
udiv0:
|
udiv0:
|
tstb ar1,ar1
|
tstb ar1,ar1
|
bne udiv1
|
bne udiv1
|
tstb ar0,ar0
|
tstb ar0,ar0
|
bn udiv1
|
bn udiv1
|
|
|
ldiu 63,rc
|
ldiu 63,rc
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
rptbd udivend0
|
rptbd udivend0
|
ldiu 0,r2
|
ldiu 0,r2
|
addi r0,r0
|
addi r0,r0
|
rolc r1
|
rolc r1
|
#else
|
#else
|
ldiu 0,r2
|
ldiu 0,r2
|
addi r0,r0
|
addi r0,r0
|
rolc r1
|
rolc r1
|
rptb udivend0
|
rptb udivend0
|
#endif
|
#endif
|
|
|
rolc r2
|
rolc r2
|
subi3 ar0,r2,r3
|
subi3 ar0,r2,r3
|
ldinc r3,r2
|
ldinc r3,r2
|
rolc r0
|
rolc r0
|
udivend0:
|
udivend0:
|
rolc r1
|
rolc r1
|
|
|
not r0
|
not r0
|
not r1
|
not r1
|
ldiu 0,r3
|
ldiu 0,r3
|
rets
|
rets
|
udiv1:
|
udiv1:
|
push r4
|
push r4
|
push r5
|
push r5
|
ldiu 63,rc
|
ldiu 63,rc
|
ldiu 0,r2
|
ldiu 0,r2
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
rptbd udivend1
|
rptbd udivend1
|
ldiu 0,r3
|
ldiu 0,r3
|
addi r0,r0
|
addi r0,r0
|
rolc r1
|
rolc r1
|
#else
|
#else
|
ldiu 0,r3
|
ldiu 0,r3
|
addi r0,r0
|
addi r0,r0
|
rolc r1
|
rolc r1
|
rptb udivend1
|
rptb udivend1
|
#endif
|
#endif
|
|
|
rolc r2
|
rolc r2
|
rolc r3
|
rolc r3
|
subi3 ar0,r2,r4
|
subi3 ar0,r2,r4
|
subb3 ar1,r3,r5
|
subb3 ar1,r3,r5
|
ldinc r4,r2
|
ldinc r4,r2
|
ldinc r5,r3
|
ldinc r5,r3
|
rolc r0
|
rolc r0
|
udivend1:
|
udivend1:
|
rolc r1
|
rolc r1
|
|
|
not r0
|
not r0
|
not r1
|
not r1
|
pop r5
|
pop r5
|
pop r4
|
pop r4
|
rets
|
rets
|
#endif
|
#endif
|
|
|
;
|
;
|
; Integer 64 by 64 unsigned modulo
|
; Integer 64 by 64 unsigned modulo
|
; long1 and long2 on stack
|
; long1 and long2 on stack
|
; result in r0,r1
|
; result in r0,r1
|
;
|
;
|
#ifdef L_umoddi3
|
#ifdef L_umoddi3
|
.text
|
.text
|
.global ___umodhi3
|
.global ___umodhi3
|
.ref ___modulo
|
.ref ___modulo
|
___umodhi3:
|
___umodhi3:
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi *-ar2(4),ar0
|
ldi *-ar2(4),ar0
|
ldi *-ar2(3),ar1
|
ldi *-ar2(3),ar1
|
ldi *-ar2(2),r0
|
ldi *-ar2(2),r0
|
ldi *-ar2(1),r1
|
ldi *-ar2(1),r1
|
call ___umodulo
|
call ___umodulo
|
pop ar0
|
pop ar0
|
bd ar0
|
bd ar0
|
ldi r2,r0
|
ldi r2,r0
|
ldi r3,r1
|
ldi r3,r1
|
nop
|
nop
|
#endif
|
#endif
|
|
|
;
|
;
|
; Integer 64 by 64 signed divide
|
; Integer 64 by 64 signed divide
|
; long1 and long2 on stack
|
; long1 and long2 on stack
|
; result in r0,r1
|
; result in r0,r1
|
;
|
;
|
#ifdef L_divdi3
|
#ifdef L_divdi3
|
.text
|
.text
|
.global ___divhi3
|
.global ___divhi3
|
.ref ___udivide
|
.ref ___udivide
|
___divhi3:
|
___divhi3:
|
ldi 0,ir0
|
ldi 0,ir0
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi *-ar2(4),r0
|
ldi *-ar2(4),r0
|
ldi *-ar2(3),r1
|
ldi *-ar2(3),r1
|
bge div1
|
bge div1
|
not ir0
|
not ir0
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
div1:
|
div1:
|
ldi r0,ar0
|
ldi r0,ar0
|
ldi r1,ar1
|
ldi r1,ar1
|
ldi *-ar2(2),r0
|
ldi *-ar2(2),r0
|
ldi *-ar2(1),r1
|
ldi *-ar2(1),r1
|
bge div2
|
bge div2
|
not ir0
|
not ir0
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
div2:
|
div2:
|
call ___udivide
|
call ___udivide
|
tstb ir0,ir0
|
tstb ir0,ir0
|
bge div3
|
bge div3
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
div3:
|
div3:
|
rets
|
rets
|
#endif
|
#endif
|
|
|
;
|
;
|
; Integer 64 by 64 signed modulo
|
; Integer 64 by 64 signed modulo
|
; long1 and long2 on stack
|
; long1 and long2 on stack
|
; result in r0,r1
|
; result in r0,r1
|
;
|
;
|
#ifdef L_moddi3
|
#ifdef L_moddi3
|
.text
|
.text
|
.global ___modhi3
|
.global ___modhi3
|
.ref ___umodulo
|
.ref ___umodulo
|
___modhi3:
|
___modhi3:
|
ldi 0,ir0
|
ldi 0,ir0
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi *-ar2(4),r0
|
ldi *-ar2(4),r0
|
ldi *-ar2(3),r1
|
ldi *-ar2(3),r1
|
bge mod1
|
bge mod1
|
not ir0
|
not ir0
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
mod1:
|
mod1:
|
ldi r0,ar0
|
ldi r0,ar0
|
ldi r1,ar1
|
ldi r1,ar1
|
ldi *-ar2(2),r0
|
ldi *-ar2(2),r0
|
ldi *-ar2(1),r1
|
ldi *-ar2(1),r1
|
bge mod2
|
bge mod2
|
not ir0
|
not ir0
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
mod2:
|
mod2:
|
call ___umodulo
|
call ___umodulo
|
ldi r2,r0
|
ldi r2,r0
|
ldi r3,r1
|
ldi r3,r1
|
tstb ir0,ir0
|
tstb ir0,ir0
|
bge mod3
|
bge mod3
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
mod3:
|
mod3:
|
rets
|
rets
|
#endif
|
#endif
|
|
|
;
|
;
|
; double to signed long long conversion
|
; double to signed long long conversion
|
; input in r2
|
; input in r2
|
; result in r0,r1
|
; result in r0,r1
|
;
|
;
|
#ifdef L_fix_truncsfdi2
|
#ifdef L_fix_truncsfdi2
|
.text
|
.text
|
.global ___fix_truncqfhi2
|
.global ___fix_truncqfhi2
|
.ref ufix_truncqfhi2n
|
.ref ufix_truncqfhi2n
|
___fix_truncqfhi2:
|
___fix_truncqfhi2:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldf *-ar0(1), r2
|
ldf *-ar0(1), r2
|
.endif
|
.endif
|
|
|
cmpf 0.0,r2
|
cmpf 0.0,r2
|
bge ufix_truncqfhi2n
|
bge ufix_truncqfhi2n
|
negf r2
|
negf r2
|
call ufix_truncqfhi2n
|
call ufix_truncqfhi2n
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
rets
|
rets
|
#endif
|
#endif
|
|
|
;
|
;
|
; double to unsigned long long conversion
|
; double to unsigned long long conversion
|
; input in r2
|
; input in r2
|
; result in r0,r1
|
; result in r0,r1
|
;
|
;
|
#ifdef L_ufix_truncsfdi2
|
#ifdef L_ufix_truncsfdi2
|
.text
|
.text
|
.global ___ufix_truncqfhi2
|
.global ___ufix_truncqfhi2
|
.global ufix_truncqfhi2n
|
.global ufix_truncqfhi2n
|
___ufix_truncqfhi2:
|
___ufix_truncqfhi2:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldf *-ar0(1), r2
|
ldf *-ar0(1), r2
|
.endif
|
.endif
|
|
|
ufix_truncqfhi2n:
|
ufix_truncqfhi2n:
|
cmpf 0.0,r2
|
cmpf 0.0,r2
|
ble ufix1
|
ble ufix1
|
pushf r2
|
pushf r2
|
pop r3
|
pop r3
|
ash -24,r3
|
ash -24,r3
|
subi 31,r3
|
subi 31,r3
|
cmpi 32,r3
|
cmpi 32,r3
|
bgt ufix1
|
bgt ufix1
|
cmpi -32,r3
|
cmpi -32,r3
|
ble ufix1
|
ble ufix1
|
ldi 1,r0
|
ldi 1,r0
|
ash 31,r0
|
ash 31,r0
|
or3 r0,r2,r0
|
or3 r0,r2,r0
|
ldi r0,r1
|
ldi r0,r1
|
lsh3 r3,r0,r0
|
lsh3 r3,r0,r0
|
subi 32,r3
|
subi 32,r3
|
cmpi -32,r3
|
cmpi -32,r3
|
ldile 0,r1
|
ldile 0,r1
|
lsh3 r3,r1,r1
|
lsh3 r3,r1,r1
|
rets
|
rets
|
ufix1:
|
ufix1:
|
ldi 0,r0
|
ldi 0,r0
|
ldi 0,r1
|
ldi 0,r1
|
rets
|
rets
|
#endif
|
#endif
|
|
|
;
|
;
|
; signed long long to double conversion
|
; signed long long to double conversion
|
; input on stack
|
; input on stack
|
; result in r0
|
; result in r0
|
;
|
;
|
#ifdef L_floatdisf2
|
#ifdef L_floatdisf2
|
.text
|
.text
|
.global ___floathiqf2
|
.global ___floathiqf2
|
.ref ufloathiqf2n
|
.ref ufloathiqf2n
|
___floathiqf2:
|
___floathiqf2:
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi *-ar2(2),r0
|
ldi *-ar2(2),r0
|
ldi *-ar2(1),r1
|
ldi *-ar2(1),r1
|
bge ufloathiqf2n
|
bge ufloathiqf2n
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
call ufloathiqf2n
|
call ufloathiqf2n
|
negf r0
|
negf r0
|
rets
|
rets
|
#endif
|
#endif
|
|
|
;
|
;
|
; unsigned long long to double conversion
|
; unsigned long long to double conversion
|
; input on stack
|
; input on stack
|
; result in r0
|
; result in r0
|
;
|
;
|
#ifdef L_ufloatdisf2
|
#ifdef L_ufloatdisf2
|
.text
|
.text
|
.global ___ufloathiqf2
|
.global ___ufloathiqf2
|
.global ufloathiqf2n
|
.global ufloathiqf2n
|
.ref ___unsfltconst
|
.ref ___unsfltconst
|
___ufloathiqf2:
|
___ufloathiqf2:
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi *-ar2(2),r0
|
ldi *-ar2(2),r0
|
ldi *-ar2(1),r1
|
ldi *-ar2(1),r1
|
ufloathiqf2n:
|
ufloathiqf2n:
|
.if .BIGMODEL
|
.if .BIGMODEL
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
ldpk @___unsfltconst
|
ldpk @___unsfltconst
|
#else
|
#else
|
ldp @___unsfltconst
|
ldp @___unsfltconst
|
#endif
|
#endif
|
.endif
|
.endif
|
ldf @___unsfltconst,r2
|
ldf @___unsfltconst,r2
|
float r0
|
float r0
|
bge uflt1
|
bge uflt1
|
addf r2,r0
|
addf r2,r0
|
uflt1:
|
uflt1:
|
float r1
|
float r1
|
bge uflt2
|
bge uflt2
|
addf r2,r1
|
addf r2,r1
|
uflt2:
|
uflt2:
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
pop r3
|
pop r3
|
bd r3
|
bd r3
|
mpyf r2,r1
|
mpyf r2,r1
|
addf r1,r0
|
addf r1,r0
|
nop
|
nop
|
#else
|
#else
|
ldf r1,r3
|
ldf r1,r3
|
and 0ffh,r3
|
and 0ffh,r3
|
norm r3,r3
|
norm r3,r3
|
mpyf r2,r3
|
mpyf r2,r3
|
pop ar2
|
pop ar2
|
bd ar2
|
bd ar2
|
addf r3,r0
|
addf r3,r0
|
mpyf r2,r1
|
mpyf r2,r1
|
addf r1,r0
|
addf r1,r0
|
#endif
|
#endif
|
#endif
|
#endif
|
|
|
;
|
;
|
; long double to signed long long conversion
|
; long double to signed long long conversion
|
; input in r2
|
; input in r2
|
; result in r0,r1
|
; result in r0,r1
|
;
|
;
|
#ifdef L_fix_truncdfdi2
|
#ifdef L_fix_truncdfdi2
|
.text
|
.text
|
.global ___fix_trunchfhi2
|
.global ___fix_trunchfhi2
|
.ref ufix_trunchfhi2n
|
.ref ufix_trunchfhi2n
|
___fix_trunchfhi2:
|
___fix_trunchfhi2:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldf *-ar0(2), r2
|
ldf *-ar0(2), r2
|
ldi *-ar0(1), r2
|
ldi *-ar0(1), r2
|
.endif
|
.endif
|
|
|
cmpf 0.0,r2
|
cmpf 0.0,r2
|
bge ufix_trunchfhi2n
|
bge ufix_trunchfhi2n
|
negf r2
|
negf r2
|
call ufix_trunchfhi2n
|
call ufix_trunchfhi2n
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
rets
|
rets
|
#endif
|
#endif
|
|
|
;
|
;
|
; long double to unsigned long long conversion
|
; long double to unsigned long long conversion
|
; input in r2
|
; input in r2
|
; result in r0,r1
|
; result in r0,r1
|
;
|
;
|
#ifdef L_ufix_truncdfdi2
|
#ifdef L_ufix_truncdfdi2
|
.text
|
.text
|
.global ___ufix_trunchfhi2
|
.global ___ufix_trunchfhi2
|
.global ufix_trunchfhi2n
|
.global ufix_trunchfhi2n
|
___ufix_trunchfhi2:
|
___ufix_trunchfhi2:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldf *-ar0(2), r2
|
ldf *-ar0(2), r2
|
ldi *-ar0(1), r2
|
ldi *-ar0(1), r2
|
.endif
|
.endif
|
|
|
ufix_trunchfhi2n:
|
ufix_trunchfhi2n:
|
cmpf 0.0,r2
|
cmpf 0.0,r2
|
ble ufixh1
|
ble ufixh1
|
pushf r2
|
pushf r2
|
pop r3
|
pop r3
|
ash -24,r3
|
ash -24,r3
|
subi 31,r3
|
subi 31,r3
|
cmpi 32,r3
|
cmpi 32,r3
|
bgt ufixh1
|
bgt ufixh1
|
cmpi -32,r3
|
cmpi -32,r3
|
ble ufixh1
|
ble ufixh1
|
ldi 1,r0
|
ldi 1,r0
|
ash 31,r0
|
ash 31,r0
|
or3 r0,r2,r0
|
or3 r0,r2,r0
|
ldi r0,r1
|
ldi r0,r1
|
lsh3 r3,r0,r0
|
lsh3 r3,r0,r0
|
subi 32,r3
|
subi 32,r3
|
cmpi -32,r3
|
cmpi -32,r3
|
ldile 0,r1
|
ldile 0,r1
|
lsh3 r3,r1,r1
|
lsh3 r3,r1,r1
|
rets
|
rets
|
ufixh1:
|
ufixh1:
|
ldi 0,r0
|
ldi 0,r0
|
ldi 0,r1
|
ldi 0,r1
|
rets
|
rets
|
#endif
|
#endif
|
|
|
;
|
;
|
; signed long long to long double conversion
|
; signed long long to long double conversion
|
; input on stack
|
; input on stack
|
; result in r0
|
; result in r0
|
;
|
;
|
#ifdef L_floatdidf2
|
#ifdef L_floatdidf2
|
.text
|
.text
|
.global ___floathihf2
|
.global ___floathihf2
|
.ref ufloathihf2n
|
.ref ufloathihf2n
|
___floathihf2:
|
___floathihf2:
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi *-ar2(2),r0
|
ldi *-ar2(2),r0
|
ldi *-ar2(1),r1
|
ldi *-ar2(1),r1
|
bge ufloathihf2n
|
bge ufloathihf2n
|
negi r0
|
negi r0
|
negb r1
|
negb r1
|
call ufloathihf2n
|
call ufloathihf2n
|
negf r0
|
negf r0
|
rets
|
rets
|
#endif
|
#endif
|
|
|
;
|
;
|
; unsigned long long to double conversion
|
; unsigned long long to double conversion
|
; input on stack
|
; input on stack
|
; result in r0
|
; result in r0
|
;
|
;
|
#ifdef L_ufloatdidf2
|
#ifdef L_ufloatdidf2
|
.text
|
.text
|
.global ___ufloathihf2
|
.global ___ufloathihf2
|
.global ufloathihf2n
|
.global ufloathihf2n
|
.ref ___unsfltconst
|
.ref ___unsfltconst
|
___ufloathihf2:
|
___ufloathihf2:
|
ldi sp,ar2
|
ldi sp,ar2
|
ldi *-ar2(2),r0
|
ldi *-ar2(2),r0
|
ldi *-ar2(1),r1
|
ldi *-ar2(1),r1
|
ufloathihf2n
|
ufloathihf2n
|
.if .BIGMODEL
|
.if .BIGMODEL
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
ldpk @___unsfltconst
|
ldpk @___unsfltconst
|
#else
|
#else
|
ldp @___unsfltconst
|
ldp @___unsfltconst
|
#endif
|
#endif
|
.endif
|
.endif
|
ldf @___unsfltconst,r2
|
ldf @___unsfltconst,r2
|
float r0
|
float r0
|
bge uflth1
|
bge uflth1
|
addf r2,r0
|
addf r2,r0
|
uflth1:
|
uflth1:
|
float r1
|
float r1
|
bge uflth2
|
bge uflth2
|
addf r2,r1
|
addf r2,r1
|
uflth2:
|
uflth2:
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
pop r3
|
pop r3
|
bd r3
|
bd r3
|
mpyf r2,r1
|
mpyf r2,r1
|
addf r1,r0
|
addf r1,r0
|
nop
|
nop
|
#else
|
#else
|
ldf r1,r3
|
ldf r1,r3
|
and 0ffh,r3
|
and 0ffh,r3
|
norm r3,r3
|
norm r3,r3
|
mpyf r2,r3
|
mpyf r2,r3
|
pop ar2
|
pop ar2
|
bd ar2
|
bd ar2
|
addf r3,r0
|
addf r3,r0
|
mpyf r2,r1
|
mpyf r2,r1
|
addf r1,r0
|
addf r1,r0
|
#endif
|
#endif
|
#endif
|
#endif
|
|
|
;
|
;
|
; calculate ffs
|
; calculate ffs
|
; input in ar2
|
; input in ar2
|
; result in r0
|
; result in r0
|
;
|
;
|
#ifdef L_ffs
|
#ifdef L_ffs
|
.global ___ffs
|
.global ___ffs
|
.ref ___unsfltconst
|
.ref ___unsfltconst
|
.text
|
.text
|
___ffs:
|
___ffs:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldi *-ar0(1), ar2
|
ldi *-ar0(1), ar2
|
.endif
|
.endif
|
|
|
negi ar2,r0
|
negi ar2,r0
|
and ar2,r0
|
and ar2,r0
|
float r0,r0
|
float r0,r0
|
ldfu 0.0,r1
|
ldfu 0.0,r1
|
.if .BIGMODEL
|
.if .BIGMODEL
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
ldpk @___unsfltconst
|
ldpk @___unsfltconst
|
#else
|
#else
|
ldp @___unsfltconst
|
ldp @___unsfltconst
|
#endif
|
#endif
|
.endif
|
.endif
|
ldflt @___unsfltconst,r1
|
ldflt @___unsfltconst,r1
|
addf r1,r0
|
addf r1,r0
|
pushf r0
|
pushf r0
|
pop r0
|
pop r0
|
pop ar0
|
pop ar0
|
bd ar0
|
bd ar0
|
ash -24,r0
|
ash -24,r0
|
ldilt -1,r0
|
ldilt -1,r0
|
addi 1,r0
|
addi 1,r0
|
#endif
|
#endif
|
|
|
;
|
;
|
; calculate long double * long double
|
; calculate long double * long double
|
; input in r2, r3
|
; input in r2, r3
|
; output in r0
|
; output in r0
|
;
|
;
|
#ifdef L_muldf3
|
#ifdef L_muldf3
|
.global ___mulhf3
|
.global ___mulhf3
|
.text
|
.text
|
___mulhf3:
|
___mulhf3:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldf *-ar0(2), r2
|
ldf *-ar0(2), r2
|
ldi *-ar0(1), r2
|
ldi *-ar0(1), r2
|
ldf *-ar0(4), r3
|
ldf *-ar0(4), r3
|
ldi *-ar0(3), r3
|
ldi *-ar0(3), r3
|
.endif
|
.endif
|
|
|
pop ar2 ; return ad
|
pop ar2 ; return ad
|
ldf r2,r0 ; copy lsb0
|
ldf r2,r0 ; copy lsb0
|
ldf r3,r1 ; copy lsb1
|
ldf r3,r1 ; copy lsb1
|
and 0ffh,r0 ; mask lsb0
|
and 0ffh,r0 ; mask lsb0
|
and 0ffh,r1 ; mask lsb1
|
and 0ffh,r1 ; mask lsb1
|
norm r0,r0 ; correct lsb0
|
norm r0,r0 ; correct lsb0
|
norm r1,r1 ; correct lsb1
|
norm r1,r1 ; correct lsb1
|
mpyf r2,r1 ; arg0*lsb1
|
mpyf r2,r1 ; arg0*lsb1
|
mpyf r3,r0 ; arg1*lsb0
|
mpyf r3,r0 ; arg1*lsb0
|
bd ar2 ; return (delayed)
|
bd ar2 ; return (delayed)
|
addf r0,r1 ; arg0*lsb1 + arg1*lsb0
|
addf r0,r1 ; arg0*lsb1 + arg1*lsb0
|
mpyf r2,r3,r0 ; msb0*msb1
|
mpyf r2,r3,r0 ; msb0*msb1
|
addf r1,r0 ; msb0*msb1 + arg0*lsb1 + arg1*lsb0
|
addf r1,r0 ; msb0*msb1 + arg0*lsb1 + arg1*lsb0
|
#endif
|
#endif
|
|
|
;
|
;
|
; calculate long double / long double
|
; calculate long double / long double
|
; r2 dividend, r3 divisor, r0 quotient
|
; r2 dividend, r3 divisor, r0 quotient
|
;
|
;
|
#ifdef L_divdf3
|
#ifdef L_divdf3
|
.global ___divhf3
|
.global ___divhf3
|
.text
|
.text
|
___divhf3:
|
___divhf3:
|
.if .REGPARM == 0
|
.if .REGPARM == 0
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
lda sp,ar0
|
lda sp,ar0
|
#else
|
#else
|
ldiu sp,ar0
|
ldiu sp,ar0
|
#endif
|
#endif
|
ldf *-ar0(2), r2
|
ldf *-ar0(2), r2
|
ldi *-ar0(1), r2
|
ldi *-ar0(1), r2
|
ldf *-ar0(4), r3
|
ldf *-ar0(4), r3
|
ldi *-ar0(3), r3
|
ldi *-ar0(3), r3
|
.endif
|
.endif
|
|
|
#ifdef _TMS320C4x
|
#ifdef _TMS320C4x
|
pop ar1
|
pop ar1
|
rcpf r3, r0
|
rcpf r3, r0
|
mpyf3 r0, r3, r1
|
mpyf3 r0, r3, r1
|
subrf 2.0, r1
|
subrf 2.0, r1
|
mpyf r1, r0
|
mpyf r1, r0
|
mpyf3 r0, r3, r1
|
mpyf3 r0, r3, r1
|
bud ar1
|
bud ar1
|
subrf 2.0, r1
|
subrf 2.0, r1
|
mpyf r1, r0
|
mpyf r1, r0
|
mpyf r2, r0
|
mpyf r2, r0
|
#else
|
#else
|
pop ar1
|
pop ar1
|
pushf r3
|
pushf r3
|
pop r0
|
pop r0
|
not r0
|
not r0
|
push r0
|
push r0
|
popf r0
|
popf r0
|
ldf -1.0, r1
|
ldf -1.0, r1
|
xor r1, r0
|
xor r1, r0
|
|
|
mpyf3 r0, r3, r1 ; r1 = r[0] * v
|
mpyf3 r0, r3, r1 ; r1 = r[0] * v
|
subrf 2.0, r1 ; r1 = 2.0 - r[0] * v
|
subrf 2.0, r1 ; r1 = 2.0 - r[0] * v
|
mpyf r1, r0 ; r0 = r[0] * (2.0 - r[0] * v) = r[1]
|
mpyf r1, r0 ; r0 = r[0] * (2.0 - r[0] * v) = r[1]
|
; End of 1st iteration
|
; End of 1st iteration
|
|
|
mpyf3 r0, r3, r1 ; r1 = r[1] * v
|
mpyf3 r0, r3, r1 ; r1 = r[1] * v
|
subrf 2.0, r1 ; r1 = 2.0 - r[1] * v
|
subrf 2.0, r1 ; r1 = 2.0 - r[1] * v
|
mpyf r1, r0 ; r0 = r[1] * (2.0 - r[1] * v) = r[2]
|
mpyf r1, r0 ; r0 = r[1] * (2.0 - r[1] * v) = r[2]
|
; End of 2nd iteration
|
; End of 2nd iteration
|
|
|
mpyf3 r0, r3, r1 ; r1 = r[2] * v
|
mpyf3 r0, r3, r1 ; r1 = r[2] * v
|
subrf 2.0, r1 ; r1 = 2.0 - r[2] * v
|
subrf 2.0, r1 ; r1 = 2.0 - r[2] * v
|
mpyf r1, r0 ; r0 = r[2] * (2.0 - r[2] * v) = r[3]
|
mpyf r1, r0 ; r0 = r[2] * (2.0 - r[2] * v) = r[3]
|
; End of 3rd iteration
|
; End of 3rd iteration
|
|
|
or 080h, r0
|
or 080h, r0
|
rnd r0
|
rnd r0
|
|
|
; mpyf3 r0, r3, r1 ; r1 = r[3] * v
|
; mpyf3 r0, r3, r1 ; r1 = r[3] * v
|
push r4
|
push r4
|
pushf r4
|
pushf r4
|
mpyf r0, r3, r1
|
mpyf r0, r3, r1
|
|
|
ldf r0, r4
|
ldf r0, r4
|
and 0ffh, r4
|
and 0ffh, r4
|
norm r4, r4
|
norm r4, r4
|
mpyf r3, r4
|
mpyf r3, r4
|
addf r4, r1
|
addf r4, r1
|
|
|
ldf r3, r4
|
ldf r3, r4
|
and 0ffh, r4
|
and 0ffh, r4
|
norm r4, r4
|
norm r4, r4
|
mpyf r0, r4
|
mpyf r0, r4
|
addf r4, r1
|
addf r4, r1
|
|
|
subrf 2.0, r1 ; r1 = 2.0 - r[3] * v
|
subrf 2.0, r1 ; r1 = 2.0 - r[3] * v
|
|
|
mpyf r1, r0, r3 ; r3 = r[3] * (2.0 - r[3] * v) = r[5]
|
mpyf r1, r0, r3 ; r3 = r[3] * (2.0 - r[3] * v) = r[5]
|
|
|
ldf r1, r4
|
ldf r1, r4
|
and 0ffh, r4
|
and 0ffh, r4
|
norm r4, r4
|
norm r4, r4
|
mpyf r0, r4
|
mpyf r0, r4
|
addf r4, r3
|
addf r4, r3
|
|
|
ldf r0, r4
|
ldf r0, r4
|
and 0ffh, r4
|
and 0ffh, r4
|
norm r4, r4
|
norm r4, r4
|
mpyf r1, r4
|
mpyf r1, r4
|
addf r4, r3
|
addf r4, r3
|
|
|
mpyf r2, r3, r0 ; Multiply by the dividend
|
mpyf r2, r3, r0 ; Multiply by the dividend
|
|
|
ldf r2, r4
|
ldf r2, r4
|
and 0ffh, r4
|
and 0ffh, r4
|
norm r4, r4
|
norm r4, r4
|
mpyf r3, r4
|
mpyf r3, r4
|
addf r4, r0
|
addf r4, r0
|
|
|
ldf r3, r4
|
ldf r3, r4
|
and 0ffh, r4
|
and 0ffh, r4
|
norm r4, r4
|
norm r4, r4
|
mpyf r2, r4
|
mpyf r2, r4
|
bd ar1
|
bd ar1
|
addf r4, r0
|
addf r4, r0
|
|
|
popf r4
|
popf r4
|
pop r4
|
pop r4
|
#endif
|
#endif
|
#endif
|
#endif
|
|
|
