/* Target Definitions for R8C/M16C/M32C
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/* Target Definitions for R8C/M16C/M32C
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Copyright (C) 2005, 2007
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Copyright (C) 2005, 2007
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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Contributed by Red Hat.
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Contributed by Red Hat.
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This file is part of GCC.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_M32C_H
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#ifndef GCC_M32C_H
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#define GCC_M32C_H
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#define GCC_M32C_H
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/* Controlling the Compilation Driver, `gcc'. */
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/* Controlling the Compilation Driver, `gcc'. */
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#undef STARTFILE_SPEC
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#undef STARTFILE_SPEC
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#define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
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#define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
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/* There are four CPU series we support, but they basically break down
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/* There are four CPU series we support, but they basically break down
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into two families - the R8C/M16C families, with 16 bit address
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into two families - the R8C/M16C families, with 16 bit address
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registers and one set of opcodes, and the M32CM/M32C group, with 24
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registers and one set of opcodes, and the M32CM/M32C group, with 24
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bit address registers and a different set of opcodes. The
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bit address registers and a different set of opcodes. The
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assembler doesn't care except for which opcode set is needed; the
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assembler doesn't care except for which opcode set is needed; the
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big difference is in the memory maps, which we cover in
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big difference is in the memory maps, which we cover in
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LIB_SPEC. */
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LIB_SPEC. */
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#undef ASM_SPEC
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#undef ASM_SPEC
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#define ASM_SPEC "\
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#define ASM_SPEC "\
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%{mcpu=r8c:--m16c} \
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%{mcpu=r8c:--m16c} \
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%{mcpu=m16c:--m16c} \
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%{mcpu=m16c:--m16c} \
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%{mcpu=m32cm:--m32c} \
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%{mcpu=m32cm:--m32c} \
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%{mcpu=m32c:--m32c} "
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%{mcpu=m32c:--m32c} "
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|
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/* The default is R8C hardware. We support a simulator, which has its
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/* The default is R8C hardware. We support a simulator, which has its
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own libgloss and link map, plus one default link map for each chip
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own libgloss and link map, plus one default link map for each chip
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family. Most of the logic here is making sure we do the right
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family. Most of the logic here is making sure we do the right
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thing when no CPU is specified, which defaults to R8C. */
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thing when no CPU is specified, which defaults to R8C. */
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#undef LIB_SPEC
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#undef LIB_SPEC
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#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
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#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
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%{msim*:%{!T*: %{mcpu=m32cm:-Tsim24.ld}%{mcpu=m32c:-Tsim24.ld} \
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%{msim*:%{!T*: %{mcpu=m32cm:-Tsim24.ld}%{mcpu=m32c:-Tsim24.ld} \
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%{!mcpu=m32cm:%{!mcpu=m32c:-Tsim16.ld}}}} \
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%{!mcpu=m32cm:%{!mcpu=m32c:-Tsim16.ld}}}} \
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%{!T*:%{!msim*: %{mcpu=m16c:-Tm16c.ld} \
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%{!T*:%{!msim*: %{mcpu=m16c:-Tm16c.ld} \
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%{mcpu=m32cm:-Tm32cm.ld} \
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%{mcpu=m32cm:-Tm32cm.ld} \
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%{mcpu=m32c:-Tm32c.ld} \
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%{mcpu=m32c:-Tm32c.ld} \
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%{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:-Tr8c.ld}}}}} \
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%{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:-Tr8c.ld}}}}} \
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"
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"
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/* Run-time Target Specification */
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/* Run-time Target Specification */
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/* Nothing unusual here. */
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/* Nothing unusual here. */
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#define TARGET_CPU_CPP_BUILTINS() \
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#define TARGET_CPU_CPP_BUILTINS() \
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{ \
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{ \
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builtin_assert ("cpu=m32c"); \
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builtin_assert ("cpu=m32c"); \
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builtin_assert ("machine=m32c"); \
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builtin_assert ("machine=m32c"); \
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builtin_define ("__m32c__=1"); \
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builtin_define ("__m32c__=1"); \
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if (TARGET_R8C) \
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if (TARGET_R8C) \
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builtin_define ("__r8c_cpu__=1"); \
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builtin_define ("__r8c_cpu__=1"); \
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if (TARGET_M16C) \
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if (TARGET_M16C) \
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builtin_define ("__m16c_cpu__=1"); \
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builtin_define ("__m16c_cpu__=1"); \
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if (TARGET_M32CM) \
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if (TARGET_M32CM) \
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builtin_define ("__m32cm_cpu__=1"); \
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builtin_define ("__m32cm_cpu__=1"); \
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if (TARGET_M32C) \
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if (TARGET_M32C) \
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builtin_define ("__m32c_cpu__=1"); \
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builtin_define ("__m32c_cpu__=1"); \
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}
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}
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/* The pragma handlers need to know if we've started processing
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/* The pragma handlers need to know if we've started processing
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functions yet, as the memregs pragma should only be given at the
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functions yet, as the memregs pragma should only be given at the
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beginning of the file. This variable starts off TRUE and later
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beginning of the file. This variable starts off TRUE and later
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becomes FALSE. */
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becomes FALSE. */
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extern int ok_to_change_target_memregs;
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extern int ok_to_change_target_memregs;
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extern int target_memregs;
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extern int target_memregs;
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/* TARGET_CPU is a multi-way option set in m32c.opt. While we could
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/* TARGET_CPU is a multi-way option set in m32c.opt. While we could
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use enums or defines for this, this and m32c.opt are the only
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use enums or defines for this, this and m32c.opt are the only
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places that know (or care) what values are being used. */
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places that know (or care) what values are being used. */
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#define TARGET_R8C (target_cpu == 'r')
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#define TARGET_R8C (target_cpu == 'r')
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#define TARGET_M16C (target_cpu == '6')
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#define TARGET_M16C (target_cpu == '6')
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#define TARGET_M32CM (target_cpu == 'm')
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#define TARGET_M32CM (target_cpu == 'm')
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#define TARGET_M32C (target_cpu == '3')
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#define TARGET_M32C (target_cpu == '3')
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/* Address register sizes. Warning: these are used all over the place
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/* Address register sizes. Warning: these are used all over the place
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to select between the two CPU families in general. */
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to select between the two CPU families in general. */
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#define TARGET_A16 (TARGET_R8C || TARGET_M16C)
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#define TARGET_A16 (TARGET_R8C || TARGET_M16C)
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#define TARGET_A24 (TARGET_M32CM || TARGET_M32C)
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#define TARGET_A24 (TARGET_M32CM || TARGET_M32C)
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#define TARGET_VERSION fprintf (stderr, " (m32c)");
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#define TARGET_VERSION fprintf (stderr, " (m32c)");
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#define OVERRIDE_OPTIONS m32c_override_options ();
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#define OVERRIDE_OPTIONS m32c_override_options ();
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/* Defining data structures for per-function information */
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/* Defining data structures for per-function information */
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typedef struct machine_function GTY (())
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typedef struct machine_function GTY (())
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{
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{
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/* How much we adjust the stack when returning from an exception
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/* How much we adjust the stack when returning from an exception
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handler. */
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handler. */
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rtx eh_stack_adjust;
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rtx eh_stack_adjust;
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/* TRUE if the current function is an interrupt handler. */
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/* TRUE if the current function is an interrupt handler. */
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int is_interrupt;
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int is_interrupt;
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/* TRUE if the current function is a leaf function. Currently, this
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/* TRUE if the current function is a leaf function. Currently, this
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only affects saving $a0 in interrupt functions. */
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only affects saving $a0 in interrupt functions. */
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int is_leaf;
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int is_leaf;
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/* Bitmask that keeps track of which registers are used in an
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/* Bitmask that keeps track of which registers are used in an
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interrupt function, so we know which ones need to be saved and
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interrupt function, so we know which ones need to be saved and
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restored. */
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restored. */
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int intr_pushm;
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int intr_pushm;
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/* Likewise, one element for each memreg that needs to be saved. */
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/* Likewise, one element for each memreg that needs to be saved. */
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char intr_pushmem[16];
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char intr_pushmem[16];
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/* TRUE if the current function can use a simple RTS to return, instead
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/* TRUE if the current function can use a simple RTS to return, instead
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of the longer ENTER/EXIT pair. */
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of the longer ENTER/EXIT pair. */
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int use_rts;
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int use_rts;
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}
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}
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machine_function;
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machine_function;
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#define INIT_EXPANDERS m32c_init_expanders ()
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#define INIT_EXPANDERS m32c_init_expanders ()
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/* Storage Layout */
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/* Storage Layout */
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#define BITS_BIG_ENDIAN 0
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#define BITS_BIG_ENDIAN 0
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#define BYTES_BIG_ENDIAN 0
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#define BYTES_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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/* We can do QI, HI, and SI operations pretty much equally well, but
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/* We can do QI, HI, and SI operations pretty much equally well, but
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GCC expects us to have a "native" format, so we pick the one that
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GCC expects us to have a "native" format, so we pick the one that
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matches "int". Pointers are 16 bits for R8C/M16C (when TARGET_A16
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matches "int". Pointers are 16 bits for R8C/M16C (when TARGET_A16
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is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
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is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
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24 bit pointers are stored in 32 bit words. */
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24 bit pointers are stored in 32 bit words. */
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#define BITS_PER_UNIT 8
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#define BITS_PER_UNIT 8
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#define UNITS_PER_WORD 2
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#define UNITS_PER_WORD 2
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#define POINTER_SIZE (TARGET_A16 ? 16 : 32)
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#define POINTER_SIZE (TARGET_A16 ? 16 : 32)
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#define POINTERS_EXTEND_UNSIGNED 1
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#define POINTERS_EXTEND_UNSIGNED 1
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/* These match the alignment enforced by the two types of stack operations. */
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/* These match the alignment enforced by the two types of stack operations. */
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#define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
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#define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
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#define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
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#define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
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/* We do this because we care more about space than about speed. For
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/* We do this because we care more about space than about speed. For
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the chips with 16 bit busses, we could set these to 16 if
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the chips with 16 bit busses, we could set these to 16 if
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desired. */
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desired. */
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#define FUNCTION_BOUNDARY 8
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#define FUNCTION_BOUNDARY 8
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#define BIGGEST_ALIGNMENT 8
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#define BIGGEST_ALIGNMENT 8
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#define STRICT_ALIGNMENT 0
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#define STRICT_ALIGNMENT 0
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#define SLOW_BYTE_ACCESS 1
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#define SLOW_BYTE_ACCESS 1
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/* Layout of Source Language Data Types */
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/* Layout of Source Language Data Types */
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#define INT_TYPE_SIZE 16
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#define INT_TYPE_SIZE 16
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#define SHORT_TYPE_SIZE 16
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#define SHORT_TYPE_SIZE 16
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#define LONG_TYPE_SIZE 32
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#define LONG_TYPE_SIZE 32
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#define LONG_LONG_TYPE_SIZE 64
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#define LONG_LONG_TYPE_SIZE 64
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#define FLOAT_TYPE_SIZE 32
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#define FLOAT_TYPE_SIZE 32
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#define DOUBLE_TYPE_SIZE 64
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#define DOUBLE_TYPE_SIZE 64
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#define LONG_DOUBLE_TYPE_SIZE 64
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#define LONG_DOUBLE_TYPE_SIZE 64
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#define DEFAULT_SIGNED_CHAR 1
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#define DEFAULT_SIGNED_CHAR 1
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#undef PTRDIFF_TYPE
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#undef PTRDIFF_TYPE
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#define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
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#define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
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/* REGISTER USAGE */
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/* REGISTER USAGE */
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/* Register Basics */
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/* Register Basics */
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/* Register layout:
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/* Register layout:
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[r0h][r0l] $r0 (16 bits, or two 8 bit halves)
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[r0h][r0l] $r0 (16 bits, or two 8 bit halves)
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[--------] $r2 (16 bits)
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[--------] $r2 (16 bits)
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[r1h][r1l] $r1 (16 bits, or two 8 bit halves)
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[r1h][r1l] $r1 (16 bits, or two 8 bit halves)
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[--------] $r3 (16 bits)
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[--------] $r3 (16 bits)
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[---][--------] $a0 (might be 24 bits)
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[---][--------] $a0 (might be 24 bits)
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[---][--------] $a1 (might be 24 bits)
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[---][--------] $a1 (might be 24 bits)
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[---][--------] $sb (might be 24 bits)
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[---][--------] $sb (might be 24 bits)
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[---][--------] $fb (might be 24 bits)
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[---][--------] $fb (might be 24 bits)
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[---][--------] $sp (might be 24 bits)
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[---][--------] $sp (might be 24 bits)
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[-------------] $pc (20 or 24 bits)
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[-------------] $pc (20 or 24 bits)
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[---] $flg (CPU flags)
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[---] $flg (CPU flags)
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[---][--------] $argp (virtual)
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[---][--------] $argp (virtual)
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[--------] $mem0 (all 16 bits)
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[--------] $mem0 (all 16 bits)
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. . .
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. . .
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[--------] $mem14
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[--------] $mem14
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*/
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*/
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#define FIRST_PSEUDO_REGISTER 20
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#define FIRST_PSEUDO_REGISTER 20
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/* Note that these two tables are modified based on which CPU family
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/* Note that these two tables are modified based on which CPU family
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you select; see m32c_conditional_register_usage for details. */
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you select; see m32c_conditional_register_usage for details. */
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/* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
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/* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
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#define FIXED_REGISTERS { 0, 0, 0, 0, \
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#define FIXED_REGISTERS { 0, 0, 0, 0, \
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0, 0, 1, 0, \
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0, 0, 1, 0, \
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1, 1, 0, 1, \
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1, 1, 0, 1, \
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0, 0, 0, 0, 0, 0, 0, 0 }
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0, 0, 0, 0, 0, 0, 0, 0 }
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#define CALL_USED_REGISTERS { 1, 1, 1, 1, \
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#define CALL_USED_REGISTERS { 1, 1, 1, 1, \
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1, 1, 1, 0, \
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1, 1, 1, 0, \
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1, 1, 1, 1, \
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1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1 }
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1, 1, 1, 1, 1, 1, 1, 1 }
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#define CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage ();
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#define CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage ();
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/* The *_REGNO theme matches m32c.md and most register number
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/* The *_REGNO theme matches m32c.md and most register number
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arguments; the PC_REGNUM is the odd one out. */
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arguments; the PC_REGNUM is the odd one out. */
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#ifndef PC_REGNO
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#ifndef PC_REGNO
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#define PC_REGNO 9
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#define PC_REGNO 9
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#endif
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#endif
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#define PC_REGNUM PC_REGNO
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#define PC_REGNUM PC_REGNO
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/* Order of Allocation of Registers */
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/* Order of Allocation of Registers */
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#define REG_ALLOC_ORDER { \
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#define REG_ALLOC_ORDER { \
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0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
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0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
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12, 13, 14, 15, 16, 17, 18, /* mem0..mem7 */ \
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12, 13, 14, 15, 16, 17, 18, /* mem0..mem7 */ \
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6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
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6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
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|
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/* How Values Fit in Registers */
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/* How Values Fit in Registers */
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#define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
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#define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
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#define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
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#define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
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#define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
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#define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
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#define AVOID_CCMODE_COPIES
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#define AVOID_CCMODE_COPIES
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|
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/* Register Classes */
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/* Register Classes */
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|
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/* Most registers are special purpose in some form or another, so this
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/* Most registers are special purpose in some form or another, so this
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table is pretty big. Class names are used for constraints also;
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table is pretty big. Class names are used for constraints also;
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for example the HL_REGS class (HL below) is "Rhl" in the md files.
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for example the HL_REGS class (HL below) is "Rhl" in the md files.
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See m32c_reg_class_from_constraint for the mapping. There's some
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See m32c_reg_class_from_constraint for the mapping. There's some
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duplication so that we can better isolate the reason for using
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duplication so that we can better isolate the reason for using
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constraints in the md files from the actual registers used; for
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constraints in the md files from the actual registers used; for
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example we may want to exclude a1a0 from SI_REGS in the future,
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example we may want to exclude a1a0 from SI_REGS in the future,
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without precluding their use as HImode registers. */
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without precluding their use as HImode registers. */
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|
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/* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
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/* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
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/* mmPAR */
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/* mmPAR */
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#define REG_CLASS_CONTENTS \
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#define REG_CLASS_CONTENTS \
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{ { 0x00000000 }, /* NO */\
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{ { 0x00000000 }, /* NO */\
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{ 0x00000100 }, /* SP - sp */\
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{ 0x00000100 }, /* SP - sp */\
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{ 0x00000080 }, /* FB - fb */\
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{ 0x00000080 }, /* FB - fb */\
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{ 0x00000040 }, /* SB - sb */\
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{ 0x00000040 }, /* SB - sb */\
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{ 0x000001c0 }, /* CR - sb fb sp */\
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{ 0x000001c0 }, /* CR - sb fb sp */\
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{ 0x00000001 }, /* R0 - r0 */\
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{ 0x00000001 }, /* R0 - r0 */\
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{ 0x00000004 }, /* R1 - r1 */\
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{ 0x00000004 }, /* R1 - r1 */\
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{ 0x00000002 }, /* R2 - r2 */\
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{ 0x00000002 }, /* R2 - r2 */\
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{ 0x00000008 }, /* R3 - r3 */\
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{ 0x00000008 }, /* R3 - r3 */\
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{ 0x00000003 }, /* R02 - r0r2 */\
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{ 0x00000003 }, /* R02 - r0r2 */\
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{ 0x00000005 }, /* HL - r0 r1 */\
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{ 0x00000005 }, /* HL - r0 r1 */\
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{ 0x00000005 }, /* QI - r0 r1 */\
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{ 0x00000005 }, /* QI - r0 r1 */\
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{ 0x0000000a }, /* R23 - r2 r3 */\
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{ 0x0000000a }, /* R23 - r2 r3 */\
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{ 0x0000000f }, /* R03 - r0r2 r1r3 */\
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{ 0x0000000f }, /* R03 - r0r2 r1r3 */\
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{ 0x0000000f }, /* DI - r0r2r1r3 + mems */\
|
{ 0x0000000f }, /* DI - r0r2r1r3 + mems */\
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{ 0x00000010 }, /* A0 - a0 */\
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{ 0x00000010 }, /* A0 - a0 */\
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{ 0x00000020 }, /* A1 - a1 */\
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{ 0x00000020 }, /* A1 - a1 */\
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{ 0x00000030 }, /* A - a0 a1 */\
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{ 0x00000030 }, /* A - a0 a1 */\
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{ 0x000000f0 }, /* AD - a0 a1 sb fp */\
|
{ 0x000000f0 }, /* AD - a0 a1 sb fp */\
|
{ 0x000001f0 }, /* PS - a0 a1 sb fp sp */\
|
{ 0x000001f0 }, /* PS - a0 a1 sb fp sp */\
|
{ 0x0000000f }, /* SI - r0r2 r1r3 a0a1 */\
|
{ 0x0000000f }, /* SI - r0r2 r1r3 a0a1 */\
|
{ 0x0000003f }, /* HI - r0 r1 r2 r3 a0 a1 */\
|
{ 0x0000003f }, /* HI - r0 r1 r2 r3 a0 a1 */\
|
{ 0x0000003f }, /* RA - r0..r3 a0 a1 */\
|
{ 0x0000003f }, /* RA - r0..r3 a0 a1 */\
|
{ 0x0000007f }, /* GENERAL */\
|
{ 0x0000007f }, /* GENERAL */\
|
{ 0x00000400 }, /* FLG */\
|
{ 0x00000400 }, /* FLG */\
|
{ 0x000001ff }, /* HC - r0l r1 r2 r3 a0 a1 sb fb sp */\
|
{ 0x000001ff }, /* HC - r0l r1 r2 r3 a0 a1 sb fb sp */\
|
{ 0x000ff000 }, /* MEM */\
|
{ 0x000ff000 }, /* MEM */\
|
{ 0x000ff003 }, /* R02_A_MEM */\
|
{ 0x000ff003 }, /* R02_A_MEM */\
|
{ 0x000ff005 }, /* A_HL_MEM */\
|
{ 0x000ff005 }, /* A_HL_MEM */\
|
{ 0x000ff00c }, /* R1_R3_A_MEM */\
|
{ 0x000ff00c }, /* R1_R3_A_MEM */\
|
{ 0x000ff00f }, /* R03_MEM */\
|
{ 0x000ff00f }, /* R03_MEM */\
|
{ 0x000ff03f }, /* A_HI_MEM */\
|
{ 0x000ff03f }, /* A_HI_MEM */\
|
{ 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
|
{ 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
|
{ 0x000ff1ff }, /* ALL */\
|
{ 0x000ff1ff }, /* ALL */\
|
}
|
}
|
|
|
enum reg_class
|
enum reg_class
|
{
|
{
|
NO_REGS,
|
NO_REGS,
|
SP_REGS,
|
SP_REGS,
|
FB_REGS,
|
FB_REGS,
|
SB_REGS,
|
SB_REGS,
|
CR_REGS,
|
CR_REGS,
|
R0_REGS,
|
R0_REGS,
|
R1_REGS,
|
R1_REGS,
|
R2_REGS,
|
R2_REGS,
|
R3_REGS,
|
R3_REGS,
|
R02_REGS,
|
R02_REGS,
|
HL_REGS,
|
HL_REGS,
|
QI_REGS,
|
QI_REGS,
|
R23_REGS,
|
R23_REGS,
|
R03_REGS,
|
R03_REGS,
|
DI_REGS,
|
DI_REGS,
|
A0_REGS,
|
A0_REGS,
|
A1_REGS,
|
A1_REGS,
|
A_REGS,
|
A_REGS,
|
AD_REGS,
|
AD_REGS,
|
PS_REGS,
|
PS_REGS,
|
SI_REGS,
|
SI_REGS,
|
HI_REGS,
|
HI_REGS,
|
RA_REGS,
|
RA_REGS,
|
GENERAL_REGS,
|
GENERAL_REGS,
|
FLG_REGS,
|
FLG_REGS,
|
HC_REGS,
|
HC_REGS,
|
MEM_REGS,
|
MEM_REGS,
|
R02_A_MEM_REGS,
|
R02_A_MEM_REGS,
|
A_HL_MEM_REGS,
|
A_HL_MEM_REGS,
|
R1_R3_A_MEM_REGS,
|
R1_R3_A_MEM_REGS,
|
R03_MEM_REGS,
|
R03_MEM_REGS,
|
A_HI_MEM_REGS,
|
A_HI_MEM_REGS,
|
A_AD_CR_MEM_SI_REGS,
|
A_AD_CR_MEM_SI_REGS,
|
ALL_REGS,
|
ALL_REGS,
|
LIM_REG_CLASSES
|
LIM_REG_CLASSES
|
};
|
};
|
|
|
#define N_REG_CLASSES LIM_REG_CLASSES
|
#define N_REG_CLASSES LIM_REG_CLASSES
|
|
|
#define REG_CLASS_NAMES {\
|
#define REG_CLASS_NAMES {\
|
"NO_REGS", \
|
"NO_REGS", \
|
"SP_REGS", \
|
"SP_REGS", \
|
"FB_REGS", \
|
"FB_REGS", \
|
"SB_REGS", \
|
"SB_REGS", \
|
"CR_REGS", \
|
"CR_REGS", \
|
"R0_REGS", \
|
"R0_REGS", \
|
"R1_REGS", \
|
"R1_REGS", \
|
"R2_REGS", \
|
"R2_REGS", \
|
"R3_REGS", \
|
"R3_REGS", \
|
"R02_REGS", \
|
"R02_REGS", \
|
"HL_REGS", \
|
"HL_REGS", \
|
"QI_REGS", \
|
"QI_REGS", \
|
"R23_REGS", \
|
"R23_REGS", \
|
"R03_REGS", \
|
"R03_REGS", \
|
"DI_REGS", \
|
"DI_REGS", \
|
"A0_REGS", \
|
"A0_REGS", \
|
"A1_REGS", \
|
"A1_REGS", \
|
"A_REGS", \
|
"A_REGS", \
|
"AD_REGS", \
|
"AD_REGS", \
|
"PS_REGS", \
|
"PS_REGS", \
|
"SI_REGS", \
|
"SI_REGS", \
|
"HI_REGS", \
|
"HI_REGS", \
|
"RA_REGS", \
|
"RA_REGS", \
|
"GENERAL_REGS", \
|
"GENERAL_REGS", \
|
"FLG_REGS", \
|
"FLG_REGS", \
|
"HC_REGS", \
|
"HC_REGS", \
|
"MEM_REGS", \
|
"MEM_REGS", \
|
"R02_A_MEM_REGS", \
|
"R02_A_MEM_REGS", \
|
"A_HL_MEM_REGS", \
|
"A_HL_MEM_REGS", \
|
"R1_R3_A_MEM_REGS", \
|
"R1_R3_A_MEM_REGS", \
|
"R03_MEM_REGS", \
|
"R03_MEM_REGS", \
|
"A_HI_MEM_REGS", \
|
"A_HI_MEM_REGS", \
|
"A_AD_CR_MEM_SI_REGS", \
|
"A_AD_CR_MEM_SI_REGS", \
|
"ALL_REGS", \
|
"ALL_REGS", \
|
}
|
}
|
|
|
#define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
|
#define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
|
|
|
/* We support simple displacements off address registers, nothing else. */
|
/* We support simple displacements off address registers, nothing else. */
|
#define BASE_REG_CLASS A_REGS
|
#define BASE_REG_CLASS A_REGS
|
#define INDEX_REG_CLASS NO_REGS
|
#define INDEX_REG_CLASS NO_REGS
|
|
|
/* We primarily use the new "long" constraint names, with the initial
|
/* We primarily use the new "long" constraint names, with the initial
|
letter classifying the constraint type and following letters
|
letter classifying the constraint type and following letters
|
specifying which. The types are:
|
specifying which. The types are:
|
|
|
I - integer values
|
I - integer values
|
R - register classes
|
R - register classes
|
S - memory references (M was used)
|
S - memory references (M was used)
|
A - addresses (currently unused)
|
A - addresses (currently unused)
|
*/
|
*/
|
|
|
#define CONSTRAINT_LEN(CHAR,STR) \
|
#define CONSTRAINT_LEN(CHAR,STR) \
|
((CHAR) == 'I' ? 3 \
|
((CHAR) == 'I' ? 3 \
|
: (CHAR) == 'R' ? 3 \
|
: (CHAR) == 'R' ? 3 \
|
: (CHAR) == 'S' ? 2 \
|
: (CHAR) == 'S' ? 2 \
|
: (CHAR) == 'A' ? 2 \
|
: (CHAR) == 'A' ? 2 \
|
: DEFAULT_CONSTRAINT_LEN(CHAR,STR))
|
: DEFAULT_CONSTRAINT_LEN(CHAR,STR))
|
#define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
|
#define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
|
m32c_reg_class_from_constraint (CHAR, STR)
|
m32c_reg_class_from_constraint (CHAR, STR)
|
|
|
#define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
|
#define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
|
#define REGNO_OK_FOR_INDEX_P(NUM) 0
|
#define REGNO_OK_FOR_INDEX_P(NUM) 0
|
|
|
#define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
|
#define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
|
#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
|
#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
|
#define LIMIT_RELOAD_CLASS(MODE,CLASS) m32c_limit_reload_class (MODE, CLASS)
|
#define LIMIT_RELOAD_CLASS(MODE,CLASS) m32c_limit_reload_class (MODE, CLASS)
|
|
|
#define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) m32c_secondary_reload_class (CLASS, MODE, X)
|
#define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) m32c_secondary_reload_class (CLASS, MODE, X)
|
|
|
#define SMALL_REGISTER_CLASSES 1
|
#define SMALL_REGISTER_CLASSES 1
|
|
|
#define CLASS_LIKELY_SPILLED_P(C) m32c_class_likely_spilled_p (C)
|
#define CLASS_LIKELY_SPILLED_P(C) m32c_class_likely_spilled_p (C)
|
|
|
#define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
|
#define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
|
|
|
#define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
|
#define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
|
|
|
#define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
|
#define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
|
m32c_const_ok_for_constraint_p (VALUE, C, STR)
|
m32c_const_ok_for_constraint_p (VALUE, C, STR)
|
#define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
|
#define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
|
#define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
|
#define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
|
m32c_extra_constraint_p (VALUE, C, STR)
|
m32c_extra_constraint_p (VALUE, C, STR)
|
#define EXTRA_MEMORY_CONSTRAINT(C,STR) \
|
#define EXTRA_MEMORY_CONSTRAINT(C,STR) \
|
m32c_extra_memory_constraint (C, STR)
|
m32c_extra_memory_constraint (C, STR)
|
#define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
|
#define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
|
m32c_extra_address_constraint (C, STR)
|
m32c_extra_address_constraint (C, STR)
|
|
|
/* STACK AND CALLING */
|
/* STACK AND CALLING */
|
|
|
/* Frame Layout */
|
/* Frame Layout */
|
|
|
/* Standard push/pop stack, no surprises here. */
|
/* Standard push/pop stack, no surprises here. */
|
|
|
#define STACK_GROWS_DOWNWARD 1
|
#define STACK_GROWS_DOWNWARD 1
|
#define STACK_PUSH_CODE PRE_DEC
|
#define STACK_PUSH_CODE PRE_DEC
|
#define FRAME_GROWS_DOWNWARD 1
|
#define FRAME_GROWS_DOWNWARD 1
|
|
|
#define STARTING_FRAME_OFFSET 0
|
#define STARTING_FRAME_OFFSET 0
|
#define FIRST_PARM_OFFSET(F) 0
|
#define FIRST_PARM_OFFSET(F) 0
|
|
|
#define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
|
#define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
|
|
|
#define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
|
#define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
|
#define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
|
#define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
|
|
|
/* Exception Handling Support */
|
/* Exception Handling Support */
|
|
|
#define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
|
#define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
|
#define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
|
#define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
|
|
|
/* Registers That Address the Stack Frame */
|
/* Registers That Address the Stack Frame */
|
|
|
#ifndef FP_REGNO
|
#ifndef FP_REGNO
|
#define FP_REGNO 7
|
#define FP_REGNO 7
|
#endif
|
#endif
|
#ifndef SP_REGNO
|
#ifndef SP_REGNO
|
#define SP_REGNO 8
|
#define SP_REGNO 8
|
#endif
|
#endif
|
#define AP_REGNO 11
|
#define AP_REGNO 11
|
|
|
#define STACK_POINTER_REGNUM SP_REGNO
|
#define STACK_POINTER_REGNUM SP_REGNO
|
#define FRAME_POINTER_REGNUM FP_REGNO
|
#define FRAME_POINTER_REGNUM FP_REGNO
|
#define ARG_POINTER_REGNUM AP_REGNO
|
#define ARG_POINTER_REGNUM AP_REGNO
|
|
|
/* The static chain must be pointer-capable. */
|
/* The static chain must be pointer-capable. */
|
#define STATIC_CHAIN_REGNUM A0_REGNO
|
#define STATIC_CHAIN_REGNUM A0_REGNO
|
|
|
#define DWARF_FRAME_REGISTERS 20
|
#define DWARF_FRAME_REGISTERS 20
|
#define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
|
#define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
|
#define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
|
#define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
|
|
|
/* Eliminating Frame Pointer and Arg Pointer */
|
/* Eliminating Frame Pointer and Arg Pointer */
|
|
|
/* If the frame pointer isn't used, we detect it manually. But the
|
/* If the frame pointer isn't used, we detect it manually. But the
|
stack pointer doesn't have as flexible addressing as the frame
|
stack pointer doesn't have as flexible addressing as the frame
|
pointer, so we always assume we have it. */
|
pointer, so we always assume we have it. */
|
#define FRAME_POINTER_REQUIRED 1
|
#define FRAME_POINTER_REQUIRED 1
|
|
|
#define ELIMINABLE_REGS \
|
#define ELIMINABLE_REGS \
|
{{AP_REGNO, SP_REGNO}, \
|
{{AP_REGNO, SP_REGNO}, \
|
{AP_REGNO, FB_REGNO}, \
|
{AP_REGNO, FB_REGNO}, \
|
{FB_REGNO, SP_REGNO}}
|
{FB_REGNO, SP_REGNO}}
|
|
|
#define CAN_ELIMINATE(FROM,TO) 1
|
#define CAN_ELIMINATE(FROM,TO) 1
|
#define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
|
#define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
|
(VAR) = m32c_initial_elimination_offset(FROM,TO)
|
(VAR) = m32c_initial_elimination_offset(FROM,TO)
|
|
|
/* Passing Function Arguments on the Stack */
|
/* Passing Function Arguments on the Stack */
|
|
|
#define PUSH_ARGS 1
|
#define PUSH_ARGS 1
|
#define PUSH_ROUNDING(N) m32c_push_rounding (N)
|
#define PUSH_ROUNDING(N) m32c_push_rounding (N)
|
#define RETURN_POPS_ARGS(D,T,S) 0
|
#define RETURN_POPS_ARGS(D,T,S) 0
|
#define CALL_POPS_ARGS(C) 0
|
#define CALL_POPS_ARGS(C) 0
|
|
|
/* Passing Arguments in Registers */
|
/* Passing Arguments in Registers */
|
|
|
#define FUNCTION_ARG(CA,MODE,TYPE,NAMED) \
|
#define FUNCTION_ARG(CA,MODE,TYPE,NAMED) \
|
m32c_function_arg (&(CA),MODE,TYPE,NAMED)
|
m32c_function_arg (&(CA),MODE,TYPE,NAMED)
|
|
|
typedef struct m32c_cumulative_args
|
typedef struct m32c_cumulative_args
|
{
|
{
|
/* For address of return value buffer (structures are returned by
|
/* For address of return value buffer (structures are returned by
|
passing the address of a buffer as an invisible first argument.
|
passing the address of a buffer as an invisible first argument.
|
This identifies it). If set, the current parameter will be put
|
This identifies it). If set, the current parameter will be put
|
on the stack, regardless of type. */
|
on the stack, regardless of type. */
|
int force_mem;
|
int force_mem;
|
/* First parm is 1, parm 0 is hidden pointer for returning
|
/* First parm is 1, parm 0 is hidden pointer for returning
|
aggregates. */
|
aggregates. */
|
int parm_num;
|
int parm_num;
|
} m32c_cumulative_args;
|
} m32c_cumulative_args;
|
|
|
#define CUMULATIVE_ARGS m32c_cumulative_args
|
#define CUMULATIVE_ARGS m32c_cumulative_args
|
#define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
|
#define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
|
m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
|
m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
|
#define FUNCTION_ARG_ADVANCE(CA,MODE,TYPE,NAMED) \
|
#define FUNCTION_ARG_ADVANCE(CA,MODE,TYPE,NAMED) \
|
m32c_function_arg_advance (&(CA),MODE,TYPE,NAMED)
|
m32c_function_arg_advance (&(CA),MODE,TYPE,NAMED)
|
#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) (TARGET_A16 ? 8 : 16)
|
#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) (TARGET_A16 ? 8 : 16)
|
#define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
|
#define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
|
|
|
/* How Scalar Function Values Are Returned */
|
/* How Scalar Function Values Are Returned */
|
|
|
#define FUNCTION_VALUE(VT,F) m32c_function_value (VT, F)
|
#define FUNCTION_VALUE(VT,F) m32c_function_value (VT, F)
|
#define LIBCALL_VALUE(MODE) m32c_libcall_value (MODE)
|
#define LIBCALL_VALUE(MODE) m32c_libcall_value (MODE)
|
|
|
#define FUNCTION_VALUE_REGNO_P(r) ((r) == R0_REGNO || (r) == MEM0_REGNO)
|
#define FUNCTION_VALUE_REGNO_P(r) ((r) == R0_REGNO || (r) == MEM0_REGNO)
|
|
|
/* How Large Values Are Returned */
|
/* How Large Values Are Returned */
|
|
|
#define DEFAULT_PCC_STRUCT_RETURN 1
|
#define DEFAULT_PCC_STRUCT_RETURN 1
|
|
|
/* Function Entry and Exit */
|
/* Function Entry and Exit */
|
|
|
#define EXIT_IGNORE_STACK 0
|
#define EXIT_IGNORE_STACK 0
|
#define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
|
#define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
|
#define EH_USES(REGNO) 0 /* FIXME */
|
#define EH_USES(REGNO) 0 /* FIXME */
|
|
|
/* Generating Code for Profiling */
|
/* Generating Code for Profiling */
|
|
|
#define FUNCTION_PROFILER(FILE,LABELNO)
|
#define FUNCTION_PROFILER(FILE,LABELNO)
|
|
|
/* Implementing the Varargs Macros */
|
/* Implementing the Varargs Macros */
|
|
|
/* Trampolines for Nested Functions */
|
/* Trampolines for Nested Functions */
|
|
|
#define TRAMPOLINE_SIZE m32c_trampoline_size ()
|
#define TRAMPOLINE_SIZE m32c_trampoline_size ()
|
#define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
|
#define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
|
#define INITIALIZE_TRAMPOLINE(a,fn,sc) m32c_initialize_trampoline (a, fn, sc)
|
#define INITIALIZE_TRAMPOLINE(a,fn,sc) m32c_initialize_trampoline (a, fn, sc)
|
|
|
/* Addressing Modes */
|
/* Addressing Modes */
|
|
|
#define HAVE_PRE_DECREMENT 1
|
#define HAVE_PRE_DECREMENT 1
|
#define HAVE_POST_INCREMENT 1
|
#define HAVE_POST_INCREMENT 1
|
#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
|
#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
|
#define MAX_REGS_PER_ADDRESS 1
|
#define MAX_REGS_PER_ADDRESS 1
|
|
|
/* This is passed to the macros below, so that they can be implemented
|
/* This is passed to the macros below, so that they can be implemented
|
in m32c.c. */
|
in m32c.c. */
|
#ifdef REG_OK_STRICT
|
#ifdef REG_OK_STRICT
|
#define REG_OK_STRICT_V 1
|
#define REG_OK_STRICT_V 1
|
#else
|
#else
|
#define REG_OK_STRICT_V 0
|
#define REG_OK_STRICT_V 0
|
#endif
|
#endif
|
|
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE,X,LABEL) \
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE,X,LABEL) \
|
if (m32c_legitimate_address_p (MODE, X, REG_OK_STRICT_V)) \
|
if (m32c_legitimate_address_p (MODE, X, REG_OK_STRICT_V)) \
|
goto LABEL;
|
goto LABEL;
|
|
|
#define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
|
#define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
|
#define REG_OK_FOR_INDEX_P(X) 0
|
#define REG_OK_FOR_INDEX_P(X) 0
|
|
|
/* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
|
/* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
|
|
|
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
|
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
|
if (m32c_legitimize_address(&(X),OLDX,MODE)) \
|
if (m32c_legitimize_address(&(X),OLDX,MODE)) \
|
goto win;
|
goto win;
|
|
|
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
|
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
|
if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
|
if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
|
goto win;
|
goto win;
|
|
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
|
if (m32c_mode_dependent_address (ADDR)) \
|
if (m32c_mode_dependent_address (ADDR)) \
|
goto LABEL;
|
goto LABEL;
|
|
|
#define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
|
#define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
|
|
|
/* Condition Code Status */
|
/* Condition Code Status */
|
|
|
#define REVERSIBLE_CC_MODE(MODE) 1
|
#define REVERSIBLE_CC_MODE(MODE) 1
|
|
|
/* Describing Relative Costs of Operations */
|
/* Describing Relative Costs of Operations */
|
|
|
#define REGISTER_MOVE_COST(MODE,FROM,TO) \
|
#define REGISTER_MOVE_COST(MODE,FROM,TO) \
|
m32c_register_move_cost (MODE, FROM, TO)
|
m32c_register_move_cost (MODE, FROM, TO)
|
#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
|
#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
|
m32c_memory_move_cost (MODE, CLASS, IN)
|
m32c_memory_move_cost (MODE, CLASS, IN)
|
|
|
/* Dividing the Output into Sections (Texts, Data, ...) */
|
/* Dividing the Output into Sections (Texts, Data, ...) */
|
|
|
#define TEXT_SECTION_ASM_OP ".text"
|
#define TEXT_SECTION_ASM_OP ".text"
|
#define DATA_SECTION_ASM_OP ".data"
|
#define DATA_SECTION_ASM_OP ".data"
|
#define BSS_SECTION_ASM_OP ".bss"
|
#define BSS_SECTION_ASM_OP ".bss"
|
|
|
#define CTOR_LIST_BEGIN
|
#define CTOR_LIST_BEGIN
|
#define CTOR_LIST_END
|
#define CTOR_LIST_END
|
#define DTOR_LIST_BEGIN
|
#define DTOR_LIST_BEGIN
|
#define DTOR_LIST_END
|
#define DTOR_LIST_END
|
#define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
|
#define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
|
#define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
|
#define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
|
#define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
|
#define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
|
#define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
|
#define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
|
|
|
/* The Overall Framework of an Assembler File */
|
/* The Overall Framework of an Assembler File */
|
|
|
#define ASM_COMMENT_START ";"
|
#define ASM_COMMENT_START ";"
|
#define ASM_APP_ON ""
|
#define ASM_APP_ON ""
|
#define ASM_APP_OFF ""
|
#define ASM_APP_OFF ""
|
|
|
/* Output and Generation of Labels */
|
/* Output and Generation of Labels */
|
|
|
#define GLOBAL_ASM_OP "\t.global\t"
|
#define GLOBAL_ASM_OP "\t.global\t"
|
|
|
/* Output of Assembler Instructions */
|
/* Output of Assembler Instructions */
|
|
|
#define REGISTER_NAMES { \
|
#define REGISTER_NAMES { \
|
"r0", "r2", "r1", "r3", \
|
"r0", "r2", "r1", "r3", \
|
"a0", "a1", "sb", "fb", "sp", \
|
"a0", "a1", "sb", "fb", "sp", \
|
"pc", "flg", "argp", \
|
"pc", "flg", "argp", \
|
"mem0", "mem2", "mem4", "mem6", "mem8", "mem10", "mem12", "mem14", \
|
"mem0", "mem2", "mem4", "mem6", "mem8", "mem10", "mem12", "mem14", \
|
}
|
}
|
|
|
#define ADDITIONAL_REGISTER_NAMES { \
|
#define ADDITIONAL_REGISTER_NAMES { \
|
{"r0l", 0}, \
|
{"r0l", 0}, \
|
{"r1l", 2}, \
|
{"r1l", 2}, \
|
{"r0r2", 0}, \
|
{"r0r2", 0}, \
|
{"r1r3", 2}, \
|
{"r1r3", 2}, \
|
{"a0a1", 4}, \
|
{"a0a1", 4}, \
|
{"r0r2r1r3", 0} }
|
{"r0r2r1r3", 0} }
|
|
|
#define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
|
#define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
|
#define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
|
#define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
|
#define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
|
#define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
|
|
|
#undef USER_LABEL_PREFIX
|
#undef USER_LABEL_PREFIX
|
#define USER_LABEL_PREFIX "_"
|
#define USER_LABEL_PREFIX "_"
|
|
|
#define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
|
#define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
|
#define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
|
#define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
|
|
|
/* Output of Dispatch Tables */
|
/* Output of Dispatch Tables */
|
|
|
#define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
|
#define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
|
fprintf (S, "\t.word L%d\n", V)
|
fprintf (S, "\t.word L%d\n", V)
|
|
|
/* Assembler Commands for Exception Regions */
|
/* Assembler Commands for Exception Regions */
|
|
|
#define DWARF_CIE_DATA_ALIGNMENT -1
|
#define DWARF_CIE_DATA_ALIGNMENT -1
|
|
|
/* Assembler Commands for Alignment */
|
/* Assembler Commands for Alignment */
|
|
|
#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
|
#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
|
fprintf (STREAM, "\t.p2align\t%d\n", POWER);
|
fprintf (STREAM, "\t.p2align\t%d\n", POWER);
|
|
|
/* Controlling Debugging Information Format */
|
/* Controlling Debugging Information Format */
|
|
|
#define DWARF2_ADDR_SIZE 4
|
#define DWARF2_ADDR_SIZE 4
|
|
|
/* Miscellaneous Parameters */
|
/* Miscellaneous Parameters */
|
|
|
#define HAS_LONG_COND_BRANCH false
|
#define HAS_LONG_COND_BRANCH false
|
#define HAS_LONG_UNCOND_BRANCH true
|
#define HAS_LONG_UNCOND_BRANCH true
|
#define CASE_VECTOR_MODE SImode
|
#define CASE_VECTOR_MODE SImode
|
#define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
|
#define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
|
|
|
#define MOVE_MAX 4
|
#define MOVE_MAX 4
|
#define TRULY_NOOP_TRUNCATION(op,ip) 1
|
#define TRULY_NOOP_TRUNCATION(op,ip) 1
|
|
|
#define STORE_FLAG_VALUE 1
|
#define STORE_FLAG_VALUE 1
|
|
|
/* 16 or 24 bit pointers */
|
/* 16 or 24 bit pointers */
|
#define Pmode (TARGET_A16 ? HImode : PSImode)
|
#define Pmode (TARGET_A16 ? HImode : PSImode)
|
#define FUNCTION_MODE QImode
|
#define FUNCTION_MODE QImode
|
|
|
#define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
|
#define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
|
|
|
#endif
|
#endif
|
|
|
