;; Predicate definitions for Motorola MCore.
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;; Predicate definitions for Motorola MCore.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; Nonzero if OP is a normal arithmetic register.
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;; Nonzero if OP is a normal arithmetic register.
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(define_predicate "mcore_arith_reg_operand"
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(define_predicate "mcore_arith_reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (! register_operand (op, mode))
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if (! register_operand (op, mode))
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return 0;
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return 0;
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if (GET_CODE (op) == SUBREG)
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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op = SUBREG_REG (op);
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if (GET_CODE (op) == REG)
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if (GET_CODE (op) == REG)
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return REGNO (op) != CC_REG;
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return REGNO (op) != CC_REG;
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return 1;
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return 1;
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})
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})
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;; Nonzero if OP can be source of a simple move operation.
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;; Nonzero if OP can be source of a simple move operation.
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(define_predicate "mcore_general_movsrc_operand"
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(define_predicate "mcore_general_movsrc_operand"
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(match_code "mem,const_int,reg,subreg,symbol_ref,label_ref")
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(match_code "mem,const_int,reg,subreg,symbol_ref,label_ref")
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{
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{
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/* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
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/* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
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if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF)
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if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF)
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return 1;
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return 1;
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return general_operand (op, mode);
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return general_operand (op, mode);
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})
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})
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;; Nonzero if OP can be destination of a simple move operation.
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;; Nonzero if OP can be destination of a simple move operation.
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(define_predicate "mcore_general_movdst_operand"
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(define_predicate "mcore_general_movdst_operand"
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(match_code "mem,const_int,reg,subreg")
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(match_code "mem,const_int,reg,subreg")
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{
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{
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if (GET_CODE (op) == REG && REGNO (op) == CC_REG)
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if (GET_CODE (op) == REG && REGNO (op) == CC_REG)
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return 0;
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return 0;
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return general_operand (op, mode);
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return general_operand (op, mode);
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})
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})
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;; Nonzero if OP should be recognized during reload for an ixh/ixw
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;; Nonzero if OP should be recognized during reload for an ixh/ixw
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;; operand. See the ixh/ixw patterns.
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;; operand. See the ixh/ixw patterns.
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(define_predicate "mcore_reload_operand"
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(define_predicate "mcore_reload_operand"
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(match_code "mem,reg,subreg")
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(match_code "mem,reg,subreg")
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{
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{
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if (mcore_arith_reg_operand (op, mode))
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if (mcore_arith_reg_operand (op, mode))
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return 1;
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return 1;
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if (! reload_in_progress)
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if (! reload_in_progress)
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return 0;
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return 0;
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return GET_CODE (op) == MEM;
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return GET_CODE (op) == MEM;
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})
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})
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;; Nonzero if OP is a valid source operand for an arithmetic insn.
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;; Nonzero if OP is a valid source operand for an arithmetic insn.
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(define_predicate "mcore_arith_J_operand"
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(define_predicate "mcore_arith_J_operand"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; Nonzero if OP is a valid source operand for an arithmetic insn.
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;; Nonzero if OP is a valid source operand for an arithmetic insn.
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(define_predicate "mcore_arith_K_operand"
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(define_predicate "mcore_arith_K_operand"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; Nonzero if OP is a valid source operand for a shift or rotate insn.
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;; Nonzero if OP is a valid source operand for a shift or rotate insn.
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(define_predicate "mcore_arith_K_operand_not_0"
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(define_predicate "mcore_arith_K_operand_not_0"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if ( GET_CODE (op) == CONST_INT
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if ( GET_CODE (op) == CONST_INT
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&& CONST_OK_FOR_K (INTVAL (op))
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&& CONST_OK_FOR_K (INTVAL (op))
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&& INTVAL (op) != 0)
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&& INTVAL (op) != 0)
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "mcore_arith_M_operand"
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(define_predicate "mcore_arith_M_operand"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "mcore_arith_K_S_operand"
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(define_predicate "mcore_arith_K_S_operand"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if (GET_CODE (op) == CONST_INT)
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if (GET_CODE (op) == CONST_INT)
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{
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{
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if (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_M (~INTVAL (op)))
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if (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_M (~INTVAL (op)))
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return 1;
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return 1;
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}
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}
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return 0;
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return 0;
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})
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})
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;; Nonzero if OP is a valid source operand for a cmov with two consts
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;; Nonzero if OP is a valid source operand for a cmov with two consts
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;; +/- 1.
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;; +/- 1.
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(define_predicate "mcore_arith_O_operand"
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(define_predicate "mcore_arith_O_operand"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; Nonzero if OP is a valid source operand for loading.
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;; Nonzero if OP is a valid source operand for loading.
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(define_predicate "mcore_arith_imm_operand"
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(define_predicate "mcore_arith_imm_operand"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op)))
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if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op)))
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "mcore_arith_any_imm_operand"
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(define_predicate "mcore_arith_any_imm_operand"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if (GET_CODE (op) == CONST_INT)
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if (GET_CODE (op) == CONST_INT)
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; Nonzero if OP is a valid source operand for a btsti.
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;; Nonzero if OP is a valid source operand for a btsti.
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(define_predicate "mcore_literal_K_operand"
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(define_predicate "mcore_literal_K_operand"
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(match_code "const_int")
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(match_code "const_int")
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{
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{
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; Nonzero if OP is a valid source operand for an add/sub insn.
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;; Nonzero if OP is a valid source operand for an add/sub insn.
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(define_predicate "mcore_addsub_operand"
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(define_predicate "mcore_addsub_operand"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if (GET_CODE (op) == CONST_INT)
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if (GET_CODE (op) == CONST_INT)
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{
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{
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return 1;
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return 1;
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/* The following is removed because it precludes large constants from being
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/* The following is removed because it precludes large constants from being
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returned as valid source operands for and add/sub insn. While large
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returned as valid source operands for and add/sub insn. While large
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constants may not directly be used in an add/sub, they may if first loaded
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constants may not directly be used in an add/sub, they may if first loaded
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into a register. Thus, this predicate should indicate that they are valid,
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into a register. Thus, this predicate should indicate that they are valid,
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and the constraint in mcore.md should control whether an additional load to
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and the constraint in mcore.md should control whether an additional load to
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register is needed. (see mcore.md, addsi). -- DAC 4/2/1998 */
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register is needed. (see mcore.md, addsi). -- DAC 4/2/1998 */
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/*
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/*
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if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op)))
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if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op)))
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return 1;
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return 1;
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*/
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*/
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}
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}
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return 0;
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return 0;
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})
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})
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;; Nonzero if OP is a valid source operand for a compare operation.
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;; Nonzero if OP is a valid source operand for a compare operation.
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(define_predicate "mcore_compare_operand"
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(define_predicate "mcore_compare_operand"
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(match_code "const_int,reg,subreg")
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(match_code "const_int,reg,subreg")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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return 1;
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return 1;
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if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
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if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; Return 1 if OP is a load multiple operation. It is known to be a
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;; Return 1 if OP is a load multiple operation. It is known to be a
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;; PARALLEL and the first section will be tested.
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;; PARALLEL and the first section will be tested.
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(define_predicate "mcore_load_multiple_operation"
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(define_predicate "mcore_load_multiple_operation"
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(match_code "parallel")
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(match_code "parallel")
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{
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{
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int count = XVECLEN (op, 0);
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int count = XVECLEN (op, 0);
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int dest_regno;
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int dest_regno;
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rtx src_addr;
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rtx src_addr;
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int i;
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int i;
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/* Perform a quick check so we don't blow up below. */
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/* Perform a quick check so we don't blow up below. */
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if (count <= 1
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if (count <= 1
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|| GET_CODE (XVECEXP (op, 0, 0)) != SET
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|| GET_CODE (XVECEXP (op, 0, 0)) != SET
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|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
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|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
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|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
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|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
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return 0;
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return 0;
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dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
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dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
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src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
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src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
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for (i = 1; i < count; i++)
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for (i = 1; i < count; i++)
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{
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{
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rtx elt = XVECEXP (op, 0, i);
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rtx elt = XVECEXP (op, 0, i);
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if (GET_CODE (elt) != SET
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if (GET_CODE (elt) != SET
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|| GET_CODE (SET_DEST (elt)) != REG
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|| GET_CODE (SET_DEST (elt)) != REG
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|| GET_MODE (SET_DEST (elt)) != SImode
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|| GET_MODE (SET_DEST (elt)) != SImode
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|| REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
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|| REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
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|| GET_CODE (SET_SRC (elt)) != MEM
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|| GET_CODE (SET_SRC (elt)) != MEM
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|| GET_MODE (SET_SRC (elt)) != SImode
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|| GET_MODE (SET_SRC (elt)) != SImode
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|| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
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|| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
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|| ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
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|| ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
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|| GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
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|| GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
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|| INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
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|| INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
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return 0;
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return 0;
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}
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}
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return 1;
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return 1;
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})
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})
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;; Similar, but tests for store multiple.
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;; Similar, but tests for store multiple.
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(define_predicate "mcore_store_multiple_operation"
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(define_predicate "mcore_store_multiple_operation"
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(match_code "parallel")
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(match_code "parallel")
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{
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{
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int count = XVECLEN (op, 0);
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int count = XVECLEN (op, 0);
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int src_regno;
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int src_regno;
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rtx dest_addr;
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rtx dest_addr;
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int i;
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int i;
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/* Perform a quick check so we don't blow up below. */
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/* Perform a quick check so we don't blow up below. */
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if (count <= 1
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if (count <= 1
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|| GET_CODE (XVECEXP (op, 0, 0)) != SET
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|| GET_CODE (XVECEXP (op, 0, 0)) != SET
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|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
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|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
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|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
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|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
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return 0;
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return 0;
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src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
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src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
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dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
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dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
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for (i = 1; i < count; i++)
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for (i = 1; i < count; i++)
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{
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{
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rtx elt = XVECEXP (op, 0, i);
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rtx elt = XVECEXP (op, 0, i);
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if (GET_CODE (elt) != SET
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if (GET_CODE (elt) != SET
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|| GET_CODE (SET_SRC (elt)) != REG
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|| GET_CODE (SET_SRC (elt)) != REG
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|| GET_MODE (SET_SRC (elt)) != SImode
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|| GET_MODE (SET_SRC (elt)) != SImode
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|| REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
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|| REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
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|| GET_CODE (SET_DEST (elt)) != MEM
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|| GET_CODE (SET_DEST (elt)) != MEM
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|| GET_MODE (SET_DEST (elt)) != SImode
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|| GET_MODE (SET_DEST (elt)) != SImode
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|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
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|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
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|| ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
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|| ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
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|| GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
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|| GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
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|| INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
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|| INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
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return 0;
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return 0;
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}
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}
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return 1;
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return 1;
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "mcore_call_address_operand"
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(define_predicate "mcore_call_address_operand"
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(match_code "reg,subreg,const_int,symbol_ref")
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(match_code "reg,subreg,const_int,symbol_ref")
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{
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{
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return register_operand (op, mode) || CONSTANT_P (op);
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return register_operand (op, mode) || CONSTANT_P (op);
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})
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})
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|
|
