;; AltiVec patterns.
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;; AltiVec patterns.
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;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007
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;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007
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;; Free Software Foundation, Inc.
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;; Free Software Foundation, Inc.
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;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
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;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
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;; This file is part of GCC.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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|
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(define_constants
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(define_constants
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[(UNSPEC_VCMPBFP 50)
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[(UNSPEC_VCMPBFP 50)
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(UNSPEC_VCMPEQUB 51)
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(UNSPEC_VCMPEQUB 51)
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(UNSPEC_VCMPEQUH 52)
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(UNSPEC_VCMPEQUH 52)
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(UNSPEC_VCMPEQUW 53)
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(UNSPEC_VCMPEQUW 53)
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(UNSPEC_VCMPEQFP 54)
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(UNSPEC_VCMPEQFP 54)
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(UNSPEC_VCMPGEFP 55)
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(UNSPEC_VCMPGEFP 55)
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(UNSPEC_VCMPGTUB 56)
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(UNSPEC_VCMPGTUB 56)
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(UNSPEC_VCMPGTSB 57)
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(UNSPEC_VCMPGTSB 57)
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(UNSPEC_VCMPGTUH 58)
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(UNSPEC_VCMPGTUH 58)
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(UNSPEC_VCMPGTSH 59)
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(UNSPEC_VCMPGTSH 59)
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(UNSPEC_VCMPGTUW 60)
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(UNSPEC_VCMPGTUW 60)
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(UNSPEC_VCMPGTSW 61)
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(UNSPEC_VCMPGTSW 61)
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(UNSPEC_VCMPGTFP 62)
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(UNSPEC_VCMPGTFP 62)
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(UNSPEC_VMSUMU 65)
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(UNSPEC_VMSUMU 65)
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(UNSPEC_VMSUMM 66)
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(UNSPEC_VMSUMM 66)
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(UNSPEC_VMSUMSHM 68)
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(UNSPEC_VMSUMSHM 68)
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(UNSPEC_VMSUMUHS 69)
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(UNSPEC_VMSUMUHS 69)
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(UNSPEC_VMSUMSHS 70)
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(UNSPEC_VMSUMSHS 70)
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(UNSPEC_VMHADDSHS 71)
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(UNSPEC_VMHADDSHS 71)
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(UNSPEC_VMHRADDSHS 72)
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(UNSPEC_VMHRADDSHS 72)
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(UNSPEC_VMLADDUHM 73)
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(UNSPEC_VMLADDUHM 73)
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(UNSPEC_VADDCUW 75)
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(UNSPEC_VADDCUW 75)
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(UNSPEC_VADDU 76)
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(UNSPEC_VADDU 76)
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(UNSPEC_VADDS 77)
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(UNSPEC_VADDS 77)
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(UNSPEC_VAVGU 80)
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(UNSPEC_VAVGU 80)
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(UNSPEC_VAVGS 81)
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(UNSPEC_VAVGS 81)
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(UNSPEC_VMULEUB 83)
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(UNSPEC_VMULEUB 83)
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(UNSPEC_VMULESB 84)
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(UNSPEC_VMULESB 84)
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(UNSPEC_VMULEUH 85)
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(UNSPEC_VMULEUH 85)
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(UNSPEC_VMULESH 86)
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(UNSPEC_VMULESH 86)
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(UNSPEC_VMULOUB 87)
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(UNSPEC_VMULOUB 87)
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(UNSPEC_VMULOSB 88)
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(UNSPEC_VMULOSB 88)
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(UNSPEC_VMULOUH 89)
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(UNSPEC_VMULOUH 89)
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(UNSPEC_VMULOSH 90)
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(UNSPEC_VMULOSH 90)
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(UNSPEC_VPKUHUM 93)
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(UNSPEC_VPKUHUM 93)
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(UNSPEC_VPKUWUM 94)
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(UNSPEC_VPKUWUM 94)
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(UNSPEC_VPKPX 95)
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(UNSPEC_VPKPX 95)
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(UNSPEC_VPKSHSS 97)
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(UNSPEC_VPKSHSS 97)
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(UNSPEC_VPKSWSS 99)
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(UNSPEC_VPKSWSS 99)
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(UNSPEC_VPKUHUS 100)
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(UNSPEC_VPKUHUS 100)
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(UNSPEC_VPKSHUS 101)
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(UNSPEC_VPKSHUS 101)
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(UNSPEC_VPKUWUS 102)
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(UNSPEC_VPKUWUS 102)
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(UNSPEC_VPKSWUS 103)
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(UNSPEC_VPKSWUS 103)
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(UNSPEC_VRL 104)
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(UNSPEC_VRL 104)
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(UNSPEC_VSL 107)
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(UNSPEC_VSL 107)
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(UNSPEC_VSLV4SI 110)
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(UNSPEC_VSLV4SI 110)
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(UNSPEC_VSLO 111)
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(UNSPEC_VSLO 111)
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(UNSPEC_VSR 118)
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(UNSPEC_VSR 118)
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(UNSPEC_VSRO 119)
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(UNSPEC_VSRO 119)
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(UNSPEC_VSUBCUW 124)
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(UNSPEC_VSUBCUW 124)
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(UNSPEC_VSUBU 125)
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(UNSPEC_VSUBU 125)
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(UNSPEC_VSUBS 126)
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(UNSPEC_VSUBS 126)
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(UNSPEC_VSUM4UBS 131)
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(UNSPEC_VSUM4UBS 131)
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(UNSPEC_VSUM4S 132)
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(UNSPEC_VSUM4S 132)
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(UNSPEC_VSUM2SWS 134)
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(UNSPEC_VSUM2SWS 134)
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(UNSPEC_VSUMSWS 135)
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(UNSPEC_VSUMSWS 135)
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(UNSPEC_VPERM 144)
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(UNSPEC_VPERM 144)
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(UNSPEC_VRFIP 148)
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(UNSPEC_VRFIP 148)
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(UNSPEC_VRFIN 149)
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(UNSPEC_VRFIN 149)
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(UNSPEC_VRFIM 150)
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(UNSPEC_VRFIM 150)
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(UNSPEC_VCFUX 151)
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(UNSPEC_VCFUX 151)
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(UNSPEC_VCFSX 152)
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(UNSPEC_VCFSX 152)
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(UNSPEC_VCTUXS 153)
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(UNSPEC_VCTUXS 153)
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(UNSPEC_VCTSXS 154)
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(UNSPEC_VCTSXS 154)
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(UNSPEC_VLOGEFP 155)
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(UNSPEC_VLOGEFP 155)
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(UNSPEC_VEXPTEFP 156)
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(UNSPEC_VEXPTEFP 156)
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(UNSPEC_VRSQRTEFP 157)
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(UNSPEC_VRSQRTEFP 157)
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(UNSPEC_VREFP 158)
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(UNSPEC_VREFP 158)
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(UNSPEC_VSEL4SI 159)
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(UNSPEC_VSEL4SI 159)
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(UNSPEC_VSEL4SF 160)
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(UNSPEC_VSEL4SF 160)
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(UNSPEC_VSEL8HI 161)
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(UNSPEC_VSEL8HI 161)
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(UNSPEC_VSEL16QI 162)
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(UNSPEC_VSEL16QI 162)
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(UNSPEC_VLSDOI 163)
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(UNSPEC_VLSDOI 163)
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(UNSPEC_VUPKHSB 167)
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(UNSPEC_VUPKHSB 167)
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(UNSPEC_VUPKHPX 168)
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(UNSPEC_VUPKHPX 168)
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(UNSPEC_VUPKHSH 169)
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(UNSPEC_VUPKHSH 169)
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(UNSPEC_VUPKLSB 170)
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(UNSPEC_VUPKLSB 170)
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(UNSPEC_VUPKLPX 171)
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(UNSPEC_VUPKLPX 171)
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(UNSPEC_VUPKLSH 172)
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(UNSPEC_VUPKLSH 172)
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(UNSPEC_PREDICATE 173)
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(UNSPEC_PREDICATE 173)
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(UNSPEC_DST 190)
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(UNSPEC_DST 190)
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(UNSPEC_DSTT 191)
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(UNSPEC_DSTT 191)
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(UNSPEC_DSTST 192)
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(UNSPEC_DSTST 192)
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(UNSPEC_DSTSTT 193)
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(UNSPEC_DSTSTT 193)
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(UNSPEC_LVSL 194)
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(UNSPEC_LVSL 194)
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(UNSPEC_LVSR 195)
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(UNSPEC_LVSR 195)
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(UNSPEC_LVE 196)
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(UNSPEC_LVE 196)
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(UNSPEC_STVX 201)
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(UNSPEC_STVX 201)
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(UNSPEC_STVXL 202)
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(UNSPEC_STVXL 202)
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(UNSPEC_STVE 203)
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(UNSPEC_STVE 203)
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(UNSPEC_SET_VSCR 213)
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(UNSPEC_SET_VSCR 213)
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(UNSPEC_GET_VRSAVE 214)
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(UNSPEC_GET_VRSAVE 214)
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(UNSPEC_REALIGN_LOAD 215)
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(UNSPEC_REALIGN_LOAD 215)
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(UNSPEC_REDUC_PLUS 217)
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(UNSPEC_REDUC_PLUS 217)
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(UNSPEC_VECSH 219)
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(UNSPEC_VECSH 219)
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(UNSPEC_VCOND_V4SI 301)
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(UNSPEC_VCOND_V4SI 301)
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(UNSPEC_VCOND_V4SF 302)
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(UNSPEC_VCOND_V4SF 302)
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(UNSPEC_VCOND_V8HI 303)
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(UNSPEC_VCOND_V8HI 303)
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(UNSPEC_VCOND_V16QI 304)
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(UNSPEC_VCOND_V16QI 304)
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(UNSPEC_VCONDU_V4SI 305)
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(UNSPEC_VCONDU_V4SI 305)
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(UNSPEC_VCONDU_V8HI 306)
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(UNSPEC_VCONDU_V8HI 306)
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(UNSPEC_VCONDU_V16QI 307)
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(UNSPEC_VCONDU_V16QI 307)
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])
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])
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(define_constants
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(define_constants
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[(UNSPECV_SET_VRSAVE 30)
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[(UNSPECV_SET_VRSAVE 30)
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(UNSPECV_MTVSCR 186)
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(UNSPECV_MTVSCR 186)
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(UNSPECV_MFVSCR 187)
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(UNSPECV_MFVSCR 187)
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(UNSPECV_DSSALL 188)
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(UNSPECV_DSSALL 188)
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(UNSPECV_DSS 189)
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(UNSPECV_DSS 189)
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])
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])
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;; Vec int modes
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;; Vec int modes
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(define_mode_macro VI [V4SI V8HI V16QI])
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(define_mode_macro VI [V4SI V8HI V16QI])
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;; Short vec in modes
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;; Short vec in modes
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(define_mode_macro VIshort [V8HI V16QI])
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(define_mode_macro VIshort [V8HI V16QI])
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;; Vec float modes
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;; Vec float modes
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(define_mode_macro VF [V4SF])
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(define_mode_macro VF [V4SF])
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;; Vec modes, pity mode macros are not composable
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;; Vec modes, pity mode macros are not composable
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(define_mode_macro V [V4SI V8HI V16QI V4SF])
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(define_mode_macro V [V4SI V8HI V16QI V4SF])
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(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
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(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
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;; Generic LVX load instruction.
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;; Generic LVX load instruction.
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(define_insn "altivec_lvx_"
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(define_insn "altivec_lvx_"
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[(set (match_operand:V 0 "altivec_register_operand" "=v")
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[(set (match_operand:V 0 "altivec_register_operand" "=v")
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(match_operand:V 1 "memory_operand" "Z"))]
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(match_operand:V 1 "memory_operand" "Z"))]
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"TARGET_ALTIVEC"
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"TARGET_ALTIVEC"
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"lvx %0,%y1"
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"lvx %0,%y1"
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[(set_attr "type" "vecload")])
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[(set_attr "type" "vecload")])
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;; Generic STVX store instruction.
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;; Generic STVX store instruction.
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(define_insn "altivec_stvx_"
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(define_insn "altivec_stvx_"
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[(set (match_operand:V 0 "memory_operand" "=Z")
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[(set (match_operand:V 0 "memory_operand" "=Z")
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(match_operand:V 1 "altivec_register_operand" "v"))]
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(match_operand:V 1 "altivec_register_operand" "v"))]
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"TARGET_ALTIVEC"
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"TARGET_ALTIVEC"
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"stvx %1,%y0"
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"stvx %1,%y0"
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[(set_attr "type" "vecstore")])
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[(set_attr "type" "vecstore")])
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;; Vector move instructions.
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;; Vector move instructions.
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(define_expand "mov"
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(define_expand "mov"
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[(set (match_operand:V 0 "nonimmediate_operand" "")
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[(set (match_operand:V 0 "nonimmediate_operand" "")
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(match_operand:V 1 "any_operand" ""))]
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(match_operand:V 1 "any_operand" ""))]
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"TARGET_ALTIVEC"
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"TARGET_ALTIVEC"
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{
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{
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rs6000_emit_move (operands[0], operands[1], mode);
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rs6000_emit_move (operands[0], operands[1], mode);
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DONE;
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DONE;
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})
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})
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(define_insn "*mov_internal"
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(define_insn "*mov_internal"
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[(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,o,r,r,v")
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[(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,o,r,r,v")
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(match_operand:V 1 "input_operand" "v,Z,v,r,o,r,W"))]
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(match_operand:V 1 "input_operand" "v,Z,v,r,o,r,W"))]
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"TARGET_ALTIVEC
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"TARGET_ALTIVEC
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&& (register_operand (operands[0], mode)
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&& (register_operand (operands[0], mode)
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|| register_operand (operands[1], mode))"
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|| register_operand (operands[1], mode))"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0: return "stvx %1,%y0";
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case 0: return "stvx %1,%y0";
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case 1: return "lvx %0,%y1";
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case 1: return "lvx %0,%y1";
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case 2: return "vor %0,%1,%1";
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case 2: return "vor %0,%1,%1";
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case 3: return "#";
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case 3: return "#";
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case 4: return "#";
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case 4: return "#";
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case 5: return "#";
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case 5: return "#";
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case 6: return output_vec_const_move (operands);
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case 6: return output_vec_const_move (operands);
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
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[(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
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(define_split
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(define_split
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[(set (match_operand:V4SI 0 "nonimmediate_operand" "")
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[(set (match_operand:V4SI 0 "nonimmediate_operand" "")
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(match_operand:V4SI 1 "input_operand" ""))]
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(match_operand:V4SI 1 "input_operand" ""))]
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"TARGET_ALTIVEC && reload_completed
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"TARGET_ALTIVEC && reload_completed
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&& gpr_or_gpr_p (operands[0], operands[1])"
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&& gpr_or_gpr_p (operands[0], operands[1])"
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[(pc)]
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[(pc)]
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{
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{
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rs6000_split_multireg_move (operands[0], operands[1]); DONE;
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rs6000_split_multireg_move (operands[0], operands[1]); DONE;
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})
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})
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|
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(define_split
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(define_split
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[(set (match_operand:V8HI 0 "nonimmediate_operand" "")
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[(set (match_operand:V8HI 0 "nonimmediate_operand" "")
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(match_operand:V8HI 1 "input_operand" ""))]
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(match_operand:V8HI 1 "input_operand" ""))]
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"TARGET_ALTIVEC && reload_completed
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"TARGET_ALTIVEC && reload_completed
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&& gpr_or_gpr_p (operands[0], operands[1])"
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&& gpr_or_gpr_p (operands[0], operands[1])"
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[(pc)]
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[(pc)]
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{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
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{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
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|
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(define_split
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(define_split
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[(set (match_operand:V16QI 0 "nonimmediate_operand" "")
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[(set (match_operand:V16QI 0 "nonimmediate_operand" "")
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(match_operand:V16QI 1 "input_operand" ""))]
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(match_operand:V16QI 1 "input_operand" ""))]
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"TARGET_ALTIVEC && reload_completed
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"TARGET_ALTIVEC && reload_completed
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&& gpr_or_gpr_p (operands[0], operands[1])"
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&& gpr_or_gpr_p (operands[0], operands[1])"
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[(pc)]
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[(pc)]
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{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
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{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
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|
|
(define_split
|
(define_split
|
[(set (match_operand:V4SF 0 "nonimmediate_operand" "")
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[(set (match_operand:V4SF 0 "nonimmediate_operand" "")
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(match_operand:V4SF 1 "input_operand" ""))]
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(match_operand:V4SF 1 "input_operand" ""))]
|
"TARGET_ALTIVEC && reload_completed
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"TARGET_ALTIVEC && reload_completed
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&& gpr_or_gpr_p (operands[0], operands[1])"
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&& gpr_or_gpr_p (operands[0], operands[1])"
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[(pc)]
|
[(pc)]
|
{
|
{
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rs6000_split_multireg_move (operands[0], operands[1]); DONE;
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rs6000_split_multireg_move (operands[0], operands[1]); DONE;
|
})
|
})
|
|
|
(define_split
|
(define_split
|
[(set (match_operand:VI 0 "altivec_register_operand" "")
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[(set (match_operand:VI 0 "altivec_register_operand" "")
|
(match_operand:VI 1 "easy_vector_constant_add_self" ""))]
|
(match_operand:VI 1 "easy_vector_constant_add_self" ""))]
|
"TARGET_ALTIVEC && reload_completed"
|
"TARGET_ALTIVEC && reload_completed"
|
[(set (match_dup 0) (match_dup 3))
|
[(set (match_dup 0) (match_dup 3))
|
(set (match_dup 0) (plus:VI (match_dup 0)
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(set (match_dup 0) (plus:VI (match_dup 0)
|
(match_dup 0)))]
|
(match_dup 0)))]
|
{
|
{
|
rtx dup = gen_easy_altivec_constant (operands[1]);
|
rtx dup = gen_easy_altivec_constant (operands[1]);
|
rtx const_vec;
|
rtx const_vec;
|
|
|
/* Divide the operand of the resulting VEC_DUPLICATE, and use
|
/* Divide the operand of the resulting VEC_DUPLICATE, and use
|
simplify_rtx to make a CONST_VECTOR. */
|
simplify_rtx to make a CONST_VECTOR. */
|
XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
|
XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
|
XEXP (dup, 0), const1_rtx);
|
XEXP (dup, 0), const1_rtx);
|
const_vec = simplify_rtx (dup);
|
const_vec = simplify_rtx (dup);
|
|
|
if (GET_MODE (const_vec) == mode)
|
if (GET_MODE (const_vec) == mode)
|
operands[3] = const_vec;
|
operands[3] = const_vec;
|
else
|
else
|
operands[3] = gen_lowpart (mode, const_vec);
|
operands[3] = gen_lowpart (mode, const_vec);
|
})
|
})
|
|
|
(define_insn "get_vrsave_internal"
|
(define_insn "get_vrsave_internal"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
|
(unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
if (TARGET_MACHO)
|
if (TARGET_MACHO)
|
return "mfspr %0,256";
|
return "mfspr %0,256";
|
else
|
else
|
return "mfvrsave %0";
|
return "mfvrsave %0";
|
}
|
}
|
[(set_attr "type" "*")])
|
[(set_attr "type" "*")])
|
|
|
(define_insn "*set_vrsave_internal"
|
(define_insn "*set_vrsave_internal"
|
[(match_parallel 0 "vrsave_operation"
|
[(match_parallel 0 "vrsave_operation"
|
[(set (reg:SI 109)
|
[(set (reg:SI 109)
|
(unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
|
(unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
|
(reg:SI 109)] UNSPECV_SET_VRSAVE))])]
|
(reg:SI 109)] UNSPECV_SET_VRSAVE))])]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
if (TARGET_MACHO)
|
if (TARGET_MACHO)
|
return "mtspr 256,%1";
|
return "mtspr 256,%1";
|
else
|
else
|
return "mtvrsave %1";
|
return "mtvrsave %1";
|
}
|
}
|
[(set_attr "type" "*")])
|
[(set_attr "type" "*")])
|
|
|
(define_insn "*save_world"
|
(define_insn "*save_world"
|
[(match_parallel 0 "save_world_operation"
|
[(match_parallel 0 "save_world_operation"
|
[(clobber (match_operand:SI 1 "register_operand" "=l"))
|
[(clobber (match_operand:SI 1 "register_operand" "=l"))
|
(use (match_operand:SI 2 "call_operand" "s"))])]
|
(use (match_operand:SI 2 "call_operand" "s"))])]
|
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
|
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
|
"bl %z2"
|
"bl %z2"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "*restore_world"
|
(define_insn "*restore_world"
|
[(match_parallel 0 "restore_world_operation"
|
[(match_parallel 0 "restore_world_operation"
|
[(return)
|
[(return)
|
(use (match_operand:SI 1 "register_operand" "l"))
|
(use (match_operand:SI 1 "register_operand" "l"))
|
(use (match_operand:SI 2 "call_operand" "s"))
|
(use (match_operand:SI 2 "call_operand" "s"))
|
(clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
|
(clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
|
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
|
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
|
"b %z2")
|
"b %z2")
|
|
|
;; Simple binary operations.
|
;; Simple binary operations.
|
|
|
;; add
|
;; add
|
(define_insn "add3"
|
(define_insn "add3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(plus:VI (match_operand:VI 1 "register_operand" "v")
|
(plus:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")))]
|
(match_operand:VI 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vaddum %0,%1,%2"
|
"vaddum %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "addv4sf3"
|
(define_insn "addv4sf3"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vaddfp %0,%1,%2"
|
"vaddfp %0,%1,%2"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vaddcuw"
|
(define_insn "altivec_vaddcuw"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VADDCUW))]
|
UNSPEC_VADDCUW))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vaddcuw %0,%1,%2"
|
"vaddcuw %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vaddus"
|
(define_insn "altivec_vaddus"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")]
|
(match_operand:VI 2 "register_operand" "v")]
|
UNSPEC_VADDU))
|
UNSPEC_VADDU))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vaddus %0,%1,%2"
|
"vaddus %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vaddss"
|
(define_insn "altivec_vaddss"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")]
|
(match_operand:VI 2 "register_operand" "v")]
|
UNSPEC_VADDS))
|
UNSPEC_VADDS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vaddss %0,%1,%2"
|
"vaddss %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
;; sub
|
;; sub
|
(define_insn "sub3"
|
(define_insn "sub3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(minus:VI (match_operand:VI 1 "register_operand" "v")
|
(minus:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")))]
|
(match_operand:VI 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsubum %0,%1,%2"
|
"vsubum %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "subv4sf3"
|
(define_insn "subv4sf3"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsubfp %0,%1,%2"
|
"vsubfp %0,%1,%2"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vsubcuw"
|
(define_insn "altivec_vsubcuw"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSUBCUW))]
|
UNSPEC_VSUBCUW))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsubcuw %0,%1,%2"
|
"vsubcuw %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vsubus"
|
(define_insn "altivec_vsubus"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")]
|
(match_operand:VI 2 "register_operand" "v")]
|
UNSPEC_VSUBU))
|
UNSPEC_VSUBU))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsubus %0,%1,%2"
|
"vsubus %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vsubss"
|
(define_insn "altivec_vsubss"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")]
|
(match_operand:VI 2 "register_operand" "v")]
|
UNSPEC_VSUBS))
|
UNSPEC_VSUBS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsubss %0,%1,%2"
|
"vsubss %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
;;
|
;;
|
(define_insn "altivec_vavgu"
|
(define_insn "altivec_vavgu"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")]
|
(match_operand:VI 2 "register_operand" "v")]
|
UNSPEC_VAVGU))]
|
UNSPEC_VAVGU))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vavgu %0,%1,%2"
|
"vavgu %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vavgs"
|
(define_insn "altivec_vavgs"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")]
|
(match_operand:VI 2 "register_operand" "v")]
|
UNSPEC_VAVGS))]
|
UNSPEC_VAVGS))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vavgs %0,%1,%2"
|
"vavgs %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpbfp"
|
(define_insn "altivec_vcmpbfp"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")]
|
(match_operand:V4SF 2 "register_operand" "v")]
|
UNSPEC_VCMPBFP))]
|
UNSPEC_VCMPBFP))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpbfp %0,%1,%2"
|
"vcmpbfp %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "altivec_vcmpequb"
|
(define_insn "altivec_vcmpequb"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")]
|
(match_operand:V16QI 2 "register_operand" "v")]
|
UNSPEC_VCMPEQUB))]
|
UNSPEC_VCMPEQUB))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpequb %0,%1,%2"
|
"vcmpequb %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpequh"
|
(define_insn "altivec_vcmpequh"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VCMPEQUH))]
|
UNSPEC_VCMPEQUH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpequh %0,%1,%2"
|
"vcmpequh %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpequw"
|
(define_insn "altivec_vcmpequw"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VCMPEQUW))]
|
UNSPEC_VCMPEQUW))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpequw %0,%1,%2"
|
"vcmpequw %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpeqfp"
|
(define_insn "altivec_vcmpeqfp"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")]
|
(match_operand:V4SF 2 "register_operand" "v")]
|
UNSPEC_VCMPEQFP))]
|
UNSPEC_VCMPEQFP))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpeqfp %0,%1,%2"
|
"vcmpeqfp %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "altivec_vcmpgefp"
|
(define_insn "altivec_vcmpgefp"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")]
|
(match_operand:V4SF 2 "register_operand" "v")]
|
UNSPEC_VCMPGEFP))]
|
UNSPEC_VCMPGEFP))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpgefp %0,%1,%2"
|
"vcmpgefp %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "altivec_vcmpgtub"
|
(define_insn "altivec_vcmpgtub"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")]
|
(match_operand:V16QI 2 "register_operand" "v")]
|
UNSPEC_VCMPGTUB))]
|
UNSPEC_VCMPGTUB))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpgtub %0,%1,%2"
|
"vcmpgtub %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpgtsb"
|
(define_insn "altivec_vcmpgtsb"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")]
|
(match_operand:V16QI 2 "register_operand" "v")]
|
UNSPEC_VCMPGTSB))]
|
UNSPEC_VCMPGTSB))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpgtsb %0,%1,%2"
|
"vcmpgtsb %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpgtuh"
|
(define_insn "altivec_vcmpgtuh"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VCMPGTUH))]
|
UNSPEC_VCMPGTUH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpgtuh %0,%1,%2"
|
"vcmpgtuh %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpgtsh"
|
(define_insn "altivec_vcmpgtsh"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VCMPGTSH))]
|
UNSPEC_VCMPGTSH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpgtsh %0,%1,%2"
|
"vcmpgtsh %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpgtuw"
|
(define_insn "altivec_vcmpgtuw"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VCMPGTUW))]
|
UNSPEC_VCMPGTUW))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpgtuw %0,%1,%2"
|
"vcmpgtuw %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpgtsw"
|
(define_insn "altivec_vcmpgtsw"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VCMPGTSW))]
|
UNSPEC_VCMPGTSW))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpgtsw %0,%1,%2"
|
"vcmpgtsw %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vcmpgtfp"
|
(define_insn "altivec_vcmpgtfp"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")]
|
(match_operand:V4SF 2 "register_operand" "v")]
|
UNSPEC_VCMPGTFP))]
|
UNSPEC_VCMPGTFP))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcmpgtfp %0,%1,%2"
|
"vcmpgtfp %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
;; Fused multiply add
|
;; Fused multiply add
|
(define_insn "altivec_vmaddfp"
|
(define_insn "altivec_vmaddfp"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v"))
|
(match_operand:V4SF 2 "register_operand" "v"))
|
(match_operand:V4SF 3 "register_operand" "v")))]
|
(match_operand:V4SF 3 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmaddfp %0,%1,%2,%3"
|
"vmaddfp %0,%1,%2,%3"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
|
;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
|
|
|
(define_expand "mulv4sf3"
|
(define_expand "mulv4sf3"
|
[(use (match_operand:V4SF 0 "register_operand" ""))
|
[(use (match_operand:V4SF 0 "register_operand" ""))
|
(use (match_operand:V4SF 1 "register_operand" ""))
|
(use (match_operand:V4SF 1 "register_operand" ""))
|
(use (match_operand:V4SF 2 "register_operand" ""))]
|
(use (match_operand:V4SF 2 "register_operand" ""))]
|
"TARGET_ALTIVEC && TARGET_FUSED_MADD"
|
"TARGET_ALTIVEC && TARGET_FUSED_MADD"
|
"
|
"
|
{
|
{
|
rtx neg0;
|
rtx neg0;
|
|
|
/* Generate [-0.0, -0.0, -0.0, -0.0]. */
|
/* Generate [-0.0, -0.0, -0.0, -0.0]. */
|
neg0 = gen_reg_rtx (V4SImode);
|
neg0 = gen_reg_rtx (V4SImode);
|
emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
|
emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
|
emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
|
emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
|
|
|
/* Use the multiply-add. */
|
/* Use the multiply-add. */
|
emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
|
emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
|
gen_lowpart (V4SFmode, neg0)));
|
gen_lowpart (V4SFmode, neg0)));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
;; 32 bit integer multiplication
|
;; 32 bit integer multiplication
|
;; A_high = Operand_0 & 0xFFFF0000 >> 16
|
;; A_high = Operand_0 & 0xFFFF0000 >> 16
|
;; A_low = Operand_0 & 0xFFFF
|
;; A_low = Operand_0 & 0xFFFF
|
;; B_high = Operand_1 & 0xFFFF0000 >> 16
|
;; B_high = Operand_1 & 0xFFFF0000 >> 16
|
;; B_low = Operand_1 & 0xFFFF
|
;; B_low = Operand_1 & 0xFFFF
|
;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
|
;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
|
|
|
;; (define_insn "mulv4si3"
|
;; (define_insn "mulv4si3"
|
;; [(set (match_operand:V4SI 0 "register_operand" "=v")
|
;; [(set (match_operand:V4SI 0 "register_operand" "=v")
|
;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
|
;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
|
;; (match_operand:V4SI 2 "register_operand" "v")))]
|
;; (match_operand:V4SI 2 "register_operand" "v")))]
|
(define_expand "mulv4si3"
|
(define_expand "mulv4si3"
|
[(use (match_operand:V4SI 0 "register_operand" ""))
|
[(use (match_operand:V4SI 0 "register_operand" ""))
|
(use (match_operand:V4SI 1 "register_operand" ""))
|
(use (match_operand:V4SI 1 "register_operand" ""))
|
(use (match_operand:V4SI 2 "register_operand" ""))]
|
(use (match_operand:V4SI 2 "register_operand" ""))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx zero;
|
rtx zero;
|
rtx swap;
|
rtx swap;
|
rtx small_swap;
|
rtx small_swap;
|
rtx sixteen;
|
rtx sixteen;
|
rtx one;
|
rtx one;
|
rtx two;
|
rtx two;
|
rtx low_product;
|
rtx low_product;
|
rtx high_product;
|
rtx high_product;
|
|
|
zero = gen_reg_rtx (V4SImode);
|
zero = gen_reg_rtx (V4SImode);
|
emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
|
emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
|
|
|
sixteen = gen_reg_rtx (V4SImode);
|
sixteen = gen_reg_rtx (V4SImode);
|
emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
|
emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
|
|
|
swap = gen_reg_rtx (V4SImode);
|
swap = gen_reg_rtx (V4SImode);
|
emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
|
emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
|
|
|
one = gen_reg_rtx (V8HImode);
|
one = gen_reg_rtx (V8HImode);
|
convert_move (one, operands[1], 0);
|
convert_move (one, operands[1], 0);
|
|
|
two = gen_reg_rtx (V8HImode);
|
two = gen_reg_rtx (V8HImode);
|
convert_move (two, operands[2], 0);
|
convert_move (two, operands[2], 0);
|
|
|
small_swap = gen_reg_rtx (V8HImode);
|
small_swap = gen_reg_rtx (V8HImode);
|
convert_move (small_swap, swap, 0);
|
convert_move (small_swap, swap, 0);
|
|
|
low_product = gen_reg_rtx (V4SImode);
|
low_product = gen_reg_rtx (V4SImode);
|
emit_insn (gen_altivec_vmulouh (low_product, one, two));
|
emit_insn (gen_altivec_vmulouh (low_product, one, two));
|
|
|
high_product = gen_reg_rtx (V4SImode);
|
high_product = gen_reg_rtx (V4SImode);
|
emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
|
emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
|
|
|
emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
|
emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
|
|
|
emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
|
emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
|
|
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
|
|
;; Fused multiply subtract
|
;; Fused multiply subtract
|
(define_insn "altivec_vnmsubfp"
|
(define_insn "altivec_vnmsubfp"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v"))
|
(match_operand:V4SF 2 "register_operand" "v"))
|
(match_operand:V4SF 3 "register_operand" "v"))))]
|
(match_operand:V4SF 3 "register_operand" "v"))))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vnmsubfp %0,%1,%2,%3"
|
"vnmsubfp %0,%1,%2,%3"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vmsumum"
|
(define_insn "altivec_vmsumum"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
|
(match_operand:VIshort 2 "register_operand" "v")
|
(match_operand:VIshort 2 "register_operand" "v")
|
(match_operand:V4SI 3 "register_operand" "v")]
|
(match_operand:V4SI 3 "register_operand" "v")]
|
UNSPEC_VMSUMU))]
|
UNSPEC_VMSUMU))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmsumum %0,%1,%2,%3"
|
"vmsumum %0,%1,%2,%3"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmsummm"
|
(define_insn "altivec_vmsummm"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
|
(match_operand:VIshort 2 "register_operand" "v")
|
(match_operand:VIshort 2 "register_operand" "v")
|
(match_operand:V4SI 3 "register_operand" "v")]
|
(match_operand:V4SI 3 "register_operand" "v")]
|
UNSPEC_VMSUMM))]
|
UNSPEC_VMSUMM))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmsummm %0,%1,%2,%3"
|
"vmsummm %0,%1,%2,%3"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmsumshm"
|
(define_insn "altivec_vmsumshm"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V4SI 3 "register_operand" "v")]
|
(match_operand:V4SI 3 "register_operand" "v")]
|
UNSPEC_VMSUMSHM))]
|
UNSPEC_VMSUMSHM))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmsumshm %0,%1,%2,%3"
|
"vmsumshm %0,%1,%2,%3"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmsumuhs"
|
(define_insn "altivec_vmsumuhs"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V4SI 3 "register_operand" "v")]
|
(match_operand:V4SI 3 "register_operand" "v")]
|
UNSPEC_VMSUMUHS))
|
UNSPEC_VMSUMUHS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmsumuhs %0,%1,%2,%3"
|
"vmsumuhs %0,%1,%2,%3"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmsumshs"
|
(define_insn "altivec_vmsumshs"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V4SI 3 "register_operand" "v")]
|
(match_operand:V4SI 3 "register_operand" "v")]
|
UNSPEC_VMSUMSHS))
|
UNSPEC_VMSUMSHS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmsumshs %0,%1,%2,%3"
|
"vmsumshs %0,%1,%2,%3"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
;; max
|
;; max
|
|
|
(define_insn "umax3"
|
(define_insn "umax3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(umax:VI (match_operand:VI 1 "register_operand" "v")
|
(umax:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")))]
|
(match_operand:VI 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmaxu %0,%1,%2"
|
"vmaxu %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "smax3"
|
(define_insn "smax3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(smax:VI (match_operand:VI 1 "register_operand" "v")
|
(smax:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")))]
|
(match_operand:VI 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmaxs %0,%1,%2"
|
"vmaxs %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "smaxv4sf3"
|
(define_insn "smaxv4sf3"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmaxfp %0,%1,%2"
|
"vmaxfp %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "umin3"
|
(define_insn "umin3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(umin:VI (match_operand:VI 1 "register_operand" "v")
|
(umin:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")))]
|
(match_operand:VI 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vminu %0,%1,%2"
|
"vminu %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "smin3"
|
(define_insn "smin3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(smin:VI (match_operand:VI 1 "register_operand" "v")
|
(smin:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")))]
|
(match_operand:VI 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmins %0,%1,%2"
|
"vmins %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "sminv4sf3"
|
(define_insn "sminv4sf3"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vminfp %0,%1,%2"
|
"vminfp %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "altivec_vmhaddshs"
|
(define_insn "altivec_vmhaddshs"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 3 "register_operand" "v")]
|
(match_operand:V8HI 3 "register_operand" "v")]
|
UNSPEC_VMHADDSHS))
|
UNSPEC_VMHADDSHS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmhaddshs %0,%1,%2,%3"
|
"vmhaddshs %0,%1,%2,%3"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmhraddshs"
|
(define_insn "altivec_vmhraddshs"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 3 "register_operand" "v")]
|
(match_operand:V8HI 3 "register_operand" "v")]
|
UNSPEC_VMHRADDSHS))
|
UNSPEC_VMHRADDSHS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmhraddshs %0,%1,%2,%3"
|
"vmhraddshs %0,%1,%2,%3"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmladduhm"
|
(define_insn "altivec_vmladduhm"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 3 "register_operand" "v")]
|
(match_operand:V8HI 3 "register_operand" "v")]
|
UNSPEC_VMLADDUHM))]
|
UNSPEC_VMLADDUHM))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmladduhm %0,%1,%2,%3"
|
"vmladduhm %0,%1,%2,%3"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmrghb"
|
(define_insn "altivec_vmrghb"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
|
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
|
(parallel [(const_int 0)
|
(parallel [(const_int 0)
|
(const_int 8)
|
(const_int 8)
|
(const_int 1)
|
(const_int 1)
|
(const_int 9)
|
(const_int 9)
|
(const_int 2)
|
(const_int 2)
|
(const_int 10)
|
(const_int 10)
|
(const_int 3)
|
(const_int 3)
|
(const_int 11)
|
(const_int 11)
|
(const_int 4)
|
(const_int 4)
|
(const_int 12)
|
(const_int 12)
|
(const_int 5)
|
(const_int 5)
|
(const_int 13)
|
(const_int 13)
|
(const_int 6)
|
(const_int 6)
|
(const_int 14)
|
(const_int 14)
|
(const_int 7)
|
(const_int 7)
|
(const_int 15)]))
|
(const_int 15)]))
|
(vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
|
(vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
|
(parallel [(const_int 8)
|
(parallel [(const_int 8)
|
(const_int 0)
|
(const_int 0)
|
(const_int 9)
|
(const_int 9)
|
(const_int 1)
|
(const_int 1)
|
(const_int 10)
|
(const_int 10)
|
(const_int 2)
|
(const_int 2)
|
(const_int 11)
|
(const_int 11)
|
(const_int 3)
|
(const_int 3)
|
(const_int 12)
|
(const_int 12)
|
(const_int 4)
|
(const_int 4)
|
(const_int 13)
|
(const_int 13)
|
(const_int 5)
|
(const_int 5)
|
(const_int 14)
|
(const_int 14)
|
(const_int 6)
|
(const_int 6)
|
(const_int 15)
|
(const_int 15)
|
(const_int 7)]))
|
(const_int 7)]))
|
(const_int 21845)))]
|
(const_int 21845)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmrghb %0,%1,%2"
|
"vmrghb %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vmrghh"
|
(define_insn "altivec_vmrghh"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
|
(vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
|
(parallel [(const_int 0)
|
(parallel [(const_int 0)
|
(const_int 4)
|
(const_int 4)
|
(const_int 1)
|
(const_int 1)
|
(const_int 5)
|
(const_int 5)
|
(const_int 2)
|
(const_int 2)
|
(const_int 6)
|
(const_int 6)
|
(const_int 3)
|
(const_int 3)
|
(const_int 7)]))
|
(const_int 7)]))
|
(vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
|
(vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
|
(parallel [(const_int 4)
|
(parallel [(const_int 4)
|
(const_int 0)
|
(const_int 0)
|
(const_int 5)
|
(const_int 5)
|
(const_int 1)
|
(const_int 1)
|
(const_int 6)
|
(const_int 6)
|
(const_int 2)
|
(const_int 2)
|
(const_int 7)
|
(const_int 7)
|
(const_int 3)]))
|
(const_int 3)]))
|
(const_int 85)))]
|
(const_int 85)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmrghh %0,%1,%2"
|
"vmrghh %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vmrghw"
|
(define_insn "altivec_vmrghw"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
|
(vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
|
(parallel [(const_int 0)
|
(parallel [(const_int 0)
|
(const_int 2)
|
(const_int 2)
|
(const_int 1)
|
(const_int 1)
|
(const_int 3)]))
|
(const_int 3)]))
|
(vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(parallel [(const_int 2)
|
(parallel [(const_int 2)
|
(const_int 0)
|
(const_int 0)
|
(const_int 3)
|
(const_int 3)
|
(const_int 1)]))
|
(const_int 1)]))
|
(const_int 5)))]
|
(const_int 5)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmrghw %0,%1,%2"
|
"vmrghw %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vmrglb"
|
(define_insn "altivec_vmrglb"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
|
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
|
(parallel [(const_int 8)
|
(parallel [(const_int 8)
|
(const_int 0)
|
(const_int 0)
|
(const_int 9)
|
(const_int 9)
|
(const_int 1)
|
(const_int 1)
|
(const_int 10)
|
(const_int 10)
|
(const_int 2)
|
(const_int 2)
|
(const_int 11)
|
(const_int 11)
|
(const_int 3)
|
(const_int 3)
|
(const_int 12)
|
(const_int 12)
|
(const_int 4)
|
(const_int 4)
|
(const_int 13)
|
(const_int 13)
|
(const_int 5)
|
(const_int 5)
|
(const_int 14)
|
(const_int 14)
|
(const_int 6)
|
(const_int 6)
|
(const_int 15)
|
(const_int 15)
|
(const_int 7)]))
|
(const_int 7)]))
|
(vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
|
(vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
|
(parallel [(const_int 0)
|
(parallel [(const_int 0)
|
(const_int 8)
|
(const_int 8)
|
(const_int 1)
|
(const_int 1)
|
(const_int 9)
|
(const_int 9)
|
(const_int 2)
|
(const_int 2)
|
(const_int 10)
|
(const_int 10)
|
(const_int 3)
|
(const_int 3)
|
(const_int 11)
|
(const_int 11)
|
(const_int 4)
|
(const_int 4)
|
(const_int 12)
|
(const_int 12)
|
(const_int 5)
|
(const_int 5)
|
(const_int 13)
|
(const_int 13)
|
(const_int 6)
|
(const_int 6)
|
(const_int 14)
|
(const_int 14)
|
(const_int 7)
|
(const_int 7)
|
(const_int 15)]))
|
(const_int 15)]))
|
(const_int 21845)))]
|
(const_int 21845)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmrglb %0,%1,%2"
|
"vmrglb %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vmrglh"
|
(define_insn "altivec_vmrglh"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
|
(vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
|
(parallel [(const_int 4)
|
(parallel [(const_int 4)
|
(const_int 0)
|
(const_int 0)
|
(const_int 5)
|
(const_int 5)
|
(const_int 1)
|
(const_int 1)
|
(const_int 6)
|
(const_int 6)
|
(const_int 2)
|
(const_int 2)
|
(const_int 7)
|
(const_int 7)
|
(const_int 3)]))
|
(const_int 3)]))
|
(vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
|
(vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
|
(parallel [(const_int 0)
|
(parallel [(const_int 0)
|
(const_int 4)
|
(const_int 4)
|
(const_int 1)
|
(const_int 1)
|
(const_int 5)
|
(const_int 5)
|
(const_int 2)
|
(const_int 2)
|
(const_int 6)
|
(const_int 6)
|
(const_int 3)
|
(const_int 3)
|
(const_int 7)]))
|
(const_int 7)]))
|
(const_int 85)))]
|
(const_int 85)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmrglh %0,%1,%2"
|
"vmrglh %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vmrglw"
|
(define_insn "altivec_vmrglw"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
|
(vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
|
(parallel [(const_int 2)
|
(parallel [(const_int 2)
|
(const_int 0)
|
(const_int 0)
|
(const_int 3)
|
(const_int 3)
|
(const_int 1)]))
|
(const_int 1)]))
|
(vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(parallel [(const_int 0)
|
(parallel [(const_int 0)
|
(const_int 2)
|
(const_int 2)
|
(const_int 1)
|
(const_int 1)
|
(const_int 3)]))
|
(const_int 3)]))
|
(const_int 5)))]
|
(const_int 5)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmrglw %0,%1,%2"
|
"vmrglw %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vmuleub"
|
(define_insn "altivec_vmuleub"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")]
|
(match_operand:V16QI 2 "register_operand" "v")]
|
UNSPEC_VMULEUB))]
|
UNSPEC_VMULEUB))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmuleub %0,%1,%2"
|
"vmuleub %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmulesb"
|
(define_insn "altivec_vmulesb"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")]
|
(match_operand:V16QI 2 "register_operand" "v")]
|
UNSPEC_VMULESB))]
|
UNSPEC_VMULESB))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmulesb %0,%1,%2"
|
"vmulesb %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmuleuh"
|
(define_insn "altivec_vmuleuh"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VMULEUH))]
|
UNSPEC_VMULEUH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmuleuh %0,%1,%2"
|
"vmuleuh %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmulesh"
|
(define_insn "altivec_vmulesh"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VMULESH))]
|
UNSPEC_VMULESH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmulesh %0,%1,%2"
|
"vmulesh %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmuloub"
|
(define_insn "altivec_vmuloub"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")]
|
(match_operand:V16QI 2 "register_operand" "v")]
|
UNSPEC_VMULOUB))]
|
UNSPEC_VMULOUB))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmuloub %0,%1,%2"
|
"vmuloub %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmulosb"
|
(define_insn "altivec_vmulosb"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")]
|
(match_operand:V16QI 2 "register_operand" "v")]
|
UNSPEC_VMULOSB))]
|
UNSPEC_VMULOSB))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmulosb %0,%1,%2"
|
"vmulosb %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmulouh"
|
(define_insn "altivec_vmulouh"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VMULOUH))]
|
UNSPEC_VMULOUH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmulouh %0,%1,%2"
|
"vmulouh %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vmulosh"
|
(define_insn "altivec_vmulosh"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VMULOSH))]
|
UNSPEC_VMULOSH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vmulosh %0,%1,%2"
|
"vmulosh %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
|
|
;; logical ops
|
;; logical ops
|
|
|
(define_insn "and3"
|
(define_insn "and3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(and:VI (match_operand:VI 1 "register_operand" "v")
|
(and:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")))]
|
(match_operand:VI 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vand %0,%1,%2"
|
"vand %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "ior3"
|
(define_insn "ior3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(ior:VI (match_operand:VI 1 "register_operand" "v")
|
(ior:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")))]
|
(match_operand:VI 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vor %0,%1,%2"
|
"vor %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "xor3"
|
(define_insn "xor3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(xor:VI (match_operand:VI 1 "register_operand" "v")
|
(xor:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")))]
|
(match_operand:VI 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vxor %0,%1,%2"
|
"vxor %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "xorv4sf3"
|
(define_insn "xorv4sf3"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(xor:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(xor:V4SF (match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
(match_operand:V4SF 2 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vxor %0,%1,%2"
|
"vxor %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "one_cmpl2"
|
(define_insn "one_cmpl2"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(not:VI (match_operand:VI 1 "register_operand" "v")))]
|
(not:VI (match_operand:VI 1 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vnor %0,%1,%1"
|
"vnor %0,%1,%1"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_nor3"
|
(define_insn "altivec_nor3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
|
(not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v"))))]
|
(match_operand:VI 2 "register_operand" "v"))))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vnor %0,%1,%2"
|
"vnor %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "andc3"
|
(define_insn "andc3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
|
(and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
|
(match_operand:VI 1 "register_operand" "v")))]
|
(match_operand:VI 1 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vandc %0,%1,%2"
|
"vandc %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "*andc3_v4sf"
|
(define_insn "*andc3_v4sf"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
|
(and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
|
(match_operand:V4SF 1 "register_operand" "v")))]
|
(match_operand:V4SF 1 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vandc %0,%1,%2"
|
"vandc %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vpkuhum"
|
(define_insn "altivec_vpkuhum"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VPKUHUM))]
|
UNSPEC_VPKUHUM))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vpkuhum %0,%1,%2"
|
"vpkuhum %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vpkuwum"
|
(define_insn "altivec_vpkuwum"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VPKUWUM))]
|
UNSPEC_VPKUWUM))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vpkuwum %0,%1,%2"
|
"vpkuwum %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vpkpx"
|
(define_insn "altivec_vpkpx"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VPKPX))]
|
UNSPEC_VPKPX))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vpkpx %0,%1,%2"
|
"vpkpx %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vpkshss"
|
(define_insn "altivec_vpkshss"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VPKSHSS))
|
UNSPEC_VPKSHSS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vpkshss %0,%1,%2"
|
"vpkshss %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vpkswss"
|
(define_insn "altivec_vpkswss"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VPKSWSS))
|
UNSPEC_VPKSWSS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vpkswss %0,%1,%2"
|
"vpkswss %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vpkuhus"
|
(define_insn "altivec_vpkuhus"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VPKUHUS))
|
UNSPEC_VPKUHUS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vpkuhus %0,%1,%2"
|
"vpkuhus %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vpkshus"
|
(define_insn "altivec_vpkshus"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VPKSHUS))
|
UNSPEC_VPKSHUS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vpkshus %0,%1,%2"
|
"vpkshus %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vpkuwus"
|
(define_insn "altivec_vpkuwus"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VPKUWUS))
|
UNSPEC_VPKUWUS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vpkuwus %0,%1,%2"
|
"vpkuwus %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vpkswus"
|
(define_insn "altivec_vpkswus"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VPKSWUS))
|
UNSPEC_VPKSWUS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vpkswus %0,%1,%2"
|
"vpkswus %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vrl"
|
(define_insn "altivec_vrl"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")]
|
(match_operand:VI 2 "register_operand" "v")]
|
UNSPEC_VRL))]
|
UNSPEC_VRL))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vrl %0,%1,%2"
|
"vrl %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vsl"
|
(define_insn "altivec_vsl"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v")]
|
(match_operand:VI 2 "register_operand" "v")]
|
UNSPEC_VSL))]
|
UNSPEC_VSL))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsl %0,%1,%2"
|
"vsl %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vsl"
|
(define_insn "altivec_vsl"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSLV4SI))]
|
UNSPEC_VSLV4SI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsl %0,%1,%2"
|
"vsl %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vslo"
|
(define_insn "altivec_vslo"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSLO))]
|
UNSPEC_VSLO))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vslo %0,%1,%2"
|
"vslo %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "lshr3"
|
(define_insn "lshr3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
|
(lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v") ))]
|
(match_operand:VI 2 "register_operand" "v") ))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsr %0,%1,%2"
|
"vsr %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "ashr3"
|
(define_insn "ashr3"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
|
(ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
|
(match_operand:VI 2 "register_operand" "v") ))]
|
(match_operand:VI 2 "register_operand" "v") ))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsra %0,%1,%2"
|
"vsra %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_vsr"
|
(define_insn "altivec_vsr"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSR))]
|
UNSPEC_VSR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsr %0,%1,%2"
|
"vsr %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vsro"
|
(define_insn "altivec_vsro"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSRO))]
|
UNSPEC_VSRO))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsro %0,%1,%2"
|
"vsro %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vsum4ubs"
|
(define_insn "altivec_vsum4ubs"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSUM4UBS))
|
UNSPEC_VSUM4UBS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsum4ubs %0,%1,%2"
|
"vsum4ubs %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vsum4ss"
|
(define_insn "altivec_vsum4ss"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSUM4S))
|
UNSPEC_VSUM4S))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsum4ss %0,%1,%2"
|
"vsum4ss %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vsum2sws"
|
(define_insn "altivec_vsum2sws"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSUM2SWS))
|
UNSPEC_VSUM2SWS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsum2sws %0,%1,%2"
|
"vsum2sws %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vsumsws"
|
(define_insn "altivec_vsumsws"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSUMSWS))
|
UNSPEC_VSUMSWS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsumsws %0,%1,%2"
|
"vsumsws %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_insn "altivec_vspltb"
|
(define_insn "altivec_vspltb"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(vec_duplicate:V16QI
|
(vec_duplicate:V16QI
|
(vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
|
(vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
|
(parallel
|
(parallel
|
[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
|
[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vspltb %0,%1,%2"
|
"vspltb %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vsplth"
|
(define_insn "altivec_vsplth"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(vec_duplicate:V8HI
|
(vec_duplicate:V8HI
|
(vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
|
(vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
|
(parallel
|
(parallel
|
[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
|
[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsplth %0,%1,%2"
|
"vsplth %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vspltw"
|
(define_insn "altivec_vspltw"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(vec_duplicate:V4SI
|
(vec_duplicate:V4SI
|
(vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
|
(vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
|
(parallel
|
(parallel
|
[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
|
[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vspltw %0,%1,%2"
|
"vspltw %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "*altivec_vspltsf"
|
(define_insn "*altivec_vspltsf"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(vec_duplicate:V4SF
|
(vec_duplicate:V4SF
|
(vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
|
(vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
|
(parallel
|
(parallel
|
[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
|
[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vspltw %0,%1,%2"
|
"vspltw %0,%1,%2"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vspltis"
|
(define_insn "altivec_vspltis"
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(vec_duplicate:VI
|
(vec_duplicate:VI
|
(match_operand:QI 1 "s5bit_cint_operand" "i")))]
|
(match_operand:QI 1 "s5bit_cint_operand" "i")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vspltis %0,%1"
|
"vspltis %0,%1"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "ftruncv4sf2"
|
(define_insn "ftruncv4sf2"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
|
(fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vrfiz %0,%1"
|
"vrfiz %0,%1"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vperm_"
|
(define_insn "altivec_vperm_"
|
[(set (match_operand:V 0 "register_operand" "=v")
|
[(set (match_operand:V 0 "register_operand" "=v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(match_operand:V 2 "register_operand" "v")
|
(match_operand:V 2 "register_operand" "v")
|
(match_operand:V16QI 3 "register_operand" "v")]
|
(match_operand:V16QI 3 "register_operand" "v")]
|
UNSPEC_VPERM))]
|
UNSPEC_VPERM))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vperm %0,%1,%2,%3"
|
"vperm %0,%1,%2,%3"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vrfip"
|
(define_insn "altivec_vrfip"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
UNSPEC_VRFIP))]
|
UNSPEC_VRFIP))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vrfip %0,%1"
|
"vrfip %0,%1"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vrfin"
|
(define_insn "altivec_vrfin"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
UNSPEC_VRFIN))]
|
UNSPEC_VRFIN))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vrfin %0,%1"
|
"vrfin %0,%1"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vrfim"
|
(define_insn "altivec_vrfim"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
UNSPEC_VRFIM))]
|
UNSPEC_VRFIM))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vrfim %0,%1"
|
"vrfim %0,%1"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vcfux"
|
(define_insn "altivec_vcfux"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:QI 2 "immediate_operand" "i")]
|
(match_operand:QI 2 "immediate_operand" "i")]
|
UNSPEC_VCFUX))]
|
UNSPEC_VCFUX))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcfux %0,%1,%2"
|
"vcfux %0,%1,%2"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vcfsx"
|
(define_insn "altivec_vcfsx"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:QI 2 "immediate_operand" "i")]
|
(match_operand:QI 2 "immediate_operand" "i")]
|
UNSPEC_VCFSX))]
|
UNSPEC_VCFSX))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vcfsx %0,%1,%2"
|
"vcfsx %0,%1,%2"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vctuxs"
|
(define_insn "altivec_vctuxs"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:QI 2 "immediate_operand" "i")]
|
(match_operand:QI 2 "immediate_operand" "i")]
|
UNSPEC_VCTUXS))
|
UNSPEC_VCTUXS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vctuxs %0,%1,%2"
|
"vctuxs %0,%1,%2"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vctsxs"
|
(define_insn "altivec_vctsxs"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:QI 2 "immediate_operand" "i")]
|
(match_operand:QI 2 "immediate_operand" "i")]
|
UNSPEC_VCTSXS))
|
UNSPEC_VCTSXS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vctsxs %0,%1,%2"
|
"vctsxs %0,%1,%2"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vlogefp"
|
(define_insn "altivec_vlogefp"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
UNSPEC_VLOGEFP))]
|
UNSPEC_VLOGEFP))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vlogefp %0,%1"
|
"vlogefp %0,%1"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vexptefp"
|
(define_insn "altivec_vexptefp"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
UNSPEC_VEXPTEFP))]
|
UNSPEC_VEXPTEFP))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vexptefp %0,%1"
|
"vexptefp %0,%1"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vrsqrtefp"
|
(define_insn "altivec_vrsqrtefp"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
UNSPEC_VRSQRTEFP))]
|
UNSPEC_VRSQRTEFP))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vrsqrtefp %0,%1"
|
"vrsqrtefp %0,%1"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_insn "altivec_vrefp"
|
(define_insn "altivec_vrefp"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
|
UNSPEC_VREFP))]
|
UNSPEC_VREFP))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vrefp %0,%1"
|
"vrefp %0,%1"
|
[(set_attr "type" "vecfloat")])
|
[(set_attr "type" "vecfloat")])
|
|
|
(define_expand "vcondv4si"
|
(define_expand "vcondv4si"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")
|
(match_operand:V4SI 3 "comparison_operator" "")
|
(match_operand:V4SI 3 "comparison_operator" "")
|
(match_operand:V4SI 4 "register_operand" "v")
|
(match_operand:V4SI 4 "register_operand" "v")
|
(match_operand:V4SI 5 "register_operand" "v")
|
(match_operand:V4SI 5 "register_operand" "v")
|
] UNSPEC_VCOND_V4SI))]
|
] UNSPEC_VCOND_V4SI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}
|
}
|
")
|
")
|
|
|
(define_expand "vconduv4si"
|
(define_expand "vconduv4si"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")
|
(match_operand:V4SI 3 "comparison_operator" "")
|
(match_operand:V4SI 3 "comparison_operator" "")
|
(match_operand:V4SI 4 "register_operand" "v")
|
(match_operand:V4SI 4 "register_operand" "v")
|
(match_operand:V4SI 5 "register_operand" "v")
|
(match_operand:V4SI 5 "register_operand" "v")
|
] UNSPEC_VCONDU_V4SI))]
|
] UNSPEC_VCONDU_V4SI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}
|
}
|
")
|
")
|
|
|
(define_expand "vcondv4sf"
|
(define_expand "vcondv4sf"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")
|
(match_operand:V4SF 3 "comparison_operator" "")
|
(match_operand:V4SF 3 "comparison_operator" "")
|
(match_operand:V4SF 4 "register_operand" "v")
|
(match_operand:V4SF 4 "register_operand" "v")
|
(match_operand:V4SF 5 "register_operand" "v")
|
(match_operand:V4SF 5 "register_operand" "v")
|
] UNSPEC_VCOND_V4SF))]
|
] UNSPEC_VCOND_V4SF))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}
|
}
|
")
|
")
|
|
|
(define_expand "vcondv8hi"
|
(define_expand "vcondv8hi"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 3 "comparison_operator" "")
|
(match_operand:V8HI 3 "comparison_operator" "")
|
(match_operand:V8HI 4 "register_operand" "v")
|
(match_operand:V8HI 4 "register_operand" "v")
|
(match_operand:V8HI 5 "register_operand" "v")
|
(match_operand:V8HI 5 "register_operand" "v")
|
] UNSPEC_VCOND_V8HI))]
|
] UNSPEC_VCOND_V8HI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}
|
}
|
")
|
")
|
|
|
(define_expand "vconduv8hi"
|
(define_expand "vconduv8hi"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 3 "comparison_operator" "")
|
(match_operand:V8HI 3 "comparison_operator" "")
|
(match_operand:V8HI 4 "register_operand" "v")
|
(match_operand:V8HI 4 "register_operand" "v")
|
(match_operand:V8HI 5 "register_operand" "v")
|
(match_operand:V8HI 5 "register_operand" "v")
|
] UNSPEC_VCONDU_V8HI))]
|
] UNSPEC_VCONDU_V8HI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}
|
}
|
")
|
")
|
|
|
(define_expand "vcondv16qi"
|
(define_expand "vcondv16qi"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")
|
(match_operand:V16QI 3 "comparison_operator" "")
|
(match_operand:V16QI 3 "comparison_operator" "")
|
(match_operand:V16QI 4 "register_operand" "v")
|
(match_operand:V16QI 4 "register_operand" "v")
|
(match_operand:V16QI 5 "register_operand" "v")
|
(match_operand:V16QI 5 "register_operand" "v")
|
] UNSPEC_VCOND_V16QI))]
|
] UNSPEC_VCOND_V16QI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}
|
}
|
")
|
")
|
|
|
(define_expand "vconduv16qi"
|
(define_expand "vconduv16qi"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")
|
(match_operand:V16QI 3 "comparison_operator" "")
|
(match_operand:V16QI 3 "comparison_operator" "")
|
(match_operand:V16QI 4 "register_operand" "v")
|
(match_operand:V16QI 4 "register_operand" "v")
|
(match_operand:V16QI 5 "register_operand" "v")
|
(match_operand:V16QI 5 "register_operand" "v")
|
] UNSPEC_VCONDU_V16QI))]
|
] UNSPEC_VCONDU_V16QI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}
|
}
|
")
|
")
|
|
|
|
|
(define_insn "altivec_vsel_v4si"
|
(define_insn "altivec_vsel_v4si"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")
|
(match_operand:V4SI 3 "register_operand" "v")]
|
(match_operand:V4SI 3 "register_operand" "v")]
|
UNSPEC_VSEL4SI))]
|
UNSPEC_VSEL4SI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsel %0,%1,%2,%3"
|
"vsel %0,%1,%2,%3"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vsel_v4sf"
|
(define_insn "altivec_vsel_v4sf"
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
|
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")
|
(match_operand:V4SF 2 "register_operand" "v")
|
(match_operand:V4SI 3 "register_operand" "v")]
|
(match_operand:V4SI 3 "register_operand" "v")]
|
UNSPEC_VSEL4SF))]
|
UNSPEC_VSEL4SF))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsel %0,%1,%2,%3"
|
"vsel %0,%1,%2,%3"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vsel_v8hi"
|
(define_insn "altivec_vsel_v8hi"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")
|
(match_operand:V8HI 3 "register_operand" "v")]
|
(match_operand:V8HI 3 "register_operand" "v")]
|
UNSPEC_VSEL8HI))]
|
UNSPEC_VSEL8HI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsel %0,%1,%2,%3"
|
"vsel %0,%1,%2,%3"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vsel_v16qi"
|
(define_insn "altivec_vsel_v16qi"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")
|
(match_operand:V16QI 2 "register_operand" "v")
|
(match_operand:V16QI 3 "register_operand" "v")]
|
(match_operand:V16QI 3 "register_operand" "v")]
|
UNSPEC_VSEL16QI))]
|
UNSPEC_VSEL16QI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsel %0,%1,%2,%3"
|
"vsel %0,%1,%2,%3"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vsldoi_"
|
(define_insn "altivec_vsldoi_"
|
[(set (match_operand:V 0 "register_operand" "=v")
|
[(set (match_operand:V 0 "register_operand" "=v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(match_operand:V 2 "register_operand" "v")
|
(match_operand:V 2 "register_operand" "v")
|
(match_operand:QI 3 "immediate_operand" "i")]
|
(match_operand:QI 3 "immediate_operand" "i")]
|
UNSPEC_VLSDOI))]
|
UNSPEC_VLSDOI))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsldoi %0,%1,%2,%3"
|
"vsldoi %0,%1,%2,%3"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vupkhsb"
|
(define_insn "altivec_vupkhsb"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
|
UNSPEC_VUPKHSB))]
|
UNSPEC_VUPKHSB))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vupkhsb %0,%1"
|
"vupkhsb %0,%1"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vupkhpx"
|
(define_insn "altivec_vupkhpx"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
UNSPEC_VUPKHPX))]
|
UNSPEC_VUPKHPX))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vupkhpx %0,%1"
|
"vupkhpx %0,%1"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vupkhsh"
|
(define_insn "altivec_vupkhsh"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
UNSPEC_VUPKHSH))]
|
UNSPEC_VUPKHSH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vupkhsh %0,%1"
|
"vupkhsh %0,%1"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vupklsb"
|
(define_insn "altivec_vupklsb"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
|
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
|
UNSPEC_VUPKLSB))]
|
UNSPEC_VUPKLSB))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vupklsb %0,%1"
|
"vupklsb %0,%1"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vupklpx"
|
(define_insn "altivec_vupklpx"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
UNSPEC_VUPKLPX))]
|
UNSPEC_VUPKLPX))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vupklpx %0,%1"
|
"vupklpx %0,%1"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_insn "altivec_vupklsh"
|
(define_insn "altivec_vupklsh"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
UNSPEC_VUPKLSH))]
|
UNSPEC_VUPKLSH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vupklsh %0,%1"
|
"vupklsh %0,%1"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
;; AltiVec predicates.
|
;; AltiVec predicates.
|
|
|
(define_expand "cr6_test_for_zero"
|
(define_expand "cr6_test_for_zero"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(eq:SI (reg:CC 74)
|
(eq:SI (reg:CC 74)
|
(const_int 0)))]
|
(const_int 0)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"")
|
"")
|
|
|
(define_expand "cr6_test_for_zero_reverse"
|
(define_expand "cr6_test_for_zero_reverse"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(eq:SI (reg:CC 74)
|
(eq:SI (reg:CC 74)
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
|
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"")
|
"")
|
|
|
(define_expand "cr6_test_for_lt"
|
(define_expand "cr6_test_for_lt"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(lt:SI (reg:CC 74)
|
(lt:SI (reg:CC 74)
|
(const_int 0)))]
|
(const_int 0)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"")
|
"")
|
|
|
(define_expand "cr6_test_for_lt_reverse"
|
(define_expand "cr6_test_for_lt_reverse"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(lt:SI (reg:CC 74)
|
(lt:SI (reg:CC 74)
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
|
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"")
|
"")
|
|
|
;; We can get away with generating the opcode on the fly (%3 below)
|
;; We can get away with generating the opcode on the fly (%3 below)
|
;; because all the predicates have the same scheduling parameters.
|
;; because all the predicates have the same scheduling parameters.
|
|
|
(define_insn "altivec_predicate_"
|
(define_insn "altivec_predicate_"
|
[(set (reg:CC 74)
|
[(set (reg:CC 74)
|
(unspec:CC [(match_operand:V 1 "register_operand" "v")
|
(unspec:CC [(match_operand:V 1 "register_operand" "v")
|
(match_operand:V 2 "register_operand" "v")
|
(match_operand:V 2 "register_operand" "v")
|
(match_operand 3 "any_operand" "")] UNSPEC_PREDICATE))
|
(match_operand 3 "any_operand" "")] UNSPEC_PREDICATE))
|
(clobber (match_scratch:V 0 "=v"))]
|
(clobber (match_scratch:V 0 "=v"))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"%3 %0,%1,%2"
|
"%3 %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "altivec_mtvscr"
|
(define_insn "altivec_mtvscr"
|
[(set (reg:SI 110)
|
[(set (reg:SI 110)
|
(unspec_volatile:SI
|
(unspec_volatile:SI
|
[(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
|
[(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"mtvscr %0"
|
"mtvscr %0"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_mfvscr"
|
(define_insn "altivec_mfvscr"
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
(unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
|
(unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"mfvscr %0"
|
"mfvscr %0"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_dssall"
|
(define_insn "altivec_dssall"
|
[(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
|
[(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"dssall"
|
"dssall"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_dss"
|
(define_insn "altivec_dss"
|
[(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
|
[(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
|
UNSPECV_DSS)]
|
UNSPECV_DSS)]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"dss %0"
|
"dss %0"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_dst"
|
(define_insn "altivec_dst"
|
[(unspec [(match_operand 0 "register_operand" "b")
|
[(unspec [(match_operand 0 "register_operand" "b")
|
(match_operand:SI 1 "register_operand" "r")
|
(match_operand:SI 1 "register_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
|
(match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
|
"TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
|
"TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
|
"dst %0,%1,%2"
|
"dst %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_dstt"
|
(define_insn "altivec_dstt"
|
[(unspec [(match_operand 0 "register_operand" "b")
|
[(unspec [(match_operand 0 "register_operand" "b")
|
(match_operand:SI 1 "register_operand" "r")
|
(match_operand:SI 1 "register_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
|
(match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
|
"TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
|
"TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
|
"dstt %0,%1,%2"
|
"dstt %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_dstst"
|
(define_insn "altivec_dstst"
|
[(unspec [(match_operand 0 "register_operand" "b")
|
[(unspec [(match_operand 0 "register_operand" "b")
|
(match_operand:SI 1 "register_operand" "r")
|
(match_operand:SI 1 "register_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
|
(match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
|
"TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
|
"TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
|
"dstst %0,%1,%2"
|
"dstst %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_dststt"
|
(define_insn "altivec_dststt"
|
[(unspec [(match_operand 0 "register_operand" "b")
|
[(unspec [(match_operand 0 "register_operand" "b")
|
(match_operand:SI 1 "register_operand" "r")
|
(match_operand:SI 1 "register_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
|
(match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
|
"TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
|
"TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
|
"dststt %0,%1,%2"
|
"dststt %0,%1,%2"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "altivec_lvsl"
|
(define_insn "altivec_lvsl"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
|
(unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"lvsl %0,%y1"
|
"lvsl %0,%y1"
|
[(set_attr "type" "vecload")])
|
[(set_attr "type" "vecload")])
|
|
|
(define_insn "altivec_lvsr"
|
(define_insn "altivec_lvsr"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
|
(unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"lvsr %0,%y1"
|
"lvsr %0,%y1"
|
[(set_attr "type" "vecload")])
|
[(set_attr "type" "vecload")])
|
|
|
(define_expand "build_vector_mask_for_load"
|
(define_expand "build_vector_mask_for_load"
|
[(set (match_operand:V16QI 0 "register_operand" "")
|
[(set (match_operand:V16QI 0 "register_operand" "")
|
(unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
|
(unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx addr;
|
rtx addr;
|
rtx temp;
|
rtx temp;
|
|
|
gcc_assert (GET_CODE (operands[1]) == MEM);
|
gcc_assert (GET_CODE (operands[1]) == MEM);
|
|
|
addr = XEXP (operands[1], 0);
|
addr = XEXP (operands[1], 0);
|
temp = gen_reg_rtx (GET_MODE (addr));
|
temp = gen_reg_rtx (GET_MODE (addr));
|
emit_insn (gen_rtx_SET (VOIDmode, temp,
|
emit_insn (gen_rtx_SET (VOIDmode, temp,
|
gen_rtx_NEG (GET_MODE (addr), addr)));
|
gen_rtx_NEG (GET_MODE (addr), addr)));
|
emit_insn (gen_altivec_lvsr (operands[0],
|
emit_insn (gen_altivec_lvsr (operands[0],
|
replace_equiv_address (operands[1], temp)));
|
replace_equiv_address (operands[1], temp)));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
;; Parallel some of the LVE* and STV*'s with unspecs because some have
|
;; Parallel some of the LVE* and STV*'s with unspecs because some have
|
;; identical rtl but different instructions-- and gcc gets confused.
|
;; identical rtl but different instructions-- and gcc gets confused.
|
|
|
(define_insn "altivec_lvex"
|
(define_insn "altivec_lvex"
|
[(parallel
|
[(parallel
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
[(set (match_operand:VI 0 "register_operand" "=v")
|
(match_operand:VI 1 "memory_operand" "Z"))
|
(match_operand:VI 1 "memory_operand" "Z"))
|
(unspec [(const_int 0)] UNSPEC_LVE)])]
|
(unspec [(const_int 0)] UNSPEC_LVE)])]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"lvex %0,%y1"
|
"lvex %0,%y1"
|
[(set_attr "type" "vecload")])
|
[(set_attr "type" "vecload")])
|
|
|
(define_insn "*altivec_lvesfx"
|
(define_insn "*altivec_lvesfx"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
(match_operand:V4SF 1 "memory_operand" "Z"))
|
(match_operand:V4SF 1 "memory_operand" "Z"))
|
(unspec [(const_int 0)] UNSPEC_LVE)])]
|
(unspec [(const_int 0)] UNSPEC_LVE)])]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"lvewx %0,%y1"
|
"lvewx %0,%y1"
|
[(set_attr "type" "vecload")])
|
[(set_attr "type" "vecload")])
|
|
|
(define_insn "altivec_lvxl"
|
(define_insn "altivec_lvxl"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(match_operand:V4SI 1 "memory_operand" "Z"))
|
(match_operand:V4SI 1 "memory_operand" "Z"))
|
(unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
|
(unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"lvxl %0,%y1"
|
"lvxl %0,%y1"
|
[(set_attr "type" "vecload")])
|
[(set_attr "type" "vecload")])
|
|
|
(define_insn "altivec_lvx"
|
(define_insn "altivec_lvx"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(match_operand:V4SI 1 "memory_operand" "Z"))]
|
(match_operand:V4SI 1 "memory_operand" "Z"))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"lvx %0,%y1"
|
"lvx %0,%y1"
|
[(set_attr "type" "vecload")])
|
[(set_attr "type" "vecload")])
|
|
|
(define_insn "altivec_stvx"
|
(define_insn "altivec_stvx"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V4SI 0 "memory_operand" "=Z")
|
[(set (match_operand:V4SI 0 "memory_operand" "=Z")
|
(match_operand:V4SI 1 "register_operand" "v"))
|
(match_operand:V4SI 1 "register_operand" "v"))
|
(unspec [(const_int 0)] UNSPEC_STVX)])]
|
(unspec [(const_int 0)] UNSPEC_STVX)])]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"stvx %1,%y0"
|
"stvx %1,%y0"
|
[(set_attr "type" "vecstore")])
|
[(set_attr "type" "vecstore")])
|
|
|
(define_insn "altivec_stvxl"
|
(define_insn "altivec_stvxl"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V4SI 0 "memory_operand" "=Z")
|
[(set (match_operand:V4SI 0 "memory_operand" "=Z")
|
(match_operand:V4SI 1 "register_operand" "v"))
|
(match_operand:V4SI 1 "register_operand" "v"))
|
(unspec [(const_int 0)] UNSPEC_STVXL)])]
|
(unspec [(const_int 0)] UNSPEC_STVXL)])]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"stvxl %1,%y0"
|
"stvxl %1,%y0"
|
[(set_attr "type" "vecstore")])
|
[(set_attr "type" "vecstore")])
|
|
|
(define_insn "altivec_stvex"
|
(define_insn "altivec_stvex"
|
[(parallel
|
[(parallel
|
[(set (match_operand:VI 0 "memory_operand" "=Z")
|
[(set (match_operand:VI 0 "memory_operand" "=Z")
|
(match_operand:VI 1 "register_operand" "v"))
|
(match_operand:VI 1 "register_operand" "v"))
|
(unspec [(const_int 0)] UNSPEC_STVE)])]
|
(unspec [(const_int 0)] UNSPEC_STVE)])]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"stvex %1,%y0"
|
"stvex %1,%y0"
|
[(set_attr "type" "vecstore")])
|
[(set_attr "type" "vecstore")])
|
|
|
(define_insn "*altivec_stvesfx"
|
(define_insn "*altivec_stvesfx"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V4SF 0 "memory_operand" "=Z")
|
[(set (match_operand:V4SF 0 "memory_operand" "=Z")
|
(match_operand:V4SF 1 "register_operand" "v"))
|
(match_operand:V4SF 1 "register_operand" "v"))
|
(unspec [(const_int 0)] UNSPEC_STVE)])]
|
(unspec [(const_int 0)] UNSPEC_STVE)])]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"stvewx %1,%y0"
|
"stvewx %1,%y0"
|
[(set_attr "type" "vecstore")])
|
[(set_attr "type" "vecstore")])
|
|
|
(define_expand "vec_init"
|
(define_expand "vec_init"
|
[(match_operand:V 0 "register_operand" "")
|
[(match_operand:V 0 "register_operand" "")
|
(match_operand 1 "" "")]
|
(match_operand 1 "" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
rs6000_expand_vector_init (operands[0], operands[1]);
|
rs6000_expand_vector_init (operands[0], operands[1]);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_setv4si"
|
(define_expand "vec_setv4si"
|
[(match_operand:V4SI 0 "register_operand" "")
|
[(match_operand:V4SI 0 "register_operand" "")
|
(match_operand:SI 1 "register_operand" "")
|
(match_operand:SI 1 "register_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_setv8hi"
|
(define_expand "vec_setv8hi"
|
[(match_operand:V8HI 0 "register_operand" "")
|
[(match_operand:V8HI 0 "register_operand" "")
|
(match_operand:HI 1 "register_operand" "")
|
(match_operand:HI 1 "register_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_setv16qi"
|
(define_expand "vec_setv16qi"
|
[(match_operand:V16QI 0 "register_operand" "")
|
[(match_operand:V16QI 0 "register_operand" "")
|
(match_operand:QI 1 "register_operand" "")
|
(match_operand:QI 1 "register_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_setv4sf"
|
(define_expand "vec_setv4sf"
|
[(match_operand:V4SF 0 "register_operand" "")
|
[(match_operand:V4SF 0 "register_operand" "")
|
(match_operand:SF 1 "register_operand" "")
|
(match_operand:SF 1 "register_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_extractv4si"
|
(define_expand "vec_extractv4si"
|
[(match_operand:SI 0 "register_operand" "")
|
[(match_operand:SI 0 "register_operand" "")
|
(match_operand:V4SI 1 "register_operand" "")
|
(match_operand:V4SI 1 "register_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
|
rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_extractv8hi"
|
(define_expand "vec_extractv8hi"
|
[(match_operand:HI 0 "register_operand" "")
|
[(match_operand:HI 0 "register_operand" "")
|
(match_operand:V8HI 1 "register_operand" "")
|
(match_operand:V8HI 1 "register_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
|
rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_extractv16qi"
|
(define_expand "vec_extractv16qi"
|
[(match_operand:QI 0 "register_operand" "")
|
[(match_operand:QI 0 "register_operand" "")
|
(match_operand:V16QI 1 "register_operand" "")
|
(match_operand:V16QI 1 "register_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
|
rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_extractv4sf"
|
(define_expand "vec_extractv4sf"
|
[(match_operand:SF 0 "register_operand" "")
|
[(match_operand:SF 0 "register_operand" "")
|
(match_operand:V4SF 1 "register_operand" "")
|
(match_operand:V4SF 1 "register_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
|
rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
;; Generate
|
;; Generate
|
;; vspltis? SCRATCH0,0
|
;; vspltis? SCRATCH0,0
|
;; vsubu?m SCRATCH2,SCRATCH1,%1
|
;; vsubu?m SCRATCH2,SCRATCH1,%1
|
;; vmaxs? %0,%1,SCRATCH2"
|
;; vmaxs? %0,%1,SCRATCH2"
|
(define_expand "abs2"
|
(define_expand "abs2"
|
[(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
|
[(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
|
(set (match_dup 3)
|
(set (match_dup 3)
|
(minus:VI (match_dup 2)
|
(minus:VI (match_dup 2)
|
(match_operand:VI 1 "register_operand" "v")))
|
(match_operand:VI 1 "register_operand" "v")))
|
(set (match_operand:VI 0 "register_operand" "=v")
|
(set (match_operand:VI 0 "register_operand" "=v")
|
(smax:VI (match_dup 1) (match_dup 3)))]
|
(smax:VI (match_dup 1) (match_dup 3)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
|
operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
|
operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
|
operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
|
})
|
})
|
|
|
;; Generate
|
;; Generate
|
;; vspltisw SCRATCH1,-1
|
;; vspltisw SCRATCH1,-1
|
;; vslw SCRATCH2,SCRATCH1,SCRATCH1
|
;; vslw SCRATCH2,SCRATCH1,SCRATCH1
|
;; vandc %0,%1,SCRATCH2
|
;; vandc %0,%1,SCRATCH2
|
(define_expand "absv4sf2"
|
(define_expand "absv4sf2"
|
[(set (match_dup 2)
|
[(set (match_dup 2)
|
(vec_duplicate:V4SI (const_int -1)))
|
(vec_duplicate:V4SI (const_int -1)))
|
(set (match_dup 3)
|
(set (match_dup 3)
|
(unspec:V4SI [(match_dup 2) (match_dup 2)] UNSPEC_VSL))
|
(unspec:V4SI [(match_dup 2) (match_dup 2)] UNSPEC_VSL))
|
(set (match_operand:V4SF 0 "register_operand" "=v")
|
(set (match_operand:V4SF 0 "register_operand" "=v")
|
(and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0))
|
(and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0))
|
(match_operand:V4SF 1 "register_operand" "v")))]
|
(match_operand:V4SF 1 "register_operand" "v")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
operands[2] = gen_reg_rtx (V4SImode);
|
operands[2] = gen_reg_rtx (V4SImode);
|
operands[3] = gen_reg_rtx (V4SImode);
|
operands[3] = gen_reg_rtx (V4SImode);
|
})
|
})
|
|
|
;; Generate
|
;; Generate
|
;; vspltis? SCRATCH0,0
|
;; vspltis? SCRATCH0,0
|
;; vsubs?s SCRATCH2,SCRATCH1,%1
|
;; vsubs?s SCRATCH2,SCRATCH1,%1
|
;; vmaxs? %0,%1,SCRATCH2"
|
;; vmaxs? %0,%1,SCRATCH2"
|
(define_expand "altivec_abss_"
|
(define_expand "altivec_abss_"
|
[(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
|
[(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
|
(parallel [(set (match_dup 3)
|
(parallel [(set (match_dup 3)
|
(unspec:VI [(match_dup 2)
|
(unspec:VI [(match_dup 2)
|
(match_operand:VI 1 "register_operand" "v")]
|
(match_operand:VI 1 "register_operand" "v")]
|
UNSPEC_VSUBS))
|
UNSPEC_VSUBS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
|
(set (match_operand:VI 0 "register_operand" "=v")
|
(set (match_operand:VI 0 "register_operand" "=v")
|
(smax:VI (match_dup 1) (match_dup 3)))]
|
(smax:VI (match_dup 1) (match_dup 3)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
{
|
{
|
operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
|
operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
|
operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
|
operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
|
})
|
})
|
|
|
;; Vector shift left in bits. Currently supported ony for shift
|
;; Vector shift left in bits. Currently supported ony for shift
|
;; amounts that can be expressed as byte shifts (divisible by 8).
|
;; amounts that can be expressed as byte shifts (divisible by 8).
|
;; General shift amounts can be supported using vslo + vsl. We're
|
;; General shift amounts can be supported using vslo + vsl. We're
|
;; not expecting to see these yet (the vectorizer currently
|
;; not expecting to see these yet (the vectorizer currently
|
;; generates only shifts divisible by byte_size).
|
;; generates only shifts divisible by byte_size).
|
(define_expand "vec_shl_"
|
(define_expand "vec_shl_"
|
[(set (match_operand:V 0 "register_operand" "=v")
|
[(set (match_operand:V 0 "register_operand" "=v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(match_operand:QI 2 "reg_or_short_operand" "")]
|
(match_operand:QI 2 "reg_or_short_operand" "")]
|
UNSPEC_VECSH))]
|
UNSPEC_VECSH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx bitshift = operands[2];
|
rtx bitshift = operands[2];
|
rtx byteshift = gen_reg_rtx (QImode);
|
rtx byteshift = gen_reg_rtx (QImode);
|
HOST_WIDE_INT bitshift_val;
|
HOST_WIDE_INT bitshift_val;
|
HOST_WIDE_INT byteshift_val;
|
HOST_WIDE_INT byteshift_val;
|
|
|
if (! CONSTANT_P (bitshift))
|
if (! CONSTANT_P (bitshift))
|
FAIL;
|
FAIL;
|
bitshift_val = INTVAL (bitshift);
|
bitshift_val = INTVAL (bitshift);
|
if (bitshift_val & 0x7)
|
if (bitshift_val & 0x7)
|
FAIL;
|
FAIL;
|
byteshift_val = bitshift_val >> 3;
|
byteshift_val = bitshift_val >> 3;
|
byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
|
byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
|
emit_insn (gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
|
emit_insn (gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
|
byteshift));
|
byteshift));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
;; Vector shift left in bits. Currently supported ony for shift
|
;; Vector shift left in bits. Currently supported ony for shift
|
;; amounts that can be expressed as byte shifts (divisible by 8).
|
;; amounts that can be expressed as byte shifts (divisible by 8).
|
;; General shift amounts can be supported using vsro + vsr. We're
|
;; General shift amounts can be supported using vsro + vsr. We're
|
;; not expecting to see these yet (the vectorizer currently
|
;; not expecting to see these yet (the vectorizer currently
|
;; generates only shifts divisible by byte_size).
|
;; generates only shifts divisible by byte_size).
|
(define_expand "vec_shr_"
|
(define_expand "vec_shr_"
|
[(set (match_operand:V 0 "register_operand" "=v")
|
[(set (match_operand:V 0 "register_operand" "=v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(match_operand:QI 2 "reg_or_short_operand" "")]
|
(match_operand:QI 2 "reg_or_short_operand" "")]
|
UNSPEC_VECSH))]
|
UNSPEC_VECSH))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx bitshift = operands[2];
|
rtx bitshift = operands[2];
|
rtx byteshift = gen_reg_rtx (QImode);
|
rtx byteshift = gen_reg_rtx (QImode);
|
HOST_WIDE_INT bitshift_val;
|
HOST_WIDE_INT bitshift_val;
|
HOST_WIDE_INT byteshift_val;
|
HOST_WIDE_INT byteshift_val;
|
|
|
if (! CONSTANT_P (bitshift))
|
if (! CONSTANT_P (bitshift))
|
FAIL;
|
FAIL;
|
bitshift_val = INTVAL (bitshift);
|
bitshift_val = INTVAL (bitshift);
|
if (bitshift_val & 0x7)
|
if (bitshift_val & 0x7)
|
FAIL;
|
FAIL;
|
byteshift_val = 16 - (bitshift_val >> 3);
|
byteshift_val = 16 - (bitshift_val >> 3);
|
byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
|
byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
|
emit_insn (gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
|
emit_insn (gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
|
byteshift));
|
byteshift));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "altivec_vsumsws_nomode"
|
(define_insn "altivec_vsumsws_nomode"
|
[(set (match_operand 0 "register_operand" "=v")
|
[(set (match_operand 0 "register_operand" "=v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
(match_operand:V4SI 2 "register_operand" "v")]
|
(match_operand:V4SI 2 "register_operand" "v")]
|
UNSPEC_VSUMSWS))
|
UNSPEC_VSUMSWS))
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vsumsws %0,%1,%2"
|
"vsumsws %0,%1,%2"
|
[(set_attr "type" "veccomplex")])
|
[(set_attr "type" "veccomplex")])
|
|
|
(define_expand "reduc_splus_"
|
(define_expand "reduc_splus_"
|
[(set (match_operand:VIshort 0 "register_operand" "=v")
|
[(set (match_operand:VIshort 0 "register_operand" "=v")
|
(unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
|
(unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
|
UNSPEC_REDUC_PLUS))]
|
UNSPEC_REDUC_PLUS))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx vzero = gen_reg_rtx (V4SImode);
|
rtx vzero = gen_reg_rtx (V4SImode);
|
rtx vtmp1 = gen_reg_rtx (V4SImode);
|
rtx vtmp1 = gen_reg_rtx (V4SImode);
|
|
|
emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
|
emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
|
emit_insn (gen_altivec_vsum4ss (vtmp1, operands[1], vzero));
|
emit_insn (gen_altivec_vsum4ss (vtmp1, operands[1], vzero));
|
emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
|
emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_expand "reduc_uplus_v16qi"
|
(define_expand "reduc_uplus_v16qi"
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
|
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
|
UNSPEC_REDUC_PLUS))]
|
UNSPEC_REDUC_PLUS))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx vzero = gen_reg_rtx (V4SImode);
|
rtx vzero = gen_reg_rtx (V4SImode);
|
rtx vtmp1 = gen_reg_rtx (V4SImode);
|
rtx vtmp1 = gen_reg_rtx (V4SImode);
|
|
|
emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
|
emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
|
emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
|
emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
|
emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
|
emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "vec_realign_load_"
|
(define_insn "vec_realign_load_"
|
[(set (match_operand:V 0 "register_operand" "=v")
|
[(set (match_operand:V 0 "register_operand" "=v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(unspec:V [(match_operand:V 1 "register_operand" "v")
|
(match_operand:V 2 "register_operand" "v")
|
(match_operand:V 2 "register_operand" "v")
|
(match_operand:V16QI 3 "register_operand" "v")]
|
(match_operand:V16QI 3 "register_operand" "v")]
|
UNSPEC_REALIGN_LOAD))]
|
UNSPEC_REALIGN_LOAD))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"vperm %0,%1,%2,%3"
|
"vperm %0,%1,%2,%3"
|
[(set_attr "type" "vecperm")])
|
[(set_attr "type" "vecperm")])
|
|
|
(define_expand "neg2"
|
(define_expand "neg2"
|
[(use (match_operand:VI 0 "register_operand" ""))
|
[(use (match_operand:VI 0 "register_operand" ""))
|
(use (match_operand:VI 1 "register_operand" ""))]
|
(use (match_operand:VI 1 "register_operand" ""))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx vzero;
|
rtx vzero;
|
|
|
vzero = gen_reg_rtx (GET_MODE (operands[0]));
|
vzero = gen_reg_rtx (GET_MODE (operands[0]));
|
emit_insn (gen_altivec_vspltis (vzero, const0_rtx));
|
emit_insn (gen_altivec_vspltis (vzero, const0_rtx));
|
emit_insn (gen_sub3 (operands[0], vzero, operands[1]));
|
emit_insn (gen_sub3 (operands[0], vzero, operands[1]));
|
|
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_expand "udot_prod"
|
(define_expand "udot_prod"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
|
(plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
|
(match_operand:VIshort 2 "register_operand" "v")]
|
(match_operand:VIshort 2 "register_operand" "v")]
|
UNSPEC_VMSUMU)))]
|
UNSPEC_VMSUMU)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
emit_insn (gen_altivec_vmsumum (operands[0], operands[1], operands[2], operands[3]));
|
emit_insn (gen_altivec_vmsumum (operands[0], operands[1], operands[2], operands[3]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_expand "sdot_prodv8hi"
|
(define_expand "sdot_prodv8hi"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
|
(plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
|
(match_operand:V8HI 2 "register_operand" "v")]
|
(match_operand:V8HI 2 "register_operand" "v")]
|
UNSPEC_VMSUMSHM)))]
|
UNSPEC_VMSUMSHM)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
|
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_expand "widen_usum3"
|
(define_expand "widen_usum3"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
|
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
|
UNSPEC_VMSUMU)))]
|
UNSPEC_VMSUMU)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
|
rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
|
|
|
emit_insn (gen_altivec_vspltis (vones, const1_rtx));
|
emit_insn (gen_altivec_vspltis (vones, const1_rtx));
|
emit_insn (gen_altivec_vmsumum (operands[0], operands[1], vones, operands[2]));
|
emit_insn (gen_altivec_vmsumum (operands[0], operands[1], vones, operands[2]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_expand "widen_ssumv16qi3"
|
(define_expand "widen_ssumv16qi3"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
|
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
|
UNSPEC_VMSUMM)))]
|
UNSPEC_VMSUMM)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx vones = gen_reg_rtx (V16QImode);
|
rtx vones = gen_reg_rtx (V16QImode);
|
|
|
emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
|
emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
|
emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
|
emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_expand "widen_ssumv8hi3"
|
(define_expand "widen_ssumv8hi3"
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
(plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
|
UNSPEC_VMSUMSHM)))]
|
UNSPEC_VMSUMSHM)))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx vones = gen_reg_rtx (V8HImode);
|
rtx vones = gen_reg_rtx (V8HImode);
|
|
|
emit_insn (gen_altivec_vspltish (vones, const1_rtx));
|
emit_insn (gen_altivec_vspltish (vones, const1_rtx));
|
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
|
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_expand "negv4sf2"
|
(define_expand "negv4sf2"
|
[(use (match_operand:V4SF 0 "register_operand" ""))
|
[(use (match_operand:V4SF 0 "register_operand" ""))
|
(use (match_operand:V4SF 1 "register_operand" ""))]
|
(use (match_operand:V4SF 1 "register_operand" ""))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx neg0;
|
rtx neg0;
|
|
|
/* Generate [-0.0, -0.0, -0.0, -0.0]. */
|
/* Generate [-0.0, -0.0, -0.0, -0.0]. */
|
neg0 = gen_reg_rtx (V4SImode);
|
neg0 = gen_reg_rtx (V4SImode);
|
emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
|
emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
|
emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
|
emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
|
|
|
/* XOR */
|
/* XOR */
|
emit_insn (gen_xorv4sf3 (operands[0],
|
emit_insn (gen_xorv4sf3 (operands[0],
|
gen_lowpart (V4SFmode, neg0), operands[1]));
|
gen_lowpart (V4SFmode, neg0), operands[1]));
|
|
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
