/* Machine description patterns for PowerPC running Darwin (Mac OS X).
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/* Machine description patterns for PowerPC running Darwin (Mac OS X).
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Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
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Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
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Contributed by Apple Computer Inc.
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Contributed by Apple Computer Inc.
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This file is part of GCC.
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This file is part of GCC.
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GNU CC is free software; you can redistribute it and/or modify
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; . */
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;; . */
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(define_insn "adddi3_high"
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(define_insn "adddi3_high"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
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(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(high:DI (match_operand 2 "" ""))))]
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(high:DI (match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_64BIT"
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"TARGET_MACHO && TARGET_64BIT"
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"{cau|addis} %0,%1,ha16(%2)"
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"{cau|addis} %0,%1,ha16(%2)"
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[(set_attr "length" "4")])
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[(set_attr "length" "4")])
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(define_insn "movdf_low_si"
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(define_insn "movdf_low_si"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
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"*
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"*
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0:
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case 0:
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return \"lfd %0,lo16(%2)(%1)\";
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return \"lfd %0,lo16(%2)(%1)\";
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case 1:
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case 1:
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{
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{
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if (TARGET_POWERPC64 && TARGET_32BIT)
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if (TARGET_POWERPC64 && TARGET_32BIT)
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/* Note, old assemblers didn't support relocation here. */
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/* Note, old assemblers didn't support relocation here. */
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return \"ld %0,lo16(%2)(%1)\";
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return \"ld %0,lo16(%2)(%1)\";
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else
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else
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{
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{
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output_asm_insn (\"{cal|la} %0,lo16(%2)(%1)\", operands);
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output_asm_insn (\"{cal|la} %0,lo16(%2)(%1)\", operands);
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output_asm_insn (\"{l|lwz} %L0,4(%0)\", operands);
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output_asm_insn (\"{l|lwz} %L0,4(%0)\", operands);
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return (\"{l|lwz} %0,0(%0)\");
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return (\"{l|lwz} %0,0(%0)\");
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}
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}
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}
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}
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default:
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default:
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gcc_unreachable ();
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gcc_unreachable ();
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}
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}
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}"
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}"
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[(set_attr "type" "load")
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[(set_attr "type" "load")
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(set_attr "length" "4,12")])
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(set_attr "length" "4,12")])
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(define_insn "movdf_low_di"
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(define_insn "movdf_low_di"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"*
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"*
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0:
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case 0:
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return \"lfd %0,lo16(%2)(%1)\";
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return \"lfd %0,lo16(%2)(%1)\";
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case 1:
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case 1:
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return \"ld %0,lo16(%2)(%1)\";
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return \"ld %0,lo16(%2)(%1)\";
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default:
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default:
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gcc_unreachable ();
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gcc_unreachable ();
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}
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}
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}"
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}"
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[(set_attr "type" "load")
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[(set_attr "type" "load")
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(set_attr "length" "4,4")])
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(set_attr "length" "4,4")])
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(define_insn "movdf_low_st_si"
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(define_insn "movdf_low_st_si"
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[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand 2 "" "")))
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(match_operand:DF 0 "gpc_reg_operand" "f"))]
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(match_operand:DF 0 "gpc_reg_operand" "f"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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"stfd %0,lo16(%2)(%1)"
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"stfd %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "movdf_low_st_di"
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(define_insn "movdf_low_st_di"
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[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand 2 "" "")))
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(match_operand:DF 0 "gpc_reg_operand" "f"))]
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(match_operand:DF 0 "gpc_reg_operand" "f"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"stfd %0,lo16(%2)(%1)"
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"stfd %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "movsf_low_si"
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(define_insn "movsf_low_si"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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"@
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"@
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lfs %0,lo16(%2)(%1)
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lfs %0,lo16(%2)(%1)
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{l|lwz} %0,lo16(%2)(%1)"
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{l|lwz} %0,lo16(%2)(%1)"
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[(set_attr "type" "load")
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "movsf_low_di"
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(define_insn "movsf_low_di"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"@
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"@
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lfs %0,lo16(%2)(%1)
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lfs %0,lo16(%2)(%1)
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{l|lwz} %0,lo16(%2)(%1)"
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{l|lwz} %0,lo16(%2)(%1)"
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[(set_attr "type" "load")
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "movsf_low_st_si"
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(define_insn "movsf_low_st_si"
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[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" "")))
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(match_operand 2 "" "")))
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(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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"@
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"@
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stfs %0,lo16(%2)(%1)
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stfs %0,lo16(%2)(%1)
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{st|stw} %0,lo16(%2)(%1)"
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{st|stw} %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "movsf_low_st_di"
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(define_insn "movsf_low_st_di"
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[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" "")))
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(match_operand 2 "" "")))
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(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"@
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"@
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stfs %0,lo16(%2)(%1)
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stfs %0,lo16(%2)(%1)
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{st|stw} %0,lo16(%2)(%1)"
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{st|stw} %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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;; 64-bit MachO load/store support
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;; 64-bit MachO load/store support
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(define_insn "movdi_low"
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(define_insn "movdi_low"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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(mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" ""))))]
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_64BIT"
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"TARGET_MACHO && TARGET_64BIT"
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"{l|ld} %0,lo16(%2)(%1)"
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"{l|ld} %0,lo16(%2)(%1)"
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[(set_attr "type" "load")
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "movsi_low_st"
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(define_insn "movsi_low_st"
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[(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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[(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand 2 "" "")))
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(match_operand:SI 0 "gpc_reg_operand" "r"))]
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(match_operand:SI 0 "gpc_reg_operand" "r"))]
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"TARGET_MACHO && ! TARGET_64BIT"
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"TARGET_MACHO && ! TARGET_64BIT"
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"{st|stw} %0,lo16(%2)(%1)"
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"{st|stw} %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "movdi_low_st"
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(define_insn "movdi_low_st"
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[(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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[(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand 2 "" "")))
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(match_operand:DI 0 "gpc_reg_operand" "r"))]
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(match_operand:DI 0 "gpc_reg_operand" "r"))]
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"TARGET_MACHO && TARGET_64BIT"
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"TARGET_MACHO && TARGET_64BIT"
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"{st|std} %0,lo16(%2)(%1)"
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"{st|std} %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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;; Mach-O PIC trickery.
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;; Mach-O PIC trickery.
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(define_expand "macho_high"
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(define_expand "macho_high"
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[(set (match_operand 0 "" "")
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[(set (match_operand 0 "" "")
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(high (match_operand 1 "" "")))]
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(high (match_operand 1 "" "")))]
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"TARGET_MACHO"
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"TARGET_MACHO"
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{
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{
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if (TARGET_64BIT)
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if (TARGET_64BIT)
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emit_insn (gen_macho_high_di (operands[0], operands[1]));
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emit_insn (gen_macho_high_di (operands[0], operands[1]));
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else
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else
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emit_insn (gen_macho_high_si (operands[0], operands[1]));
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emit_insn (gen_macho_high_si (operands[0], operands[1]));
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DONE;
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DONE;
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})
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})
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(define_insn "macho_high_si"
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(define_insn "macho_high_si"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
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(high:SI (match_operand 1 "" "")))]
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(high:SI (match_operand 1 "" "")))]
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"TARGET_MACHO && ! TARGET_64BIT"
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"TARGET_MACHO && ! TARGET_64BIT"
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"{liu|lis} %0,ha16(%1)")
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"{liu|lis} %0,ha16(%1)")
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(define_insn "macho_high_di"
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(define_insn "macho_high_di"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
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(high:DI (match_operand 1 "" "")))]
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(high:DI (match_operand 1 "" "")))]
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"TARGET_MACHO && TARGET_64BIT"
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"TARGET_MACHO && TARGET_64BIT"
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"{liu|lis} %0,ha16(%1)")
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"{liu|lis} %0,ha16(%1)")
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(define_expand "macho_low"
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(define_expand "macho_low"
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[(set (match_operand 0 "" "")
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[(set (match_operand 0 "" "")
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(lo_sum (match_operand 1 "" "")
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(lo_sum (match_operand 1 "" "")
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(match_operand 2 "" "")))]
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(match_operand 2 "" "")))]
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"TARGET_MACHO"
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"TARGET_MACHO"
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{
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{
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if (TARGET_64BIT)
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if (TARGET_64BIT)
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emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
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emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
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else
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else
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emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
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emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
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DONE;
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DONE;
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})
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})
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(define_insn "macho_low_si"
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(define_insn "macho_low_si"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
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(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
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(match_operand 2 "" "")))]
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(match_operand 2 "" "")))]
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"TARGET_MACHO && ! TARGET_64BIT"
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"TARGET_MACHO && ! TARGET_64BIT"
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"@
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"@
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{cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
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{cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
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{cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
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{cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
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(define_insn "macho_low_di"
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(define_insn "macho_low_di"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
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(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
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(match_operand 2 "" "")))]
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(match_operand 2 "" "")))]
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"TARGET_MACHO && TARGET_64BIT"
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"TARGET_MACHO && TARGET_64BIT"
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"@
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"@
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{cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
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{cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
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{cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
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{cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
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|
|
(define_split
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(define_split
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[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
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[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
|
(match_operand:DI 1 "short_cint_operand" "")))
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(match_operand:DI 1 "short_cint_operand" "")))
|
(match_operand:V4SI 2 "register_operand" ""))
|
(match_operand:V4SI 2 "register_operand" ""))
|
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
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(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
|
"TARGET_MACHO && TARGET_64BIT"
|
"TARGET_MACHO && TARGET_64BIT"
|
[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
|
[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
|
(set (mem:V4SI (match_dup 3))
|
(set (mem:V4SI (match_dup 3))
|
(match_dup 2))]
|
(match_dup 2))]
|
"")
|
"")
|
|
|
(define_expand "load_macho_picbase"
|
(define_expand "load_macho_picbase"
|
[(set (match_operand 0 "" "")
|
[(set (match_operand 0 "" "")
|
(unspec [(match_operand 1 "" "")]
|
(unspec [(match_operand 1 "" "")]
|
UNSPEC_LD_MPIC))]
|
UNSPEC_LD_MPIC))]
|
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
|
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
|
{
|
{
|
if (TARGET_32BIT)
|
if (TARGET_32BIT)
|
emit_insn (gen_load_macho_picbase_si (operands[0], operands[1]));
|
emit_insn (gen_load_macho_picbase_si (operands[0], operands[1]));
|
else
|
else
|
emit_insn (gen_load_macho_picbase_di (operands[0], operands[1]));
|
emit_insn (gen_load_macho_picbase_di (operands[0], operands[1]));
|
|
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "load_macho_picbase_si"
|
(define_insn "load_macho_picbase_si"
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
(unspec:SI [(match_operand:SI 1 "immediate_operand" "s")
|
(unspec:SI [(match_operand:SI 1 "immediate_operand" "s")
|
(pc)] UNSPEC_LD_MPIC))]
|
(pc)] UNSPEC_LD_MPIC))]
|
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
|
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
|
"bcl 20,31,%1\\n%1:"
|
"bcl 20,31,%1\\n%1:"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "load_macho_picbase_di"
|
(define_insn "load_macho_picbase_di"
|
[(set (match_operand:DI 0 "register_operand" "=l")
|
[(set (match_operand:DI 0 "register_operand" "=l")
|
(unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
|
(unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
|
(pc)] UNSPEC_LD_MPIC))]
|
(pc)] UNSPEC_LD_MPIC))]
|
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
|
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
|
"bcl 20,31,%1\\n%1:"
|
"bcl 20,31,%1\\n%1:"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_expand "macho_correct_pic"
|
(define_expand "macho_correct_pic"
|
[(set (match_operand 0 "" "")
|
[(set (match_operand 0 "" "")
|
(plus (match_operand 1 "" "")
|
(plus (match_operand 1 "" "")
|
(unspec [(match_operand 2 "" "")
|
(unspec [(match_operand 2 "" "")
|
(match_operand 3 "" "")]
|
(match_operand 3 "" "")]
|
UNSPEC_MPIC_CORRECT)))]
|
UNSPEC_MPIC_CORRECT)))]
|
"DEFAULT_ABI == ABI_DARWIN"
|
"DEFAULT_ABI == ABI_DARWIN"
|
{
|
{
|
if (TARGET_32BIT)
|
if (TARGET_32BIT)
|
emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
|
emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
|
operands[3]));
|
operands[3]));
|
else
|
else
|
emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
|
emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
|
operands[3]));
|
operands[3]));
|
|
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "macho_correct_pic_si"
|
(define_insn "macho_correct_pic_si"
|
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
|
(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
|
(unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
|
(unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
|
(match_operand:SI 3 "immediate_operand" "s")]
|
(match_operand:SI 3 "immediate_operand" "s")]
|
UNSPEC_MPIC_CORRECT)))]
|
UNSPEC_MPIC_CORRECT)))]
|
"DEFAULT_ABI == ABI_DARWIN"
|
"DEFAULT_ABI == ABI_DARWIN"
|
"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
|
"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
|
[(set_attr "length" "8")])
|
[(set_attr "length" "8")])
|
|
|
(define_insn "macho_correct_pic_di"
|
(define_insn "macho_correct_pic_di"
|
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
|
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
|
(unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
|
(unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
|
(match_operand:DI 3 "immediate_operand" "s")]
|
(match_operand:DI 3 "immediate_operand" "s")]
|
16)))]
|
16)))]
|
"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
|
"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
|
"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
|
"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
|
[(set_attr "length" "8")])
|
[(set_attr "length" "8")])
|
|
|
(define_insn "*call_indirect_nonlocal_darwin64"
|
(define_insn "*call_indirect_nonlocal_darwin64"
|
[(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
|
[(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
|
(match_operand 1 "" "g,g,g,g"))
|
(match_operand 1 "" "g,g,g,g"))
|
(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
|
(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
|
(clobber (match_scratch:SI 3 "=l,l,l,l"))]
|
(clobber (match_scratch:SI 3 "=l,l,l,l"))]
|
"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
|
"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
|
{
|
{
|
return "b%T0l";
|
return "b%T0l";
|
}
|
}
|
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
|
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
|
(set_attr "length" "4,4,8,8")])
|
(set_attr "length" "4,4,8,8")])
|
|
|
(define_insn "*call_nonlocal_darwin64"
|
(define_insn "*call_nonlocal_darwin64"
|
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
|
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
|
(match_operand 1 "" "g,g"))
|
(match_operand 1 "" "g,g"))
|
(use (match_operand:SI 2 "immediate_operand" "O,n"))
|
(use (match_operand:SI 2 "immediate_operand" "O,n"))
|
(clobber (match_scratch:SI 3 "=l,l"))]
|
(clobber (match_scratch:SI 3 "=l,l"))]
|
"(DEFAULT_ABI == ABI_DARWIN)
|
"(DEFAULT_ABI == ABI_DARWIN)
|
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
|
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
|
{
|
{
|
#if TARGET_MACHO
|
#if TARGET_MACHO
|
return output_call(insn, operands, 0, 2);
|
return output_call(insn, operands, 0, 2);
|
#else
|
#else
|
gcc_unreachable ();
|
gcc_unreachable ();
|
#endif
|
#endif
|
}
|
}
|
[(set_attr "type" "branch,branch")
|
[(set_attr "type" "branch,branch")
|
(set_attr "length" "4,8")])
|
(set_attr "length" "4,8")])
|
|
|
(define_insn "*call_value_indirect_nonlocal_darwin64"
|
(define_insn "*call_value_indirect_nonlocal_darwin64"
|
[(set (match_operand 0 "" "")
|
[(set (match_operand 0 "" "")
|
(call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
|
(call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
|
(match_operand 2 "" "g,g,g,g")))
|
(match_operand 2 "" "g,g,g,g")))
|
(use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
|
(use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
|
(clobber (match_scratch:SI 4 "=l,l,l,l"))]
|
(clobber (match_scratch:SI 4 "=l,l,l,l"))]
|
"DEFAULT_ABI == ABI_DARWIN"
|
"DEFAULT_ABI == ABI_DARWIN"
|
{
|
{
|
return "b%T1l";
|
return "b%T1l";
|
}
|
}
|
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
|
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
|
(set_attr "length" "4,4,8,8")])
|
(set_attr "length" "4,4,8,8")])
|
|
|
(define_insn "*call_value_nonlocal_darwin64"
|
(define_insn "*call_value_nonlocal_darwin64"
|
[(set (match_operand 0 "" "")
|
[(set (match_operand 0 "" "")
|
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
|
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
|
(match_operand 2 "" "g,g")))
|
(match_operand 2 "" "g,g")))
|
(use (match_operand:SI 3 "immediate_operand" "O,n"))
|
(use (match_operand:SI 3 "immediate_operand" "O,n"))
|
(clobber (match_scratch:SI 4 "=l,l"))]
|
(clobber (match_scratch:SI 4 "=l,l"))]
|
"(DEFAULT_ABI == ABI_DARWIN)
|
"(DEFAULT_ABI == ABI_DARWIN)
|
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
|
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
|
{
|
{
|
#if TARGET_MACHO
|
#if TARGET_MACHO
|
return output_call(insn, operands, 1, 3);
|
return output_call(insn, operands, 1, 3);
|
#else
|
#else
|
gcc_unreachable ();
|
gcc_unreachable ();
|
#endif
|
#endif
|
}
|
}
|
[(set_attr "type" "branch,branch")
|
[(set_attr "type" "branch,branch")
|
(set_attr "length" "4,8")])
|
(set_attr "length" "4,8")])
|
|
|
(define_insn "*sibcall_nonlocal_darwin64"
|
(define_insn "*sibcall_nonlocal_darwin64"
|
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
|
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(use (match_operand 2 "immediate_operand" "O,n"))
|
(use (match_operand 2 "immediate_operand" "O,n"))
|
(use (match_operand:SI 3 "register_operand" "l,l"))
|
(use (match_operand:SI 3 "register_operand" "l,l"))
|
(return)]
|
(return)]
|
"(DEFAULT_ABI == ABI_DARWIN)
|
"(DEFAULT_ABI == ABI_DARWIN)
|
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
|
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
|
{
|
{
|
return "b %z0";
|
return "b %z0";
|
}
|
}
|
[(set_attr "type" "branch,branch")
|
[(set_attr "type" "branch,branch")
|
(set_attr "length" "4,8")])
|
(set_attr "length" "4,8")])
|
|
|
(define_insn "*sibcall_value_nonlocal_darwin64"
|
(define_insn "*sibcall_value_nonlocal_darwin64"
|
[(set (match_operand 0 "" "")
|
[(set (match_operand 0 "" "")
|
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
|
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
|
(match_operand 2 "" "")))
|
(match_operand 2 "" "")))
|
(use (match_operand:SI 3 "immediate_operand" "O,n"))
|
(use (match_operand:SI 3 "immediate_operand" "O,n"))
|
(use (match_operand:SI 4 "register_operand" "l,l"))
|
(use (match_operand:SI 4 "register_operand" "l,l"))
|
(return)]
|
(return)]
|
"(DEFAULT_ABI == ABI_DARWIN)
|
"(DEFAULT_ABI == ABI_DARWIN)
|
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
|
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
|
"*
|
"*
|
{
|
{
|
return \"b %z1\";
|
return \"b %z1\";
|
}"
|
}"
|
[(set_attr "type" "branch,branch")
|
[(set_attr "type" "branch,branch")
|
(set_attr "length" "4,8")])
|
(set_attr "length" "4,8")])
|
|
|
|
|
(define_insn "*sibcall_symbolic_64"
|
(define_insn "*sibcall_symbolic_64"
|
[(call (mem:SI (match_operand:DI 0 "call_operand" "s,c")) ; 64
|
[(call (mem:SI (match_operand:DI 0 "call_operand" "s,c")) ; 64
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(use (match_operand 2 "" ""))
|
(use (match_operand 2 "" ""))
|
(use (match_operand:SI 3 "register_operand" "l,l"))
|
(use (match_operand:SI 3 "register_operand" "l,l"))
|
(return)]
|
(return)]
|
"TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
|
"TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
|
"*
|
"*
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"b %z0\";
|
case 0: return \"b %z0\";
|
case 1: return \"b%T0\";
|
case 1: return \"b%T0\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}"
|
}"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "*sibcall_value_symbolic_64"
|
(define_insn "*sibcall_value_symbolic_64"
|
[(set (match_operand 0 "" "")
|
[(set (match_operand 0 "" "")
|
(call (mem:SI (match_operand:DI 1 "call_operand" "s,c"))
|
(call (mem:SI (match_operand:DI 1 "call_operand" "s,c"))
|
(match_operand 2 "" "")))
|
(match_operand 2 "" "")))
|
(use (match_operand:SI 3 "" ""))
|
(use (match_operand:SI 3 "" ""))
|
(use (match_operand:SI 4 "register_operand" "l,l"))
|
(use (match_operand:SI 4 "register_operand" "l,l"))
|
(return)]
|
(return)]
|
"TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
|
"TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
|
"*
|
"*
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"b %z1\";
|
case 0: return \"b %z1\";
|
case 1: return \"b%T1\";
|
case 1: return \"b%T1\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}"
|
}"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
|
|
